PIC18F47J53 Family Data Sheet 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC18F47J53 FAMILY 28/44-Pin, High-Performance USB MCUs with nanoWatt XLP Technology Universal Serial Bus Features: Peripheral Highlights: • USB V2.0 Compliant • Low Speed (1.
USB RTCC CTMU PMP/PSP Deep Sleep Comparators 10/12-Bit A/D (Ch) SPI w/DMA I2C™ MSSP EUSART ECCP/(PWM) Timers 8/16-Bit Remappable Pins SRAM (bytes) Pins PIC18F Device Program Memory (bytes) PIC18F47J53 FAMILY PIC18F26J53 28 64K 3.8K* 16 4/4 3/7 2 2 Y Y 10 3 Y N Y Y Y PIC18F27J53 28 128K 3.8K* 16 4/4 3/7 2 2 Y Y 10 3 Y N Y Y Y PIC18F46J53 44 64K 3.8K* 22 4/4 3/7 2 2 Y Y 13 3 Y Y Y Y Y PIC18F47J53 44 128K 3.
PIC18F47J53 FAMILY RA1/AN1/C2INA/VBG/RP1 RA0/AN0/C1INA/ULPWU/RP0 MCLR RB7/CCP7/KBI3/PGD/RP10 RB6/CCP6/KBI2/PGC/RP9 RB5/CCP5/KBI1/SDI1/SDA1/RP8 RB4/CCP4/KBI0/SCK1/SCL1/RP7 Pin Diagrams 28-Pin QFN 28 27 26 25 24 23 22 1 2 3 4 5 6 7 PIC18F2XJ53 8 9 10 11 12 13 14 21 20 19 18 17 16 15 RB3/AN9/C3INA/CTED2/VPO/RP6 RB2/AN8/C2INC/CTED1/VMO/REFO/RP5 RB1/AN10/C3INC/RTCC/RP4 RB0/AN12/C3IND/INT0/RP3 VDD VSS2 RC7/CCP10/RX1/DT1/SDO1/RP18 RC0/T1OSO/T1CKI/RP11 RC1/CCP8/T1OSI/UOE/RP12 RC2/AN11/C2IND/CTPLS/RP13 VUSB
PIC18F47J53 FAMILY RC6/CCP9/PMA5/TX1/CK1/RP17 RC5/D+/VP RC4/D-/VM RD3/PMD3/RP20 RD2/PMD2/RP19 RD1/PMD1/SDA2 RD0/PMD0/SCL2 VUSB RC2/AN11/C2IND/CTPLS/RP13 RC1/CCP8/T1OSI/UOE/RP12 RC0/T1OSO/T1CKI/RP11 Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 44-Pin QFN PIC18F4XJ53 33 32 31 30 29 28 27 26 25 24 23 OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS2 AVSS1 VDD2 AVDD2 RE2/AN7/PMCS RE1/AN6/PMWR RE0/AN5/PMRD RA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2 VDDCORE/VCAP 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11
PIC18F47J53 FAMILY Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 RC6/CCP9/PMA5/TX1/CK1/RP17 RC5/D+/VP RC4/D-/VM RD3/PMD3/RP20 RD2/PMD2/RP19 RD1/PMD1/SDA2 RD0/PMD0/SCL2 VUSB RC2/AN11/C2IND/CTPLS/RP13 RC1/CCP8/T1OSI/UOE/RP12 NC 44-Pin TQFP(2) PIC18F4XJ53 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 NC RC0/T1OSO/T1CKI/RP11 OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS2 VDD2 RE2/AN7/PMCS RE1/AN6/PMWR RE0/AN5/PMRD RA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2 VDDCORE/VCAP N
PIC18F47J53 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 31 3.0 Oscillator Configurations .....................................................................................
PIC18F47J53 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC18F47J53 FAMILY NOTES: DS39964B-page 10 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 1.0 DEVICE OVERVIEW 1.1.3 This document contains device-specific information for the following devices: • PIC18F26J53 • PIC18LF26J53 • PIC18F27J53 • PIC18LF27J53 • PIC18F46J53 • PIC18LF46J53 • PIC18F47J53 • PIC18LF47J53 This family introduces a new line of low-voltage Universal Serial Bus (USB) microcontrollers with the main traditional advantage of all PIC18 microcontrollers, namely, high computational performance and a rich feature set at an extremely competitive price point.
PIC18F47J53 FAMILY 1.1.5 EXTENDED INSTRUCTION SET The PIC18F47J53 family implements the optional extension to the PIC18 instruction set, adding eight new instructions and an Indexed Addressing mode. Enabled as a device configuration option, the extension has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C. 1.1.
PIC18F47J53 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F2XJ53 (28-PIN DEVICES) Features Operating Frequency Program Memory (Kbytes) Program Memory (Instructions) Data Memory (Kbytes) PIC18F26J53 PIC18F27J53 DC – 48 MHz DC – 48 MHz 64 128 32,768 65,536 3.8 3.
PIC18F47J53 FAMILY FIGURE 1-1: PIC18F2XJ53 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 20 Address Latch PCU PCH PCL Program Counter 12 Data Address<12> 31-Level Stack 4 BSR Address Latch STKPTR Program Memory (16 Kbytes-64 Kbytes) 12 PORTC RC0:RC7(1) inc/dec logic Table Latch Instruction Bus <16> PORTB RB0:RB7(1) 4 Access Bank 12 FSR0 FSR1 FSR2 Data Latch 8 RA0:RA7(1) Data Memory (3.
PIC18F47J53 FAMILY FIGURE 1-2: PIC18F4XJ53 (44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> inc/dec logic 21 Address Latch PCU PCH PCL Program Counter 31-Level Stack System Bus Interface PORTB RB0:RB7(1) 12 Data Address<12> 4 Address Latch 4 12 BSR STKPTR Program Memory (16 Kbytes-64 Kbytes) RA0:RA7(1) Data Memory (3.
PIC18F47J53 FAMILY TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS Pin Number Pin Name MCLR OSC1/CLKI/RA7 OSC1 Pin Buffer 28-SPDIP/ SSOP/ 28-QFN Type Type SOIC 1(2) 26(2) 9 6 I I CLKI RA7(1) OSC2/CLKO/RA6 OSC2 I I/O 10 7 O CLKO O RA6(1) I/O ST Description Master Clear (Reset) input. This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise.
PIC18F47J53 FAMILY TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 28-SPDIP/ SSOP/ 28-QFN Type Type SOIC Description PORTA is a bidirectional I/O port.
PIC18F47J53 FAMILY TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 28-SPDIP/ SSOP/ 28-QFN Type Type SOIC Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F47J53 FAMILY TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 28-SPDIP/ SSOP/ 28-QFN Type Type SOIC Description PORTB (continued) (2) RB4/CCP4/KBI0/SCK1/SCL1/ RP7 RB4 CCP4 KBI0 SCK1 SCL1 RP7 25 RB5/CCP5/KBI1/SDI1/SDA1/ RP8 RB5 CCP5 KBI1 SDI1 SDA1 RP8 26(2) RB6/CCP6/KBI2/PGC/RP9 RB6 CCP6 KBI2 PGC RP9 27(2) RB7/CCP7/KBI3/PGD/RP10 RB7 CCP7 KBI3 PGD 28(2) RP10 (2) 22 I/O I/O I I/O I/O I/O TTL/DIG ST/DIG TTL ST/DIG I2C ST/DIG Digital I/O.
PIC18F47J53 FAMILY TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 28-SPDIP/ SSOP/ 28-QFN Type Type SOIC Description PORTC is a bidirectional I/O port.
PIC18F47J53 FAMILY TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 28-SPDIP/ SSOP/ 28-QFN Type Type SOIC VSS1 8 5 P VSS2 19 16 — — VDD 20 17 P — Positive supply for peripheral digital logic and I/O pins. VDDCORE/VCAP 6 3 — — VDDCORE P — VCAP P — Core logic power or external filter capacitor connection. Positive supply for microcontroller core logic (regulator disabled). External filter capacitor connection (regulator enabled).
PIC18F47J53 FAMILY TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS Pin Number Pin Name MCLR OSC1/CLKI/RA7 OSC1 Pin Buffer 44- 44- Type Type QFN TQFP 18(3) 18 32 30 I I CLKI RA7(1) OSC2/CLKO/RA6 OSC2 I I/O 33 31 O CLKO O RA6(1) I/O ST Description Master Clear (Reset) input; this is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS.
PIC18F47J53 FAMILY TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 44- 44- Type Type QFN TQFP Description PORTA is a bidirectional I/O port. RA0/AN0/C1INA/ULPWU/PMA6/ RP0 RA0 AN0 C1INA ULPWU PMA6 19 19 I/O I I I I/O 20 Digital I/O. Analog Input 1. Comparator 2 Input A. Band Gap Reference Voltage (VBG) output. Parallel Master Port digital I/O.
PIC18F47J53 FAMILY TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 44- 44- Type Type QFN TQFP Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F47J53 FAMILY TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 44- 44- Type Type QFN TQFP Description PORTB (continued) RB4/CCP4/PMA1/KBI0/SCK1/ SCL1/RP7 RB4 CCP4(2) PMA1(2) 14 (3) 14 (3) I/O I/O I/O KBI0 SCK1 SCL1 RP7 RB5/CCP5/PMA0/KBI1/SDI1/ SDA1/RP8 RB5 CCP5 PMA0(2) Digital I/O. Capture/Compare/PWM input/output. Parallel Master Port address. Digital I/O. Capture/Compare/PWM input/output. Parallel Master Port address.
PIC18F47J53 FAMILY TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 44- 44- Type Type QFN TQFP Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI/RP11 RC0 T1OSO T1CKI RP11 34 RC1/CCP8/T1OSI/UOE/RP12 RC1 CCP8 T1OSI UOE RP12 35 RC2/AN11/C2IND/CTPLS/RP13 RC2 AN11 C2IND CTPLS RP13 36 RC4/D-/VM RC4 DVM 42 RC5/D+/VP RC5 D+ VP 43 32 I/O O I I/O STDIG Analog ST ST/DIG Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.
PIC18F47J53 FAMILY TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name RC6/CCP9/PMA5/TX1/CK1/RP17 RC6 CCP9 PMA5 TX1 Pin Buffer 44- 44- Type Type QFN TQFP 44(3) 44(3) I/O I/O I/O O CK1 RP17 RC7/CCP10/PMA4/RX1/DT1/ SDO1/RP18 RC7 CCP10 PMA4 RX1 DT1 SDO1 RP18 Description (3) 1 1 I/O ST/DIG ST/DIG DIG ST/TTL/ DIG ST/DIG I/O ST/DIG I/O I/O I/O ST/DIG ST/DIG ST/TTL/ DIG I ST I/O O I/O ST/DIG DIG ST/DIG Digital I/O. Capture/Compare/PWM input/output.
PIC18F47J53 FAMILY TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 44- 44- Type Type QFN TQFP Description PORTD is a bidirectional I/O port. RD0/PMD0/SCL2 RD0 PMD0 38(3) 38 (3) I/O I/O SCL2 RD1/PMD1/SDA2 RD1 PMD1 I/O I/O I/O I/O I/O I/O I/O 41(3) I/O I/O I/O 2(3) I/O I/O I/O 3(3) I/O I/O I/O 4(3) RP24 ST/DIG ST/TTL/ DIG ST/DIG Digital I/O. Parallel Master Port data. ST/DIG ST/TTL/ DIG ST/DIG Digital I/O. Parallel Master Port data.
PIC18F47J53 FAMILY TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 44- 44- Type Type QFN TQFP Description PORTE is a bidirectional I/O port. RE0/AN5/PMRD RE0 AN5 PMRD 25 RE1/AN6/PMWR RE1 AN6 PMWR 26 RE2/AN7/PMCS RE2 AN7 PMCS 27 VSS1 6 VSS2 AVSS1 25 I/O I I/O ST/DIG Analog ST/TTL/ DIG Digital I/O. Analog Input 5. Parallel Master Port input/output. I/O I I/O ST/DIG Analog ST/TTL/ DIG Digital I/O. Analog Input 6. Parallel Master Port write strobe.
PIC18F47J53 FAMILY NOTES: DS39964B-page 30 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) Getting started with the PIC18F47J53 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. R1 R2 VSS VDD VDD Basic Connection Requirements VCAP/VDDCORE C1 The following pins must always be connected: C7 PIC18FXXJXX VSS VDD VDD VSS C3(2) C5(2) VSS C6(2) VDD • All VDD and VSS pins (see Section 2.
PIC18F47J53 FAMILY 2.2 2.2.1 Power Supply Pins 2.3 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC18F47J53 FAMILY 2.4 Voltage Regulator Pins (VCAP/VDDCORE) 2.5 On “F” devices, a low-ESR (< 5Ω) capacitor is required on the VCAP/VDDCORE pin to stabilize the voltage regulator output voltage. The VCAP/VDDCORE pin must not be connected to VDD and must use a capacitor of 10 F connected to ground. The type can be ceramic or tantalum. A suitable example is the Murata GRM21BF50J106ZE01 (10 F, 6.3V) or equivalent. Designers may use Figure 2-3 to evaluate ESR equivalence of candidate devices.
PIC18F47J53 FAMILY 2.6 External Oscillator Pins FIGURE 2-4: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 “Oscillator Configurations” for details). Single-Sided and In-Line Layouts: Copper Pour (tied to ground) The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.
PIC18F47J53 FAMILY 3.0 3.1 OSCILLATOR CONFIGURATIONS TABLE 3-1: Overview Devices in the PIC18F47J53 family incorporate a different oscillator and microcontroller clock system than general purpose PIC18F devices. Besides the USB module, with its unique requirements for a stable clock source, make it is necessary to provide a separate clock source that is compliant with both USB low-speed and full-speed specifications.
PIC18F47J53 FAMILY FIGURE 3-1: PIC18F47J53 FAMILY CLOCK DIAGRAM PLL Prescaler PLLDIV<2:0> Primary Oscillator OSC2 12 10 6 5 4 3 2 1 000 001 010 011 100 101 110 111 4 MHz 96 MHz PLL(1) 2 48 MHz FSEN FOSC2 1 1 0 0 PLLEN 8 CPDIV<1:0> 6 3 2 1 00 LS48MHZ 10 11 FOSC<2:1> Primary Clock Source(4) OSCCON<6:4> INTRC 31 kHz 8 MHz INTOSC Postscaler 8 MHz 111 4 MHz 110 2 MHz 101 1 MHz 100 500 kHz 011 250 kHz 010 125 kHz 001 1 31 kHz 000 0 OSCTUNE<7> Note 1: 2: 3: 4: IDLE CPU
PIC18F47J53 FAMILY 3.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS In HS and HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 3-2 displays the pin connections. TABLE 3-3: Osc Type HS The oscillator design requires the use of a parallel resonant crystal. Note: Use of a series resonant crystal may give a frequency out of the crystal manufacturer’s specifications.
PIC18F47J53 FAMILY 3.2.3 EXTERNAL CLOCK INPUT The EC and ECPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset (POR) or after an exit from Sleep mode. There is also a CPU divider, which can be used to derive the microcontroller clock from the PLL. This allows the USB peripheral and microcontroller to use the same oscillator input and still operate at different clock speeds.
PIC18F47J53 FAMILY 3.2.5.1 OSCTUNE Register 3.2.5.3 The internal oscillator’s output has been calibrated at the factory but can be adjusted in the user’s application. This is done by writing to the OSCTUNE register (Register 3-1). The tuning sensitivity is constant throughout the tuning range. When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. The INTOSC clock will stabilize typically within 1 s. Code execution continues during this shift.
PIC18F47J53 FAMILY REGISTER 3-1: OSCTUNE: OSCILLATOR TUNING REGISTER (ACCESS F9Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.
PIC18F47J53 FAMILY TABLE 3-5: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION Input Oscillator Frequency PLL Division (PLLDIV<2:0>) 48 MHz 48 MHz 40 MHz 24 MHz 24 MHz 20 MHz 16 MHz 12 MHz 8 MHz 4 MHz Note 1: N/A 12 (000) 10 (001) 6 (010) N/A 5 (011) 4 (100) 3 (101) 2 (110) 1 (111) Clock Mode (FOSC<2:0>) EC ECPLL ECPLL ECPLL EC(1) ECPLL HSPLL, ECPLL HSPLL, ECPLL HSPLL, ECPLL, INTOSCPLL/ INTOSCPLLO HSPLL, ECPLL MCU Clock Division (CPDIV<1:0>) Microcontroller Cl
PIC18F47J53 FAMILY 3.4 USB From INTOSC 3.5.1 The 8 MHz INTOSC included in all PIC18F47J53 family devices is extremely accurate. When the 8 MHz INTOSC is used with the 96 MHz PLL, it may be used to derive the USB module clock. The high accuracy of the INTOSC will allow the application to meet low-speed USB signal rate specifications. 3.
PIC18F47J53 FAMILY The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 4.0 “Low-Power Modes”. Note 1: The Timer1 crystal driver is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select the Timer1 clock source will be ignored, unless the CONFIG2L register’s T1DIG bit is set. 3.5.
PIC18F47J53 FAMILY REGISTER 3-3: R-0(2) U-0 — OSCCON2: OSCILLATOR CONTROL REGISTER 2 (ACCESS F87h) SOSCRUN U-0 — R/W-1 R/W-0(2) (3) SOSCDRV SOSCGO R/W-1 U-0 U-0 PRISD — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 SOSCRUN: SOSC Run Status bit 1 = System clock comes from secondary SOSC 0 = System clock comes from an oscillat
PIC18F47J53 FAMILY 3.6 Reference Clock Output In addition to the peripheral clock/4 output in certain oscillator modes, the device clock in the PIC18F47J53 family can also be configured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. This reference clock output is controlled by the REFOCON register (Register 3-4).
PIC18F47J53 FAMILY 3.7 Effects of Power-Managed Modes on Various Clock Sources When the PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. Unless the USB module is enabled, the OSC1 pin (and OSC2 pin if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock.
PIC18F47J53 FAMILY 4.0 LOW-POWER MODES The IDLEN bit (OSCCON<7>) controls CPU clocking and the SCS<1:0> bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 4-1. The PIC18F47J53 family devices can manage power consumption through clocking to the CPU and the peripherals. In general, reducing the clock frequency and number of circuits being clocked reduces power consumption. 4.1.
PIC18F47J53 FAMILY TABLE 4-1: Mode LOW-POWER MODES DSCONH<7> OSCCON<7,1:0> DSEN(1) IDLEN(1) SCS<1:0> Module Clocking CPU Peripherals Off Sleep 0 0 N/A Off Deep Sleep(3) 1 0 N/A Powered off(2) PRI_RUN 0 N/A 00 Clocked Available Clock and Oscillator Source Timer1 oscillator and/or RTCC may optionally be enabled Powered off RTCC can run uninterrupted using the Timer1 or internal low-power RC oscillator Clocked The normal, full-power execution mode; primary clock source (defined by FOSC
PIC18F47J53 FAMILY 4.2 Run Modes Note: The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS<1:0> bits are set to ‘01’, entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result.
PIC18F47J53 FAMILY 4.2.3 RC_RUN MODE On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC block while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-4). When the clock switch is complete, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch.
PIC18F47J53 FAMILY 4.3 Sleep Mode When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS<1:0> bits becomes ready (see Figure 4-6), or it will be clocked from the internal oscillator if either the Two-Speed Start-up or the FSCM is enabled (see Section 28.0 “Special Features of the CPU”). In either case, the OSTS bit is set when the primary clock is providing the device clocks.
PIC18F47J53 FAMILY 4.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘1’ when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS<1:0> bits; however, the CPU will not be clocked. The clock source status bits are not affected.
PIC18F47J53 FAMILY FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q4 Q3 Q2 Q1 OSC1 CPU Clock Peripheral Clock Program Counter FIGURE 4-8: PC PC + 2 TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program Counter PC Wake Event 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then clear the SCS bits and execute SLEEP.
PIC18F47J53 FAMILY 4.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all.
PIC18F47J53 FAMILY 4.6.2 I/O PINS DURING DEEP SLEEP 4.6.3 During Deep Sleep, the general purpose I/O pins will retain their previous states. DEEP SLEEP WAKE-UP SOURCES Pins that are configured as inputs (TRIS bit set) prior to entry into Deep Sleep will remain high-impedance during Deep Sleep. The device can be awakened from Deep Sleep mode by a MCLR, POR, RTCC, INT0 I/O pin interrupt, DSWDT or ULPWU event. After waking, the device performs a POR.
PIC18F47J53 FAMILY 4.6.5 DEEP SLEEP BROWN-OUT RESET (DSBOR) The Deep Sleep module contains a dedicated Deep Sleep BOR (DSBOR) circuit. This circuit may be optionally enabled through the DSBOREN Configuration bit. The DSBOR circuit monitors the VDD supply rail voltage. The behavior of the DSBOR circuit is described in Section 5.4 “Brown-out Reset (BOR)”. 4.6.6 RTCC PERIPHERAL AND DEEP SLEEP The RTCC can operate uninterrupted during Deep Sleep mode.
PIC18F47J53 FAMILY 4.6.9 DEEP SLEEP MODE REGISTERS Deep Sleep mode registers are Register 4-1 through Register 4-6.
PIC18F47J53 FAMILY REGISTER 4-3: DSGPR0: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 0 (BANKED F4Eh) R/W-xxxx(1) Deep Sleep Persistent General Purpose bits bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown Deep Sleep Persistent General Purpose bits Contents are retained even in Deep Sleep mode.
PIC18F47J53 FAMILY REGISTER 4-6: DSWAKEL: DEEP SLEEP WAKE LOW BYTE REGISTER (BANKED F4Ah) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-1 DSFLT — DSULP DSWDT DSRTC DSMCLR — DSPOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DSFLT: Deep Sleep Fault Detected bit 1 = A Deep Sleep Fault was detected during Deep Sleep 0 = A Deep Sleep Fault was not detected during D
PIC18F47J53 FAMILY 4.7 Ultra Low-Power Wake-up The Ultra Low-Power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupt-on-change without excess current consumption. Follow these steps to use this feature: 1. 2. 3. 4. 5. 6. 7. 8. Configure a remappable output pin to output the ULPOUT signal. Map an INTx interrupt-on-change input function to the same pin as used for the ULPOUT output function.
PIC18F47J53 FAMILY EXAMPLE 4-1: ULTRA LOW-POWER WAKE-UP INITIALIZATION //********************************************************************************* //Configure a remappable output pin with interrupt capability //for ULPWU function (RP21 => RD4/INT1 in this example) //********************************************************************************* RPOR21 = 13;// ULPWU function mapped to RP21/RD4 RPINR1 = 21;// INT1 mapped to RP21 (RD4) //*************************** //Charge the capacitor on RA0 //*
PIC18F47J53 FAMILY A series resistor between RA0 and the external capacitor provides overcurrent protection for the RA0/AN0/C1INA/ULPWU/RP0 pin and can allow for software calibration of the time-out (see Figure 4-9). FIGURE 4-9: SERIAL RESISTOR R1 RA0 A timer can be used to measure the charge time and discharge time of the capacitor. The charge time can then be adjusted to provide the desired interrupt delay. This technique will compensate for the affects of temperature, voltage and component accuracy.
PIC18F47J53 FAMILY NOTES: DS39964B-page 64 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 5.
PIC18F47J53 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER (ACCESS FD0h) R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplement
PIC18F47J53 FAMILY 5.2 Master Clear (MCLR) The Master Clear Reset (MCLR) pin provides a method for triggering a hard external Reset of the device. A Reset is generated by holding the pin low. PIC18 extended microcontroller devices have a noise filter in the MCLR Reset path, which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. 5.3 Power-on Reset (POR) A POR condition is generated on-chip whenever VDD rises above a certain threshold.
PIC18F47J53 FAMILY 5.5 Configuration Mismatch (CM) 5.6 The Configuration Mismatch (CM) Reset is designed to detect, and attempt to recover from, random memory corrupting events. These include Electrostatic Discharge (ESD) events, which can cause widespread single bit changes throughout the device and result in catastrophic failure.
PIC18F47J53 FAMILY FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 5-4: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-5: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 3.3V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 5.7 Reset State of Registers TO, PD, POR and BOR) are set or cleared differently in different Reset situations, as indicated in Table 5-1. These bits are used in software to determine the nature of the Reset. Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred.
PIC18F47J53 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset, Wake From Deep Sleep MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt TOSU PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu(1) TOSH PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu(1) TOSL PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu(1) STKPTR PIC18F2XJ53 PIC18F4XJ53 00-0 0000 uu-0 000
PIC18F47J53 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset, Wake From Deep Sleep MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt INDF2 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A POSTINC2 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A POSTDEC2 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A PREINC2 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N/A PLUSW2 PIC18F2XJ53 PIC18F4XJ53 N/A N/A N
PIC18F47J53 FAMILY TABLE 5-2: Register PSTR1CON INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset, Wake From Deep Sleep MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt uu-u uuuu PIC18F2XJ53 PIC18F4XJ53 00-0 0001 00-0 0001 ECCP1AS PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu ECCP1DEL PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu CCPR1H PIC18F2XJ53 PIC18F4XJ53 xxxx
PIC18F47J53 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset, Wake From Deep Sleep MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt IPR1 PIC18F2XJ53 PIC18F4XJ53 1111 1111 1111 1111 uuuu uuuu PIR1 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu(3) PIE1 PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu RCSTA2 PIC18F2XJ53 PIC18F4XJ53 0000 000x 00
PIC18F47J53 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset, Wake From Deep Sleep MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt TMR3H PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L PIC18F2XJ53 PIC18F4XJ53 xxxx xxxx uuuu uuuu uuuu uuuu T3CON PIC18F2XJ53 PIC18F4XJ53 0000 0000 uuuu uuuu uuuu uuuu TMR4 PIC18F2XJ53 PIC18F4XJ53 0000 0000 uuuu
PIC18F47J53 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset, Wake From Deep Sleep MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt PMCONL PIC18F2XJ53 PIC18F4XJ53 000- 0000 000- 0000 uuu- uuuu PMMODEH PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu PMMODEL PIC18F2XJ53 PIC18F4XJ53 0000 0000 0000 0000 uuuu uuuu PMDOUT2H PIC18F2XJ53 PIC18F4XJ53 0000 0
PIC18F47J53 FAMILY TABLE 5-2: Register REFOCON INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset, Wake From Deep Sleep MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt PIC18F4XJ53 0-00 0000 u-uu uuuu u-uu uuuu Applicable Devices PIC18F2XJ53 PADCFG1 PIC18F2XJ53 PIC18F4XJ53 ---- -000 ---- -uuu ---- -uuu RTCVALH PIC18F2XJ53 PIC18F4XJ53 0xxx xxxx 0uuu uuuu 0uuu uuuu RTCVALL PIC18F2XJ53 PIC18F4XJ53 0xxx xx
PIC18F47J53 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset, Wake From Deep Sleep MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt TMR8 PIC18F2XJ53 PIC18F4XJ53 0000 0000 — — PR8 PIC18F2XJ53 PIC18F4XJ53 1111 1111 — — T8CON PIC18F2XJ53 PIC18F4XJ53 -000 0000 — — PSTR3CON PIC18F2XJ53 PIC18F4XJ53 00-0 0001 — — ECCP3AS PIC18F2XJ53 PIC18F4XJ53 0000 0000
PIC18F47J53 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset, Wake From Deep Sleep MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt RPINR22 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu RPINR21 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu RPINR17 PIC18F2XJ53 PIC18F4XJ53 ---1 1111 ---1 1111 ---u uuuu RPINR16 PIC18F2XJ53 PIC18F4XJ53 ---1 1
PIC18F47J53 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset, Wake From Deep Sleep MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt RPOR5 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu RPOR4 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu RPOR3 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---0 0000 ---u uuuu RPOR2 PIC18F2XJ53 PIC18F4XJ53 ---0 0000 ---
PIC18F47J53 FAMILY 6.0 MEMORY ORGANIZATION 6.1 There are two types of memory in PIC18 Flash microcontrollers: • Program Memory • Data RAM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. Section 7.0 “Flash Program Memory” provides additional information on the operation of the Flash program memory.
PIC18F47J53 FAMILY 6.1.1 6.1.2 HARD MEMORY VECTORS FLASH CONFIGURATION WORDS All PIC18 devices have a total of three hard-coded return vectors in their program memory space. The Reset vector address is the default value to which the program counter returns on all device Resets; it is located at 0000h. Because PIC18F47J53 family devices do not have persistent configuration memory, the top four words of on-chip program memory are reserved for configuration information.
PIC18F47J53 FAMILY 6.1.3 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
PIC18F47J53 FAMILY 6.1.4.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off of the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value.
PIC18F47J53 FAMILY 6.1.4.4 Stack Full and Underflow Resets 6.1.6 Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration register 1L. When STVREN is set, a full or underflow condition sets the appropriate STKFUL or STKUNF bit and then causes a device Reset. When STVREN is cleared, a full or underflow condition sets the appropriate STKFUL or STKUNF bit, but does not cause a device Reset.
PIC18F47J53 FAMILY 6.2 PIC18 Instruction Cycle 6.2.1 6.2.2 An “Instruction Cycle” consists of four Q cycles, Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 6-3).
PIC18F47J53 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as 2 bytes or 4 bytes in program memory. The Least Significant Byte (LSB) of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘0’ (see Section 6.1.3 “Program Counter”).
PIC18F47J53 FAMILY 6.3 Note: Data Memory Organization 6.3.1 The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each.
PIC18F47J53 FAMILY 6.3.2 BANK SELECT REGISTER Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes.
PIC18F47J53 FAMILY FIGURE 6-6: DATA MEMORY MAP FOR PIC18F47J53 FAMILY DEVICES BSR3:BSR0 00h = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 When a = 0: Data Memory Map Access RAM Bank 0 Bank 1 FFh 00h GPR GPR (1) (1) (1) 1FFh 200h FFh 00h GPR(1) Bank 2 FFh 00h Bank 3 2FFh 300h When a = 1: The BSR specifies the bank used by the instruction.
PIC18F47J53 FAMILY FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 0 0 0 Bank Select(2) 1 0 000h Data Memory Bank 0 100h Bank 1 7 FFh 00h 11 From Opcode(2) 11 11 11 11 1 0 1 1 FFh 00h 200h 300h 00h Bank 2 FFh 00h Bank 3 through Bank 13 FFh 00h E00h Bank 14 FFh 00h F00h FFFh Note 1: 2: 6.3.
PIC18F47J53 FAMILY 6.3.5 SPECIAL FUNCTION REGISTERS The SFRs are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy more than the top half of Bank 15 (F40h to FFFh). Table 6-2, Table 6-3 and Table 6-4 provide a list of these registers. ALU’s STATUS register is described later in this section.
PIC18F47J53 FAMILY TABLE 6-3: Address F5Fh NON-ACCESS BANK SPECIAL FUNCTION REGISTER MAP Name PMCONH Address F3Fh Name RTCCFG Address Name F1Fh PR6 Address Name EFFh RPINR24 Address Name EDFh — Address Name EBFh PPSCON — F5Eh PMCONL F3Eh RTCCAL F1Eh T6CON EFEh RPINR23 EDEh — EBEh F5Dh PMMODEH F3Dh REFOCON F1Dh TMR8 EFDh RPINR22 EDDh — EBDh — F5Ch PMMODEL F3Ch PADCFG1 F1Ch PR8 EFCh RPINR21 EDCh — EBCh PMDIS3 F5Bh PMDOUT2H F3Bh RTCVALH F1Bh T8CON EF
PIC18F47J53 FAMILY 6.3.5.1 Context Defined SFRs • PMADDRH/L and PMDOUT2H/L: In this case, these named buffer pairs are actually the same physical registers. The Parallel Master Port (PMP) module’s operating mode determines what function the registers take on. See Section 11.1.2 “Data Registers” for additional details. There are several registers that share the same address in the SFR space. The register's definition and usage depends on the operating mode of its associated peripheral.
PIC18F47J53 FAMILY TABLE 6-4: Addr.
PIC18F47J53 FAMILY TABLE 6-4: Addr.
PIC18F47J53 FAMILY TABLE 6-4: Addr.
PIC18F47J53 FAMILY TABLE 6-4: Addr.
PIC18F47J53 FAMILY TABLE 6-4: Addr.
PIC18F47J53 FAMILY TABLE 6-4: Addr.
PIC18F47J53 FAMILY TABLE 6-4: Addr.
PIC18F47J53 FAMILY 6.3.6 STATUS REGISTER The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic.
PIC18F47J53 FAMILY 6.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way through the PC, information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
PIC18F47J53 FAMILY 6.4.3.1 FSR Registers and the INDF Operand (INDF) SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target.
PIC18F47J53 FAMILY 6.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value.
PIC18F47J53 FAMILY 6.6 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different. This is due to the introduction of a new addressing mode for the data memory space. This mode also alters the behavior of Indirect Addressing using FSR2 and its associated operands.
PIC18F47J53 FAMILY FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When a = 0 and f 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh. This is the same as locations, F60h to FFFh (Bank 15), of data memory. Locations below 060h are not available in this addressing mode.
PIC18F47J53 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data memory space.
PIC18F47J53 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on 1 byte at a time. A write to program memory is executed on blocks of 64 bytes at a time or 2 bytes at a time.
PIC18F47J53 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: 7.2 The Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “Writing to Flash Program Memory”.
PIC18F47J53 FAMILY REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 (ACCESS FA6h) U-0 U-0 R/W-0 R/W-0 R/W-x R/W-0 R/S-0 U-0 — — WPROG FREE WRERR WREN WR — bit 7 bit 0 Legend: S = Settable bit (cannot be cleared in software) R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 WPROG: One Word-Wide Program bit 1 = Program 2 bytes on the next WR comm
PIC18F47J53 FAMILY 7.2.2 TABLE LATCH REGISTER (TABLAT) 7.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped into the Special Function Register (SFR) space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. TBLPTR is used in reads, writes and erases of the Flash program memory. 7.2.
PIC18F47J53 FAMILY 7.3 Reading the Flash Program Memory The TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, the TBLPTR can be modified automatically for the next table read operation. The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. The internal program memory is typically organized by words.
PIC18F47J53 FAMILY 7.4 Erasing Flash Program Memory The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 1024 bytes of program memory is erased. The Most Significant 12 bits of the TBLPTR<21:10> point to the block being erased; TBLPTR<9:0> are ignored.
PIC18F47J53 FAMILY 7.5 Writing to Flash Program Memory The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. The programming block is 32 words or 64 bytes. Programming one word or 2 bytes at a time is also supported. Note 1: Unlike previous PIC® devices, devices of the PIC18F47J53 family do not reset the holding registers after a write occurs.
PIC18F47J53 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base address ; of the memory block, minus 1 BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF MOVLW MOVWF EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE D'16' WRITE_COUNTER ; enable write to memory ; enable Erase operation ; disable interrupts MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D
PIC18F47J53 FAMILY 7.5.2 FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PRORAMMING). 3. The PIC18F47J53 family of devices has a feature that allows programming a single word (two bytes). This feature is enabled when the WPROG bit is set. If the memory location is already erased, the following sequence is required to enable this feature: 1. 2. 4. 5. 6. 7. 8. Load the Table Pointer register with the address of the data to be written. (It must be an even address.
PIC18F47J53 FAMILY 7.5.3 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.5.
PIC18F47J53 FAMILY 8.0 8 x 8 HARDWARE MULTIPLIER 8.1 Introduction EXAMPLE 8-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register. ARG1, W ARG2 EXAMPLE 8-2: Making multiplication a hardware operation allows it to be completed in a single instruction cycle.
PIC18F47J53 FAMILY Example 8-3 provides the instruction sequence for a 16 x 16 unsigned multiplication. Equation 8-1 provides the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
PIC18F47J53 FAMILY 9.0 INTERRUPTS Devices of the PIC18F47J53 family have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress. There are 19 registers, which are used to control interrupt operation.
PIC18F47J53 FAMILY FIGURE 9-1: PIC18F47J53 FAMILY INTERRUPT LOGIC Wake-up if in Idle or Sleep modes TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> Interrupt to CPU Vector to Location 0008h GIE/GIEH IPEN PIR3<7:0> PIE3<7:0> IPR3<7:0> IPEN PEIE/GIEL IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<
PIC18F47J53 FAMILY 9.1 INTCON Registers Note: The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 9-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18F47J53 FAMILY REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 (ACCESS FF1h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0
PIC18F47J53 FAMILY REGISTER 9-3: INTCON3: INTERRUPT CONTROL REGISTER 3 (ACCESS FF0h) R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High pri
PIC18F47J53 FAMILY 9.2 PIR Registers Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3).
PIC18F47J53 FAMILY REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ACCESS FA1h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF CM2IF CM1IF USBIF BCL1IF HLVDIF TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = The device oscillator failed, clock input has changed to INTOSC (m
PIC18F47J53 FAMILY REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 (ACCESS FA4h) R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be c
PIC18F47J53 FAMILY REGISTER 9-7: PIR4: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 4 (ACCESS F8Fh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP10IF CCP9IF CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 CCP10IF:CCP4IF: CCP<10:4> Interrupt Flag bits Capture Mode 1 = A TMR register capture occurred (must be cle
PIC18F47J53 FAMILY REGISTER 9-8: PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5 (ACCESS F98h) U-0 U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CM3IF TMR8IF TMR6IF TMR5IF TMR5GIF TMR1GIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 CM3IF: Comparator Interrupt Flag bit 1 = Comparator3 input has changed (must be cleared in software) 0 = Com
PIC18F47J53 FAMILY 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18F47J53 FAMILY REGISTER 9-10: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ACCESS FA0h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CM2IE CM1IE USBIE BCL1IE HLVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CM2IE: Comparator 2 Interrupt Enable bit 1 = Enabled 0 = Disab
PIC18F47J53 FAMILY REGISTER 9-11: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 (ACCESS FA3h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 BCL2IE: Bus Collision Interrupt Enable bit
PIC18F47J53 FAMILY REGISTER 9-12: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 (ACCESS F8Eh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP10IE CCP9IE CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 CCP10IE:CCP4IE: CCP<10:4> Interrupt Enable bits 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Di
PIC18F47J53 FAMILY 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18F47J53 FAMILY REGISTER 9-15: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (ACCESS FA2h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CM2IP CM1IP USBIP BCL1IP HLVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CM2IP: Comparator 2 Interrupt Priority bit 1 = H
PIC18F47J53 FAMILY REGISTER 9-16: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 (ACCESS FA5h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision Interru
PIC18F47J53 FAMILY REGISTER 9-17: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4 (ACCESS F90h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CCP10IP CCP9IP CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 CCP10IP:CCP4IP: CCP<10:4> Interrupt Priority bits 1 = High priority 0 = Low priority bit 0 CCP3IP: ECCP3 Interrupt Priority bit 1
PIC18F47J53 FAMILY 9.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep mode. RCON also contains the bit that enables interrupt priorities (IPEN).
PIC18F47J53 FAMILY 9.6 INTx Pin Interrupts External interrupts on the INT0, INT1, INT2 and INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the INTx pin, the corresponding flag bit and INTxIF are set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE.
PIC18F47J53 FAMILY 10.0 I/O PORTS 10.1 I/O Port Pin Capabilities Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. When developing an application, the capabilities of the port pins must be considered.
PIC18F47J53 FAMILY 10.1.3 INTERFACING TO A 5V SYSTEM Though the VDDMAX of the PIC18F47J53 family is 3.6V, these devices are still capable of interfacing with 5V systems, even if the VIH of the target system is above 3.6V. This is accomplished by adding a pull-up resistor to the port pin (Figure 10-2), clearing the LAT bit for that pin and manipulating the corresponding TRIS bit (Figure 10-1) to either allow the line to be pulled high or to drive the pin low.
PIC18F47J53 FAMILY REGISTER 10-1: ODCON1: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 1 (BANKED F42h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCP8OD: CCP8 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 6 CCP7O
PIC18F47J53 FAMILY REGISTER 10-2: ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2 (BANKED F41h) U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CCP10OD CCP9OD U2OD U1OD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 CCP10OD: CCP10 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 2
PIC18F47J53 FAMILY REGISTER 10-4: PADCFG1: PAD CONFIGURATION CONTROL REGISTER 1 (BANKED F3Ch) U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 RTSECSEL1(1) RTSECSEL0(1) PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-1 RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits(1) 11 = Reserved; do not use 10 = RTCC source cl
PIC18F47J53 FAMILY TABLE 10-3: PORTA I/O SUMMARY Pin Function TRIS Setting I/O I/O Type Description RA0/AN0/C1INA/ ULPWU/PMA6/ RP0 RA0 1 I TTL PORTA<0> data input; disabled when analog input is enabled. 0 O DIG LATA<0> data output; not affected by analog input. AN0 1 I ANA A/D Input Channel 0 and Comparator C1- input. Default input configuration on POR; does not affect digital output. C1INA 1 I ANA Comparator 1 Input A. ULPWU 1 I ANA Ultra low-power wake-up input.
PIC18F47J53 FAMILY TABLE 10-3: PORTA I/O SUMMARY (CONTINUED) Pin Function TRIS Setting I/O I/O Type RA5/AN4/C1INC/ SS1/HLVDIN/ RCV/RP2 RA5 0 O DIG LATA<5> data output; not affected by analog input. 1 I TTL PORTA<5> data input; disabled when analog input is enabled. OSC2/CLKO/ RA6 OSC1/CLKI/RA7 Description AN4 1 I ANA A/D Input Channel 4. Default configuration on POR. C1INC 0 O DIG Comparator 1 Input C. SS1 1 I TTL Slave select input for MSSP1.
PIC18F47J53 FAMILY 10.3 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped.
PIC18F47J53 FAMILY TABLE 10-5: Pin RB0/AN12/ C3IND/INT0/ RP3 RB1/AN10/ C3INC/PMBE/ RTCC/ RP4 RB2/AN8/ C2INC/CTED1/ PMA3/VMO/ REFO/RP5 RB3/AN9/ C3INA/CTED2/ PMA2/VPO/ RP6 PORTB I/O SUMMARY Function TRIS Setting I/O I/O Type RB0 1 I TTL PORTB<0> data input; weak pull-up when the RBPU bit is cleared. Disabled when analog input is enabled.(1) 0 O DIG LATB<0> data output; not affected by analog input. AN12 1 I ANA A/D Input Channel 12.(1) C3IND 1 I ANA Comparator 3 Input D.
PIC18F47J53 FAMILY TABLE 10-5: Pin PORTB I/O SUMMARY (CONTINUED) Function TRIS Setting I/O I/O Type RB4 0 O DIG LATB<4> data output; not affected by analog input. 1 I TTL PORTB<4> data input; weak pull-up when the RBPU bit is cleared. Disabled when analog input is enabled.(1) 1 I ST Capture input. 0 O DIG Compare/PWM output. PMA1 x I/O KBI0 1 I RB4/CCP4/ PMA1/KBI0/ SCK1/SCL1/ RP7 CCP4(3) SCK1 Description ST/TTL/ Parallel Master Port address. DIG TTL Interrupt-on-change pin.
PIC18F47J53 FAMILY TABLE 10-5: Pin RB7/CCP7/ KBI3/PGD/ RP10 PORTB I/O SUMMARY (CONTINUED) Function TRIS Setting I/O I/O Type RB7 0 O DIG LATB<7> data output. 1 I TTL PORTB<7> data input; weak pull-up when the RBPU bit is cleared. 1 I ST Capture input. 0 O DIG Compare/PWM output. KBI3 1 O TTL Interrupt-on-change pin. PGD x O DIG Serial execution data output for ICSP and ICD operation.(2) x I ST Serial execution data input for ICSP and ICD operation.
PIC18F47J53 FAMILY 10.4 PORTC, TRISC and LATC Registers Note: PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped.
PIC18F47J53 FAMILY TABLE 10-7: Pin RC0/T1OSO/ T1CKI/RP11 PORTC I/O SUMMARY(1) Function TRIS Setting I/O I/O Type RC0 1 I ST 0 O DIG LATC<0> data output. x O ANA Timer1 oscillator output; enabled when Timer1 oscillator is enabled. Disables digital I/O. T1OSO RC1/CCP8/ T1OSI/UOE/ RP12 RC2/AN11/ C2IND/CTPLS/ RP13 RC4/D-/VM PORTC<0> data input. T1CKI 1 I ST Timer1 digital clock input. RP11 1 I ST Remappable Peripheral Pin 11 input. 0 O DIG Remappable Peripheral Pin 11 output.
PIC18F47J53 FAMILY TABLE 10-7: Pin PORTC I/O SUMMARY(1) (CONTINUED) Function TRIS Setting I/O I/O Type RC6 1 I ST RC6/CCP9/ PMA5/TX1/ CK1/RP17 PORTC<6> data input. 0 O DIG LATC<6> data output. CCP9 1 I ST Capture input. 0 O DIG Compare/PWM output. PMA5(2) 1 I ST/TTL Parallel Master Port io_addr_in<5>. 0 O DIG Parallel Master Port address. TX1 0 O DIG Asynchronous serial transmit data output (EUSART module); takes priority over port data. User must configure as an output.
PIC18F47J53 FAMILY 10.5 Note: PORTD, TRISD and LATD Registers EXAMPLE 10-5: PORTD CLRF LATD PORTD is available only in 44-pin devices. PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e.
PIC18F47J53 FAMILY TABLE 10-9: Pin PORTD I/O SUMMARY Function TRIS Setting I/O I/O Type RD0 1 I ST PORTD<0> data input. 0 O DIG LATD<0> data output. 1 I 0 O DIG Parallel Master Port data out. 1 I I2C/ SMB I2C™ clock input (MSSP2 module); input type depends on module setting. 0 O DIG I2C clock output (MSSP2 module); takes priority over port data. RD1 1 I ST PORTD<1> data input. 0 O DIG LATD<1> data output. PMD1(1) 1 I 0 O DIG Parallel Master Port data out.
PIC18F47J53 FAMILY TABLE 10-9: Pin RD6/PMD6/ RP23 PORTD I/O SUMMARY (CONTINUED) Function TRIS Setting I/O I/O Type RD6 1 I ST PORTD<6> data input. 0 O DIG LATD<6> data output. PMD6(1) 1 I 0 O DIG Parallel Master Port data out. 1 I ST Remappable Peripheral Pin 23 input. RP23 RD7/PMD7/ RP24 Description ST/TTL Parallel Master Port data in. 0 O DIG Remappable Peripheral Pin 23 output. RD7 1 I ST PORTD<7> data input. 0 O DIG LATD<7> data output.
PIC18F47J53 FAMILY 10.6 Note: PORTE, TRISE and LATE Registers EXAMPLE 10-6: PORTE CLRF LATE MOVLW MOVWF MOVLW 0Ah ADCON1 03h MOVWF TRISE PORTE is available only in 44-pin devices. Depending on the particular PIC18F47J53 family device selected, PORTE is implemented in two different ways. For 44-pin devices, PORTE is a 3-bit wide port. Three pins (RE0/AN5/PMRD, RE1/AN6/PMWR and RE2/ AN7/PMCS) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers.
PIC18F47J53 FAMILY TABLE 10-11: PORTE I/O SUMMARY Pin RE0/AN5/ PMRD RE1/AN6/ PMWR Function TRIS Setting I/O I/O Type Description RE0 1 I ST PORTE<0> data input; disabled when analog input is enabled. 0 O DIG LATE<0> data output; not affected by analog input. AN5 1 I ANA A/D Input Channel 5; default input configuration on POR. PMRD 1 I 0 O RE1 RE2/AN7/ PMCS DIG Parallel Master Port read strobe. 1 I ST PORTE<1> data input; disabled when analog input is enabled.
PIC18F47J53 FAMILY 10.7 Peripheral Pin Select (PPS) 10.7.2 A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low pin count devices similar to the PIC18F47J53 family. In an application that needs to use more than one peripheral, multiplexed on a single pin, inconvenient workarounds in application code or a complete redesign may be the only option.
PIC18F47J53 FAMILY 10.7.3.1 Input Mapping The inputs of the PPS options are mapped on the basis of the peripheral; that is, a control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 10-6 through Register 10-23). Each register contains a 5-bit field which is associated TABLE 10-13: with one of the pin selectable peripherals.
PIC18F47J53 FAMILY 10.7.3.2 Output Mapping In contrast to inputs, the outputs of the PPS options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. The value of the bit field corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see Table 10-14).
PIC18F47J53 FAMILY 10.7.3.3 Mapping Limitations 10.7.4.3 The control schema of the PPS is extremely flexible. Other than systematic blocks that prevent signal contention caused by two physical pins being configured as the same functional input or two functional outputs configured as the same pin, there are no hardware enforced lockouts. The flexibility extends to the point of allowing a single input to drive multiple peripherals or a single functional output to drive multiple output pins. 10.7.
PIC18F47J53 FAMILY Choosing the configuration requires the review of all PPSs and their pin assignments, especially those that will not be used in the application. In all cases, unused pin selectable peripherals should be disabled completely. Unused peripherals should have their inputs assigned to an unused RPn pin function. I/O pins with unused RPn functions should be configured with the null peripheral output.
PIC18F47J53 FAMILY 10.7.6 PERIPHERAL PIN SELECT REGISTERS Note: The PIC18F47J53 family of devices implements a total of 37 registers for remappable peripheral configuration of 44-pin devices. The 28-pin devices have 31 registers for remappable peripheral configuration. REGISTER 10-5: Input and output register values can only be changed if IOLOCK (PPSCON<0>) = 0. See Example 10-7 for a specific command sequence.
PIC18F47J53 FAMILY REGISTER 10-8: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 (BANKED EE3h) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — INTR3R4 INTR3R3 INTR3R2 INTR3R1 INTR3R0 bit 7 bit 0 Legend: R/W = Readable bit, Writable bit if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 INTR3R<4:0>: Assign External Interrupt 3 (I
PIC18F47J53 FAMILY REGISTER 10-11: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 (BANKED EE8h) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 bit 7 bit 0 Legend: R/W = Readable bit, Writable bit if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC1R<4:0>: Assign Input Capture 1 (ECCP1) to the Corre
PIC18F47J53 FAMILY REGISTER 10-14: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12 (BANKED EF2h) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T1GR4 T1GR3 T1GR2 T1GR1 T1GR0 bit 7 bit 0 Legend: R/W = Readable bit, Writable bit if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T1GR<4:0>: Timer1 Gate Input (T1G) to the Correspond
PIC18F47J53 FAMILY REGISTER 10-17: RPINR16: PERIPHERAL PIN SELECT INPUT REGISTER 16 (BANKED EF7h) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — RX2DT2R4 RX2DT2R3 RX2DT2R2 RX2DT2R1 RX2DT2R0 bit 7 bit 0 Legend: R/W = Readable bit, Writable bit if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RX2DT2R<4:0>: EUSART2 Synchronous/Asy
PIC18F47J53 FAMILY REGISTER 10-21: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 (BANKED EFDh) U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 bit 7 bit 0 Legend: R/W = Readable bit, Writable bit if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 SCK2R<4:0>: Assign SPI2 Clock Input (SCK2) to t
PIC18F47J53 FAMILY REGISTER 10-24: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 (BANKED EC1h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 bit 7 bit 0 Legend: R/W = Readable bit, Writable bit if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP0R<4:0>: Peripheral Output Function is Assigned to R
PIC18F47J53 FAMILY REGISTER 10-27: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 (BANKED EC3h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 bit 7 bit 0 Legend: R/W = Readable bit, Writable bit if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP3R<4:0>: Peripheral Output Function is Assigned to R
PIC18F47J53 FAMILY REGISTER 10-30: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 (BANKED EC6h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 bit 7 bit 0 Legend: R/W = Readable bit, Writable bit if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to R
PIC18F47J53 FAMILY REGISTER 10-33: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 (BANKED EC9h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 bit 7 bit 0 Legend: R/W = Readable bit, Writable bit if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP9R<4:0>: Peripheral Output Function is Assigned to R
PIC18F47J53 FAMILY REGISTER 10-36: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 (BANKED ECCh) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 bit 7 bit 0 Legend: R/W = Readable bit, Writable bit if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP12R<4:0>: Peripheral Output Function is Assig
PIC18F47J53 FAMILY REGISTER 10-39: RPOR18: PERIPHERAL PIN SELECT OUTPUT REGISTER 18 (BANKED ED2h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP18R4 RP18R3 RP18R2 RP18R1 RP18R0 bit 7 bit 0 Legend: R/W = Readable bit, Writable bit if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP18R<4:0>: Peripheral Output Function is Assig
PIC18F47J53 FAMILY REGISTER 10-42: RPOR21: PERIPHERAL PIN SELECT OUTPUT REGISTER 21 (BANKED ED5h)(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 bit 7 bit 0 Legend: R/W = Readable bit, Writable bit if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP21R<4:0>: Peripheral Output Function is As
PIC18F47J53 FAMILY REGISTER 10-45: RPOR24: PERIPHERAL PIN SELECT OUTPUT REGISTER 24 (BANKED ED8h)(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 bit 7 bit 0 Legend: R/W = Readable bit, Writable bit if IOLOCK = 0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is As
PIC18F47J53 FAMILY 11.0 PARALLEL MASTER PORT (PMP) Key features of the PMP module are: The Parallel Master Port module (PMP) is an 8-bit parallel I/O module, specifically designed to communicate with a wide variety of parallel devices, such as communication peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP is highly configurable.
PIC18F47J53 FAMILY 11.1 Module Registers The PMCON registers (Register 11-1 and Register 11-2) control basic module operations, including turning the module on or off. They also configure address multiplexing and control strobe configuration. The PMP module has a total of 14 Special Function Registers (SFRs) for its operation, plus one additional register to set configuration options. Of these, eight registers are used for control and six are used for PMP data transfer. 11.1.
PIC18F47J53 FAMILY REGISTER 11-2: PMCONL: PARALLEL PORT CONTROL REGISTER LOW BYTE (BANKED F5Eh)(1) R/W-0 R/W-0 R/W-0(2) U-0 R/W-0(2) R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP — CS1P BEP WRSP RDSP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CSF<1:0>: Chip Select Function bits 11 = Reserved 10 = Chip select function is enabled and PMCSx acts as chip select (in Maste
PIC18F47J53 FAMILY REGISTER 11-3: PMMODEH: PARALLEL PORT MODE REGISTER HIGH BYTE (BANKED F5Dh)(1) R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy bit 6-5 IRQM<1:0>: Interrupt Request Mode bits 1
PIC18F47J53 FAMILY REGISTER 11-4: PMMODEL: PARALLEL PORT MODE REGISTER LOW BYTE (BANKED F5Ch)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAITB1(2) WAITB0(2) WAITM3 WAITM2 WAITM1 WAITM0 WAITE1(2) WAITE0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits(2) 11 = Data Wait of 4 TCY; multiplexed address phas
PIC18F47J53 FAMILY REGISTER 11-5: PMEH: PARALLEL PORT ENABLE REGISTER HIGH BYTE (BANKED F57h)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 PTEN<15:14>: PMCS1 Port Enable bits 1 = PMA<15:14> function as either PMA<15:14> or PMCS2 and PMCS1 0 = PMA<15:14
PIC18F47J53 FAMILY REGISTER 11-7: PMSTATH: PARALLEL PORT STATUS REGISTER HIGH BYTE (BANKED F55h)(1) R-0 R/W-0 U-0 U-0 R-0 R-0 R-0 R-0 IBF IBOV — — IB3F IB2F IB1F IB0F bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty
PIC18F47J53 FAMILY 11.1.2 DATA REGISTERS The PMP module uses eight registers for transferring data into and out of the microcontroller. They are arranged as four pairs to allow the option of 16-bit data operations: • • • • PMDIN1H and PMDIN1L PMDIN2H and PMDIN2L PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L PMDOUT2H and PMDOUT2L The PMDIN1 registers are used for incoming data in Slave modes, and both input and output data in Master modes.
PIC18F47J53 FAMILY REGISTER 11-9: PMADDRH: PARALLEL PORT ADDRESS REGISTER HIGH BYTE (MASTER MODES ONLY) (ACCESS F6Fhh)(1) U0 R/W-0 — CS1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Parallel Master Port Address High Byte<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 CS1: Chip Select bit If PMCON<7:6> = 10: 1 = Chip select is active 0 = Chip select is
PIC18F47J53 FAMILY 11.2 Slave Port Modes The primary mode of operation for the module is configured using the MODE<1:0> bits in the PMMODEH register. The setting affects whether the module acts as a slave or a master, and it determines the usage of the control pins. 11.2.1 LEGACY MODE (PSP) In Legacy mode (PMMODEH<1:0> = 00 and PMPEN = 1), the module is configured as a Parallel Slave Port (PSP) with the associated enabled module FIGURE 11-2: pins dedicated to the module.
PIC18F47J53 FAMILY 11.2.2 WRITE TO SLAVE PORT 11.2.3 When chip select is active and a write strobe occurs (PMCSx = 1 and PMWR = 1), the data from PMD<7:0> is captured into the lower PMDIN1L register. The PMPIF and IBF flag bits are set when the write ends.The timing for the control signals in Write mode is displayed in Figure 11-3. The polarity of the control signals are configurable.
PIC18F47J53 FAMILY 11.2.4 BUFFERED PARALLEL SLAVE PORT MODE 11.2.4.2 Buffered Parallel Slave Port mode is functionally identical to the legacy PSP mode with one exception, the implementation of 4-level read and write buffers. Buffered PSP mode is enabled by setting the INCM bits in the PMMODEH register. If the INCM<1:0> bits are set to ‘11’, the PMP module will act as the buffered PSP.
PIC18F47J53 FAMILY 11.2.5 ADDRESSABLE PARALLEL SLAVE PORT MODE In the Addressable Parallel Slave Port mode (PMMODEH<1:0> = 01), the module is configured with two extra inputs, PMA<1:0>, which are the address lines 1 and 0. This makes the 4-byte buffer space directly addressable as fixed pairs of read and write buffers. As with Legacy Buffered mode, data is output from PMDOUT1L, PMDOUT1H, PMDOUT2L and PMDOUT2H, and is read in PMDIN1L, PMDIN1H, PMDIN2L and PMDIN2H.
PIC18F47J53 FAMILY 11.2.5.2 WRITE TO SLAVE PORT When chip select is active and a write strobe occurs (PMCSx = 1 and PMWR = 1), the data from PMD<7:0> is captured into one of the four input buffer bytes. Which byte is written depends on the 2-bit address placed on ADDRL<1:0>. When an input buffer is written, the corresponding IBxF bit is set. The IBF flag bit is set when all the buffers are written.
PIC18F47J53 FAMILY 11.3 MASTER PORT MODES In its Master modes, the PMP module provides an 8-bit data bus, up to 16 bits of address, and all the necessary control signals to operate a variety of external parallel devices, such as memory devices, peripherals and slave microcontrollers. To use the PMP as a master, the module must be enabled (PMPEN = 1) and the mode must be set to one of the two possible Master modes (PMMODEH<1:0> = 10 or 11).
PIC18F47J53 FAMILY FIGURE 11-9: DEMULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F PMA<7:0> PMD<7:0> PMCSx PMRD Address Bus Data Bus PMWR FIGURE 11-10: Control Lines PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F PMD<7:0> PMA<7:0> PMCSx PMALL PMRD PMWR FIGURE 11-11: Address Bus Multiplexed Data and Address Bus Control Lines FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC1
PIC18F47J53 FAMILY 11.3.5 CHIP SELECT FEATURES Up to two chip select lines, PMCS1 and PMCS2, are available for the Master modes of the PMP. The two chip select lines are multiplexed with the Most Significant bit (MSb) of the address bus (PMADDRH<6>). When a pin is configured as a chip select, it is not included in any address auto-increment/decrement. The function of the chip select signals is configured using the chip select function bits (PMCONL<7:6>). 11.3.
PIC18F47J53 FAMILY 11.3.11 MASTER MODE TIMING This section contains a number of timing examples that represent the common Master mode configuration options. These options vary from 8-bit to 16-bit data, fully demultiplexed to fully multiplexed address and Wait states.
PIC18F47J53 FAMILY FIGURE 11-15: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 Address<7:0> PMD<7:0> Data PMWR PMRD PMALL PMPIF BUSY FIGURE 11-16: WRITE TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - PMCS1 Address<7:0> PMD<7:0> Data PMWR PMRD PMALL PMPIF BUSY WAITB<1:0> = 01
PIC18F47J53 FAMILY FIGURE 11-18: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 PMD<7:0> Address<7:0> Data PMRD/PMWR PMENB PMALL PMPIF BUSY FIGURE 11-19: READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 Address<7:0> PMD<7:0> Data Address<13:8> PMWR PMRD PMALL PMALH PMPIF BUSY FIGURE 11-20: WRITE TIMING, 8-BI
PIC18F47J53 FAMILY FIGURE 11-21: READ TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 LSB PMD<7:0> MSB PMA<7:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 11-22: WRITE TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 LSB PMD<7:0> MSB PMA<7:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 11-23: READ TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q
PIC18F47J53 FAMILY FIGURE 11-24: WRITE TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 PMD<7:0> Address<7:0> LSB MSB PMWR PMRD PMBE PMALL PMPIF BUSY FIGURE 11-25: READ TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS1 Address<7:0> PMD<7:0> Address<13:8> LSB MSB PMWR PMRD PMBE PMALH PMALL PMPIF BUS
PIC18F47J53 FAMILY 11.4 Application Examples 11.4.1 This section introduces some potential applications for the PMP module. FIGURE 11-27: MULTIPLEXED MEMORY OR PERIPHERAL Figure 11-27 demonstrates the hookup of a memory or another addressable peripheral in Full Multiplex mode. Consequently, this mode achieves the best pin saving from the microcontroller perspective. However, for this configuration, there needs to be some external latches to maintain the address.
PIC18F47J53 FAMILY 11.4.3 PARALLEL EEPROM EXAMPLE Figure 11-30 provides an example connecting parallel EEPROM to the PMP. Figure 11-31 demonstrates a slight variation to this, configuring the connection for 16-bit data from a single EEPROM.
PIC18F47J53 FAMILY TABLE 11-2: Name INTCON REGISTERS ASSOCIATED WITH PMP MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PMPIF (2) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF PIE1 PMPIE(2) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE IPR1 PMPIP(2) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP PMCONH(2) PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN PMCONL(2) CSF1 CSF0 ALP — CS1
PIC18F47J53 FAMILY NOTES: DS39964B-page 204 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 12.0 TIMER0 MODULE The Timer0 module incorporates the following features: • Software selectable operation as a timer or counter in both 8-bit or 16-bit modes • Readable and writable registers • Dedicated 8-bit, software programmable prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 12-1: The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection.
PIC18F47J53 FAMILY 12.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
PIC18F47J53 FAMILY 12.3 Prescaler 12.3.1 An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. Its value is set by the PSA and T0PS<2:0> bits (T0CON<3:0>), which determine the prescaler assignment and prescale ratio. The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution. 12.4 Clearing the PSA bit assigns the prescaler to the Timer0 module.
PIC18F47J53 FAMILY NOTES: DS39964B-page 208 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 13.
PIC18F47J53 FAMILY 13.1 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), displayed in Register 13-2, is used to control the Timer1 gate.
PIC18F47J53 FAMILY 13.2 Timer1 Operation 13.3.2 The Timer1 module is an 8-bit or 16-bit incrementing counter, which is accessed through the TMR1H:TMR1L register pair. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source.
PIC18F47J53 FAMILY FIGURE 13-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1G 00 From Timer2 Match PR2 Comparator 1 Output Comparator 2 Output 01 T1GSPM 0 T1G_IN 10 Single Pulse 11 TMR1ON T1GPOL T1GVAL 0 D Q CK R Q 1 Acq.
PIC18F47J53 FAMILY 13.4 Timer1 16-Bit Read/Write Mode TABLE 13-2: Timer1 can be configured for 16-bit reads and writes. When the RD16 control bit (T1CON<1>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L loads the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register.
PIC18F47J53 FAMILY 13.5.1 USING TIMER1 AS A CLOCK SOURCE FIGURE 13-3: The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the clock select bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, the device switches to SEC_RUN mode; both the CPU and peripherals are clocked from the Timer1 oscillator. If the IDLEN bit (OSCCON<7>) is cleared and a SLEEP instruction is executed, the device enters SEC_IDLE mode. Additional details are available in Section 4.0 “Low-Power Modes”.
PIC18F47J53 FAMILY 13.7 Resetting Timer1 Using the ECCP Special Event Trigger 13.8 The Timer1 can be configured to count freely or the count can be enabled and disabled using the Timer1 gate circuitry. This is also referred to as Timer1 gate count enable. If ECCP1 or ECCP2 is configured to use Timer1 and to generate a Special Event Trigger in Compare mode (CCPxM<3:0> = 1011), this signal will reset Timer3.
PIC18F47J53 FAMILY 13.8.2 TIMER1 GATE SOURCE SELECTION 13.8.2.2 The Timer1 gate source can be selected from one of four different sources. Source selection is controlled by the T1GSSx bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register. TABLE 13-4: TIMER1 GATE SOURCES T1GSS<1:0> Timer1 Gate Pin 01 TMR2 matches PR2 10 Comparator 1 output 11 Comparator 2 output 13.8.2.1 13.8.
PIC18F47J53 FAMILY 13.8.4 TIMER1 GATE SINGLE PULSE MODE When Timer1 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/T1DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/T1DONE bit will automatically be cleared.
PIC18F47J53 FAMILY FIGURE 13-7: TIMER1 GATE SINGLE PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by Hardware on Falling Edge of T1GVAL Set by Software T1DONE Counting Enabled on Rising Edge of T1G T1G_IN T1CKI T1GVAL Timer1 TABLE 13-5: N+2 N+4 N+3 Set by Hardware on Falling Edge of T1GVAL Cleared by Software TMR1GIF Name N+1 N Cleared by Software REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON
PIC18F47J53 FAMILY 14.0 TIMER2 MODULE 14.1 Timer2 Operation • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4 and 1:16) • Software programmable postscaler (1:1 through 1:16) • Interrupt on TMR2 to PR2 match • Optional use as the shift clock for the MSSP modules In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4).
PIC18F47J53 FAMILY 14.2 Timer2 Interrupt 14.3 Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 Match Interrupt Flag, which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>).
PIC18F47J53 FAMILY 15.0 TIMER3/5 MODULE The Timer3/5 timer/counter modules incorporate these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMRxH and TMRxL) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on ECCP Special Event Trigger A simplified block diagram of the Timer3/5 module is shown in Figure 15-1.
PIC18F47J53 FAMILY REGISTER 15-1: TxCON: TIMER3/5 CONTROL REGISTER (ACCESS F79h, BANKED F22h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMRxCS1 TMRxCS0 TxCKPS1 TxCKPS0 TxOSCEN TxSYNC RD16 TMRxON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TMRxCS<1:0>: Clock Source Select bits 10 = Clock source is the pin or TxCKI input pin 01 = Clock source is the system clock (FOSC)(
PIC18F47J53 FAMILY 15.1 Timer3/5 Gate Control Register The Timer3/5 Gate Control register (TxGCON), provided in Register 14-2, is used to control the Timerx gate.
PIC18F47J53 FAMILY REGISTER 15-3: OSCCON2: OSCILLATOR CONTROL REGISTER 2 (ACCESS F87h) U-0 R-0(2) — SOSCRUN U-0 — R/W-1 R/W-0(2) SOSCDRV SOSCGO(3) R/W-1 U-0 U-0 PRISD — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 SOSCRUN: SOSC Run Status bit 1 = System clock comes from secondary SOSC 0 = System clock comes from an oscilla
PIC18F47J53 FAMILY 15.2 Timer3/5 Operation The operating mode is determined by the clock select bits, TMRxCSx (TxCON<7:6>). When the TMRxCSx bits are cleared (= 00), Timer3/5 increments on every internal instruction cycle (FOSC/4). When TMRxCSx = 01, the Timer3/5 clock source is the system clock (FOSC), and when it is ‘10’, Timer3/5 works as a counter from the external clock from the TxCKI pin (on the rising edge after the first falling edge) or the Timer1 oscillator.
PIC18F47J53 FAMILY 15.3 Timer3/5 16-Bit Read/Write Mode 15.5 Timer3/5 can be configured for 16-bit reads and writes (see Figure 15.3). When the RD16 control bit (TxCON<1>) is set, the address for TMRxH is mapped to a buffer register for the high byte of Timer3/5. A read from TMRxL will load the contents of the high byte of Timer3/5 into the Timerx High Byte Buffer register.
PIC18F47J53 FAMILY 15.5.2 TIMER3/5 GATE SOURCE SELECTION 15.5.2.2 Timer4/6 Match Gate Operation The Timer3/5 gate source can be selected from one of four different sources. Source selection is controlled by the TxGSS<1:0> bits (TxGCON<1:0>). The polarity for each available source is also selectable and is controlled by the TxGPOL bit (TxGCON<6>). The TMR4/6 register will increment until it matches the value in the PR4/6 register. On the very next increment cycle, TMR4/6 will be reset to 00h.
PIC18F47J53 FAMILY 15.5.4 TIMER3/5 GATE SINGLE PULSE MODE No other gate events will be allowed to increment Timer3/5 until the TxGGO/TxDONE bit is once again set in software. When Timer3/5 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer3/5 Gate Single Pulse mode is first enabled by setting the TxGSPM bit (TxGCON<4>). Next, the TxGGO/TxDONE bit (TxGCON<3>) must be set. Clearing the TxGSPM bit TxGGO/TxDONE bit. (For Figure 15-4.
PIC18F47J53 FAMILY FIGURE 15-5: TIMER3/5 GATE SINGLE PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ Cleared by Hardware on Falling Edge of TxGVAL Set by Software TxDONE Counting Enabled on Rising Edge of TxG TxG_IN TxCKI TxGVAL Timer3/5 TMRxGIF 15.5.5 N N+1 N+2 N+3 N+4 Set by Hardware on Falling Edge of TxGVAL Cleared by Software TIMER3/5 GATE VALUE STATUS 15.5.
PIC18F47J53 FAMILY 15.6 Timer3/5 Interrupt 15.7 The TMRx register pair (TMRxH:TMRxL) increments from 0000h to FFFFh and overflows to 0000h. The Timerx interrupt, if enabled, is generated on overflow and is latched in the interrupt flag bit, TMRxIF. Table 15-3 gives each module’s flag bit.
PIC18F47J53 FAMILY TABLE 15-5: Name INTCON PIR5 REGISTERS ASSOCIATED WITH TIMER3/5 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF — — CM3IF TMR8IF TMR6IF TMR5IF TMR5GIF TMR1GIF PIE5 — — CM3IE TMR8IE TMR6IE TMR5IE TMR5GIE TMR1GIE PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF HLVDIF TMR3IF CCP2IF OSCFIE CM2IE CM1IE USBIE BCL1IE HLVDIE TMR3IE CCP2IE PIE2 TMR3H Timer3 Register High Byte TMR3L
PIC18F47J53 FAMILY NOTES: DS39964B-page 232 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 16.
PIC18F47J53 FAMILY REGISTER 16-1: TxCON: TIMER4/6/8 CONTROL REGISTER (ACCESS F76h, BANKED F1Eh, BANKED F1Bh) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TxOUTPS3 TxOUTPS2 TxOUTPS1 TxOUTPS0 TMRxON TxCKPS1 TxCKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TxOUTPS<3:0>: Timerx Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2
PIC18F47J53 FAMILY TABLE 16-3: Name REGISTERS ASSOCIATED WITH TIMER4/6/8 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF IPR5 TMR7GIP TMR12IP TMR10IP TMR8IP TMR7IP TMR6IP TMR5IP TMR4IP PIR5 — — CM3IF TMR8IF TMR6IF TMR5IF TMR5GIF TMR1GIF PIE5 — — CM3IE TMR8IE TMR6IE TMR5IE TMR5GIE TMR1GIE TMR4ON T4CKPS1 T4CKPS0 TMR6ON T6CKPS1 T6CKPS0 TMR8ON T8CKPS1 T8CKPS0 TMR4 T4CON Timer4
PIC18F47J53 FAMILY NOTES: DS39964B-page 236 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 17.0 REAL-TIME CLOCK AND CALENDAR (RTCC) The key features of the Real-Time Clock and Calendar (RTCC) module are: • • • • • • • • • • • • Time: hours, minutes and seconds 24-hour format (military time) Calendar: weekday, date, month and year Alarm configurable Year range: 2000 to 2099 Leap year correction BCD format for compact firmware Optimized for low-power operation User calibration with auto-adjust Calibration range: 2.64 seconds error per month Requirements: external 32.
PIC18F47J53 FAMILY 17.1 RTCC MODULE REGISTERS Alarm Value Registers The RTCC module registers are divided into following categories: RTCC Control Registers • • • • • RTCCFG RTCCAL PADCFG1 ALRMCFG ALRMRPT • ALRMVALH and ALRMVALL – Can access the following registers: - ALRMMNTH - ALRMDAY - ALRMWD - ALRMHR - ALRMMIN - ALRMSEC Note: RTCC Value Registers The RTCVALH and RTCVALL registers can be accessed through RTCRPT<1:0>. ALRMVALH and ALRMVALL can be accessed through ALRMPTR<1:0>.
PIC18F47J53 FAMILY 17.1.
PIC18F47J53 FAMILY RTCCAL: RTCC CALIBRATION REGISTER (BANKED F3Eh) REGISTER 17-2: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown CAL<7:0>: RTCC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every minute . . .
PIC18F47J53 FAMILY REGISTER 17-4: ALRMCFG: ALARM CONFIGURATION REGISTER (ACCESS F47h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 0000 0000
PIC18F47J53 FAMILY REGISTER 17-5: ALRMRPT: ALARM REPEAT COUNTER (ACCESS F46h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times . . .
PIC18F47J53 FAMILY 17.1.
PIC18F47J53 FAMILY REGISTER 17-9: DAY: DAY VALUE REGISTER(1) U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal value of Day’s Tens Digit bits Contains a value from 0 to 3.
PIC18F47J53 FAMILY REGISTER 17-11: HOURS: HOURS VALUE REGISTER(1) U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2.
PIC18F47J53 FAMILY 17.1.
PIC18F47J53 FAMILY REGISTER 17-16: ALRMWD: ALARM WEEKDAY VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6.
PIC18F47J53 FAMILY REGISTER 17-18: ALRMMIN: ALARM MINUTES VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5.
PIC18F47J53 FAMILY 17.1.4 17.2 RTCEN BIT WRITE An attempt to write to the RTCEN bit while RTCWREN = 0 will be ignored. RTCWREN must be set before a write to RTCEN can take place. Like the RTCEN bit, the RTCVALH and RTCVALL registers can only be written to when RTCWREN = 1. A write to these registers, while RTCWREN = 0, will be ignored. FIGURE 17-2: FIGURE 17-3: The register interface for the RTCC and alarm values is implemented using the Binary Coded Decimal (BCD) format.
PIC18F47J53 FAMILY 17.2.2 CLOCK SOURCE As mentioned earlier, the RTCC module is intended to be clocked by an external Real-Time Clock (RTC) crystal oscillating at 32.768 kHz, but can also be clocked by the INTRC. The RTCC clock selection is decided by the RTCOSC bit (CONFIG3L<1>). FIGURE 17-4: Calibration of the crystal can be done through this module to yield an error of 3 seconds or less per month. (For further details, see Section 17.2.9 “Calibration”.) CLOCK SOURCE MULTIPLEXING 32.
PIC18F47J53 FAMILY TABLE 17-2: DAY TO MONTH ROLLOVER SCHEDULE Month Maximum Day Field 01 (January) 31 02 (February) 28 or 29(1) 03 (March) 31 04 (April) 30 05 (May) 31 06 (June) 30 07 (July) 31 08 (August) 31 17.2.6 SAFETY WINDOW FOR REGISTER READS AND WRITES The RTCSYNC bit indicates a time window during which the RTCC Clock Domain registers can be safely read and written without concern about a rollover. When RTCSYNC = 0, the registers can be safely accessed by the CPU.
PIC18F47J53 FAMILY TABLE 17-3: RTCVALH AND RTCVALL REGISTER MAPPING To calibrate the RTCC module: 1. RTCC Value Register Window RTCPTR<1:0> RTCVAL<15:8> RTCVAL<7:0> 00 MINUTES SECONDS 01 WEEKDAY HOURS 10 MONTH DAY 11 — YEAR Use another timer resource on the device to find the error of the 32.768 kHz crystal. Convert the number of error clock pulses per minute (see Equation 17-1). 2.
PIC18F47J53 FAMILY 17.3 Alarm The alarm can also be configured to repeat based on a preconfigured interval. The number of times this occurs, after the alarm is enabled, is stored in the ALRMRPT register. The alarm features and characteristics are: • Configurable from half a second to one year • Enabled using the ALRMEN bit (ALRMCFG<7>, Register 17-4) • Offers one-time and repeat alarm options 17.3.
PIC18F47J53 FAMILY When ALRMCFG = 00 and the CHIME bit = 0 (ALRMCFG<6>), the repeat function is disabled and only a single alarm will occur. The alarm can be repeated up to 255 times by loading the ALRMRPT register with FFh. After each alarm is issued, the ALRMRPT register is decremented by one. Once the register has reached ‘00’, the alarm will be issued one last time. After the alarm is issued a last time, the ALRMEN bit is cleared automatically and the alarm turned off.
PIC18F47J53 FAMILY 17.6 Register Maps Table 17-5, Table 17-6 and Table 17-7 summarize the registers associated with the RTCC module.
PIC18F47J53 FAMILY NOTES: DS39964B-page 256 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 18.0 CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F47J53 family devices have seven CCP (Capture/Compare/PWM) modules, designated CCP4 through CCP10. All the modules implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes. Note: Each CCP module contains a 16-bit register that can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register.
PIC18F47J53 FAMILY REGISTER 18-2: CCPTMRS1: CCP4-10 TIMER SELECT 1 REGISTER (BANKED F51h) R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C7TSEL1 C7TSEL0 — C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 C7TSEL<1:0>: CCP7 Timer Selection bit 00 = CCP7 is based off of TMR1/TMR2 01 = CCP7 is based off of TMR5/TMR4 10 = CCP7 is based off of TMR5/TMR6
PIC18F47J53 FAMILY REGISTER 18-3: CCPTMRS2: CCP4-10 TIMER SELECT 2 REGISTER (BANKED F50h) U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — — — C10TSEL0 — C9TSEL0 C8TSEL1 C8TSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 C10TSEL0: CCP10 Timer Selection bit 0 = CCP10 is based off of TMR1/TMR2 1 = Reserved; do not use bit 3 Unimplemented: Read a
PIC18F47J53 FAMILY REGISTER 18-4: CCPRxL: CCP4-10 PERIOD LOW BYTE REGISTER (4, BANKED F13h; 5, F10h; 6, F0Dh; 7, F0Ah; 8, F07h; 9, F04h; 10, F01h) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CCPRxL7 CCPRxL6 CCPRxL5 CCPRxL4 CCPRxL3 CCPRxL2 CCPRxL1 CCPRxL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown CCPRxL<7:0>: CCPx Period Register Low Byte bits Captu
PIC18F47J53 FAMILY 18.1 CCP Module Configuration TABLE 18-1: Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two eight-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 18.1.
PIC18F47J53 FAMILY 18.1.2 OPEN-DRAIN OUTPUT OPTION The event is selected by the mode select bits, CCP4M<3:0> (CCP4CON<3:0>). When a capture is made, the interrupt request flag bit, CCP4IF (PIR4<1>), is set. (It must be cleared in software.) If another capture occurs before the value in register, CCPR4, is read, the old captured value is overwritten by the new captured value.
PIC18F47J53 FAMILY 18.2.3 SOFTWARE INTERRUPT 18.3.1 When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP4IE bit (PIE4<1>) clear to avoid false interrupts and should clear the flag bit, CCP4IF, following any such change in operating mode. 18.2.4 Switching from one capture prescaler to another may generate an interrupt. Doing that also will not clear the prescaler counter – meaning the first capture may be from a non-zero prescaler.
PIC18F47J53 FAMILY FIGURE 18-2: COMPARE MODE OPERATION BLOCK DIAGRAM CCPR5H Set CCP5IF CCPR5L Special Event Trigger (Timer1/5 Reset) CCP5 Pin Compare Match Comparator S Output Logic Q R TRIS Output Enable 4 CCP5CON<3:0> TMR1H TMR1L TMR5H TMR5L 0 1 C5TSEL0 0 TMR1H TMR1L 1 TMR5H TMR5L Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) C4TSEL1 C4TSEL0 Set CCP4IF Comparator CCPR4H CCP4 Pin Compare Match Output Logic 4 CCPR4L S Q R TRIS Output Enable CCP4CON<3:0> Note:
PIC18F47J53 FAMILY TABLE 18-4: Name INTCON RCON REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1/3/5/7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF IPEN — CM RI TO PD POR BOR PIR4 CCP10IF CCP9IF CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF PIE4 CCP10IE CCP9IE CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE IPR4 CCP10IP CCP9IP CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP TRISB TRISB7 TRISB6 TRISB5 TRISB4
PIC18F47J53 FAMILY 18.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCP4 pin produces up to a 10-bit resolution PWM output. Since the CCP4 pin is multiplexed with a PORTB data latch, the appropriate TRIS bit must be cleared to make the CCP4 pin an output. A PWM output (Figure 18-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
PIC18F47J53 FAMILY 18.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR4L register and to the CCP4CON<5:4> bits. Up to 10-bit resolution is available. The CCPR4L contains the eight MSbs and the CCP4CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR4L:CCP4CON<5:4>.
PIC18F47J53 FAMILY TABLE 18-6: REGISTERS ASSOCIATED WITH PWM AND TIMERS Name INTCON Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF IPEN — CM RI TO PD POR BOR PIR4 PIE4 CCP10IF CCP10IE CCP9IF CCP9IE CCP8IF CCP8IE CCP7IF CCP7IE CCP6IF CCP6IE CCP5IF CCP5IE CCP4IF CCP4IE CCP3IF CCP3IE IPR4 TRISB CCP10IP TRISB7 CCP9IP TRISB6 CCP8IP TRISB5 CCP7IP TRISB4 CCP6IP TRISB3 CCP5IP TRISB2 CCP4IP TRISB1 CCP3IP TRISB0 TRIS
PIC18F47J53 FAMILY 19.0 ENHANCED CAPTURE/COMPARE/PWM (ECCP) MODULE The ECCP modules are implemented as standard CCP modules with enhanced PWM capabilities. These include: PIC18F47J53 family devices have three Enhanced Capture/Compare/PWM (ECCP) modules: ECCP1, ECCP2 and ECCP3. These modules contain a 16-bit register, which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. These ECCP modules are upwardly compatible with CCP.
PIC18F47J53 FAMILY REGISTER 19-1: CCPxCON: ECCP1/2/3 CONTROL (1, ACCESS FBAh; 2, FB4h; 3, BANKED F15h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits If CCPxM<3:2> = 00, 01, 10: xx = PxA assigned as capture/comp
PIC18F47J53 FAMILY REGISTER 19-2: CCPTMRS0: ECCP1/2/3 TIMER SELECT 0 REGISTER (BANKED F52h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 C3TSEL<1:0>: ECCP3 Timer Selection bits 00 = ECCP3 is based off of TMR1/TMR2 01 = ECCP3 is based off of TMR3/TMR4 10 = ECCP3 is
PIC18F47J53 FAMILY 19.1 ECCP Outputs and Configuration The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated PxA through PxD, are routed through the Peripheral Pin Select (PPS) module. Therefore, individual functions can be mapped to any of the remappable I/O pins (RPn). The outputs that are active depend on the ECCP operating mode selected. The pin assignments are summarized in Table 19-3.
PIC18F47J53 FAMILY 19.2.2 TIMER1/TIMER3 MODE SELECTION The timers that are to be used with the capture feature (Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer to be used with each ECCP module is selected in the CCPTMRS0 register (Register 19-2). 19.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated.
PIC18F47J53 FAMILY 19.3 Compare Mode 19.3.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPRx register pair value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the ECCPx pin can be: Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the ECCP module is using the compare feature. In Asynchronous Counter mode, the compare operation will not work reliably. • • • • 19.3.
PIC18F47J53 FAMILY 19.4 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are designated: PxA, PxB, PxC and PxD. The polarity of the PWM pins is configurable and is selected by setting the CCPxM bits in the CCPxCON register appropriately. The Enhanced PWM mode can generate a PWM signal on up to four different output pins with up to 10 bits of resolution. It can do this through four different PWM Output modes: • • • • Table 19-1 provides the pin assignments for each Enhanced PWM mode.
PIC18F47J53 FAMILY TABLE 19-3: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM<1:0> PxA PxB PxC PxD Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: Outputs are enabled by pulse steering in Single mode (see Register 19-5).
PIC18F47J53 FAMILY FIGURE 19-5: ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) EXAMPLE PxM<1:0> Signal PR2 + 1 Pulse Width 0 Period 00 (Single Output) PxA Modulated PxA Modulated 10 (Half-Bridge) Delay(1) Delay(1) PxB Modulated PxA Active 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPRxL<7
PIC18F47J53 FAMILY 19.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the PxA pin, while the complementary PWM output signal is output on the PxB pin (see Figure 19-6). This mode can be used for half-bridge applications, as shown in Figure 19-7, or for full-bridge applications, where four power switches are being modulated with two PWM signals.
PIC18F47J53 FAMILY 19.4.2 FULL-BRIDGE MODE In the Reverse mode, the PxC pin is driven to its active state and the PxB pin is modulated, while the PxA and PxD pins are driven to their inactive state, as shown in Figure 19-9. In Full-Bridge mode, all four pins are used as outputs. An example of a full-bridge application is provided in Figure 19-8. The PxA, PxB, PxC and PxD outputs are multiplexed with the port data latches.
PIC18F47J53 FAMILY FIGURE 19-9: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period PxA (2) Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) Note 1: 2: (1) At this time, the TMR2 register is equal to the PR2 register. The output signal is shown as active-high. DS39964B-page 280 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 19.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the PxM1 bit in the CCPxCON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the PxM1 bit of the CCPxCON register.
PIC18F47J53 FAMILY FIGURE 19-11: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period PxA PxB PW PxC PxD PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: 19.4.3 T = TOFF – TON All signals are shown as active-high. 2: TON is the turn-on delay of power switch, QC, and its driver. 3: TOFF is the turn-off delay of power switch, QD, and its driver.
PIC18F47J53 FAMILY When a shutdown event occurs, two things happen: • The ECCPxASE bit is set to ‘1’. The ECCPxASE will remain set until cleared in firmware or an auto-restart occurs. (See Section 19.4.5 “Auto-Restart Mode”.) • The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs (PxA/PxC) and REGISTER 19-3: (PxB/PxD). The state of each pin pair is determined by the PSSxAC and PSSxBD bits (ECCPxAS<3:0>).
PIC18F47J53 FAMILY FIGURE 19-12: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PxRSEN = 0) PWM Period Shutdown Event ECCPxASE bit PWM Activity Normal PWM Start of PWM Period 19.4.5 Shutdown Event Occurs AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PxRSEN bit (ECCPxDEL<7>).
PIC18F47J53 FAMILY 19.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 19-14: In half-bridge applications, where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period until one switch completely turns off.
PIC18F47J53 FAMILY REGISTER 19-4: ECCPxDEL: ECCP1/2/3 ENHANCED PWM CONTROL REGISTER (1, ACCESS FBDh; 2, FB7h; 3, BANKED F18h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPxASE bit clears automatical
PIC18F47J53 FAMILY REGISTER 19-5: R/W-0 CMPL1 PSTRxCON: PULSE STEERING CONTROL (1, ACCESS FBFh; 2, FB9h; 3, BANKED F1Ah)(1) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 CMPL0 — STRSYNC STRD STRC STRB STRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits 1 = Modulated output pin toggles between PxA an
PIC18F47J53 FAMILY FIGURE 19-16: SIMPLIFIED STEERING BLOCK DIAGRAM 19.4.7.1 The STRSYNC bit of the PSTRxCON register gives the user two choices for when the steering event will happen. When the STRSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRxCON register. In this case, the output signal at the Px pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin.
PIC18F47J53 FAMILY 19.4.8 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change. If the ECCPx pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from HFINTOSC and the postscaler may not be immediately stable.
PIC18F47J53 FAMILY TABLE 19-4: REGISTERS ASSOCIATED WITH ECCP1/2/3 MODULE AND TIMER1/2/3/4/6/8 (CONTINUED) File Name Bit 7 T8CON CCPR1H CCPR1L CCPR2H CCPR2L CCPR3H CCPR3L CCP1CON CCP2CON CCP3CON — Bit 6 Bit 5 T8OUTPS3 T8OUTPS2 Bit 4 T8OUTPS1 T8OUTPS0 Capture/Compare/PWM Register1 High Byte Capture/Compare/PWM Register1 Low Byte Capture/Compare/PWM Register2 High Byte Capture/Compare/PWM Register2 Low Byte Capture/Compare/PWM Register3 High Byte Capture/Compare/PWM Register3 Low Byte P1M1 P1M0 DC1
PIC18F47J53 FAMILY 20.0 All of the MSSP1 module related SPI and I2C I/O functions are hard-mapped to specific I/O pins. MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE For MSSP2 functions: The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices include serial EEPROMs, shift registers, display drivers and A/D Converters. 20.
PIC18F47J53 FAMILY 20.2 Control Registers FIGURE 20-1: Each MSSP module has three associated control registers. These include a status register (SSPxSTAT) and two control registers (SSPxCON1 and SSPxCON2). The use of these registers and their individual Configuration bits differs significantly depending on whether the MSSP module is operated in SPI or I2C mode. Internal Data Bus Read 20.
PIC18F47J53 FAMILY 20.3.1 REGISTERS SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. Each MSSP module has four registers for SPI mode operation. These are: In receive operations, SSPxSR and SSPxBUF together, create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set.
PIC18F47J53 FAMILY REGISTER 20-2: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) (1, ACCESS FC6h; 2, F72h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitti
PIC18F47J53 FAMILY 20.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
PIC18F47J53 FAMILY 20.3.4 ENABLING SPI I/O To enable the serial port, MSSP Enable bit, SSPEN (SSPxCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPxCON1 registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as serial port pins.
PIC18F47J53 FAMILY 20.3.6 MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx. The master determines when the slave (Processor 2, Figure 20-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input).
PIC18F47J53 FAMILY 20.3.7 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin.
PIC18F47J53 FAMILY FIGURE 20-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 SDIx (SMP = 0) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2 SSPxSR to SSPxBUF FIGURE 20-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx bit 7 SDIx (SMP = 0) bit 7 b
PIC18F47J53 FAMILY 20.3.9 OPERATION IN POWER-MANAGED MODES In SPI Master mode, module clocks may be operating at a different speed than when in full-power mode. In the case of Sleep mode, all clocks are halted. In Idle modes, a clock is provided to the peripherals. That clock can be from the primary clock source, the secondary clock (Timer1 oscillator) or the INTOSC source. See Section 3.5 “Clock Sources and Oscillator Switching” for additional information. 20.3.
PIC18F47J53 FAMILY TABLE 20-2: Name REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF (2) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF PIE1 PMPIE (2) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE IPR1 PMPIP(2) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP INTCON PIR1 PMPIF PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF PIE3 SSP2IE BCL2IE RC2IE T
PIC18F47J53 FAMILY 20.4 SPI DMA MODULE 20.4.3 The SPI DMA module contains control logic to allow the MSSP2 module to perform SPI direct memory access transfers. This enables the module to quickly transmit or receive large amounts of data with relatively little CPU intervention. When the SPI DMA module is used, MSSP2 can directly read and write to general purpose SRAM. When the SPI DMA module is not enabled, MSSP2 functions normally, but without DMA capability.
PIC18F47J53 FAMILY 20.4.4.1 DMACON1 The DMACON1 register is used to select the main operating mode of the SPI DMA module. The SSCON1 and SSCON0 bits are used to control the slave select pin. When MSSP2 is used in SPI Master mode with the SPI DMA module, SSDMA can be controlled by the DMA module as an output pin.
PIC18F47J53 FAMILY REGISTER 20-3: DMACON1: DMA CONTROL REGISTER 1 (ACCESS F88h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSCON1 SSCON0 TXINC RXINC DUPLEX1 DUPLEX0 DLYINTEN DMAEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 SSCON<1:0>: SSDMA Output Control bits (Master modes only) 11 = SSDMA is asserted for the duration of 4 bytes; DLYINTEN is alway
PIC18F47J53 FAMILY 20.4.4.2 DMACON2 The DMACON2 register contains control bits for controlling interrupt generation and inter-byte delay behavior. The INTLVL<3:0> bits are used to select when an SSP2IF interrupt should be generated. The function of the DLYCYC<3:0> bits depends on the SPI operating mode (Master/Slave), as well as the DLYINTEN setting. In SPI Master mode, the DLYCYC<3:0> bits can be used REGISTER 20-4: to control how much time the module will Idle between bytes in a transfer.
PIC18F47J53 FAMILY 20.4.4.3 DMABCH and DMABCL The DMABCH and DMABCL register pair forms a 10-bit Byte Count register, which is used by the SPI DMA module to send/receive up to 1,024 bytes for each DMA transaction. When the DMA module is actively running (DMAEN = 1), the DMA Byte Count register decrements after each byte is transmitted/received. The DMA transaction will halt and the DMAEN bit will be automatically cleared by hardware after the last byte has completed.
PIC18F47J53 FAMILY 20.4.6 USING THE SPI DMA MODULE 4. The following steps would typically be taken to enable and use the SPI DMA module: 1. 2. 3. Configure the I/O pins, which will be used by MSSP2. a) Assign SCK2, SDO2, SDI2 and SS2 to the RPn pins as appropriate for the SPI mode which will be used. Only functions which will be used need to be assigned to a pin. b) Initialize the associated LATx registers for the desired Idle SPI bus state.
PIC18F47J53 FAMILY EXAMPLE 20-2: 512-BYTE SPI MASTER MODE Init AND TRANSFER ;For this example, let's use RP5(RB2) for SCK2, ;RP4(RB1) for SDO2, and RP3(RB0) for SDI2 ;Let’s use SPI master mode, CKE = 0, CKP = 0, ;without using slave select signalling.
PIC18F47J53 FAMILY EXAMPLE 20-2: 512-BYTE SPI MASTER MODE Init AND TRANSFER (CONTINUED) ;Somewhere else in our project, lets assume we have ;allocated some RAM for use as SPI receive and ;transmit buffers.
PIC18F47J53 FAMILY 20.5 I2C Mode 20.5.1 The MSSP module in I2C mode fully implements all master and slave functions (including general call support), and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications and 7-bit and 10-bit addressing.
PIC18F47J53 FAMILY REGISTER 20-5: R/W-1 SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) (1, ACCESS FC7h; 2, F73h) R/W-1 SMP CKE R-1 R-1 R-1 D/A (1) (1) P S R-1 R/W (2,3) R-1 R-1 UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Sl
PIC18F47J53 FAMILY REGISTER 20-6: R/W-0 SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C MODE) (1, ACCESS FC6h; 2, F73h) R/W-0 WCOL SSPOV R/W-0 (1) SSPEN R/W-0 CKP R/W-0 (2) SSPM3 R/W-0 SSPM2 (2) R/W-0 (2) SSPM1 R/W-0 SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was a
PIC18F47J53 FAMILY REGISTER 20-7: R/W-0 (3) GCEN SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MASTER MODE) (1, ACCESS FC5h; 2, F71h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only)(3) 1 = Enable interrupt when a general c
PIC18F47J53 FAMILY REGISTER 20-8: R/W-0 GCEN SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ SLAVE MODE) (1, ACCESS FC5h; 2, F71h) R/W-0 ACKSTAT (2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enables interrupt when a general call addres
PIC18F47J53 FAMILY 20.5.2 OPERATION The MSSP module functions are enabled by setting the MSSP Enable bit, SSPEN (SSPxCON1<5>). The SSPxCON1 register allows control of the I2C operation.
PIC18F47J53 FAMILY 20.5.3.2 Address Masking Modes Masking an address bit causes that bit to become a “don’t care”. When one address bit is masked, two addresses will be Acknowledged and cause an interrupt. It is possible to mask more than one address bit at a time, which greatly expands the number of addresses Acknowledged. The I2C slave behaves the same way, whether address masking is used or not.
PIC18F47J53 FAMILY 20.5.3.4 7-Bit Address Masking Mode Unlike 5-Bit Address Masking mode, 7-Bit Address Masking mode uses a mask of up to eight bits (in 10-bit addressing) to define a range of addresses than can be Acknowledged, using the lowest bits of the incoming address. This allows the module to Acknowledge up to 127 different addresses with 7-bit addressing, or 255 with 10-bit addressing (see Example 20-4).
PIC18F47J53 FAMILY 20.5.3.5 Reception 20.5.3.6 When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and the SDAx line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit, BF (SSPxSTAT<0>), is set or bit, SSPOV (SSPxCON1<6>), is set.
2010 Microchip Technology Inc.
DS39964B-page 320 2 A6 Preliminary Note 1: 3 4 X 5 A3 Receiving Address A5 6 X 7 X 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPxBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt.
2010 Microchip Technology Inc.
DS39964B-page 322 2 1 3 1 Preliminary 2: 5 0 7 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR 6 A9 9 A7 2 X 4 5 A3 6 A2 UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with low byte of address 7 X Cleared in software 3 A5 Dummy read of SSPxBUF to clear BF flag 1 A6 Receive Second Byte of Address 8 X 9 ACK 1 D7 4 5 6 Cleared in software 3 D3 D2 7 8 9 1
2010 Microchip Technology Inc.
DS39964B-page 324 2 1 3 1 4 1 Preliminary CKP (SSPxCON1<4>) UA (SSPxSTAT<1>) BF (SSPxSTAT<0>) 5 0 6 7 A9 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S 1 9 ACK R/W = 0 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPxADD needs to be updated 8 A0 Cleared by hardware when SSPxADD is updated with low byte of address 6 A6 A5 A4 A3 A2 A1 Receive Second Byte of Addre
PIC18F47J53 FAMILY 20.5.4 CLOCK STRETCHING 20.5.4.3 Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPxCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCLx pin to be held low at the end of each data receive sequence. 20.5.4.
PIC18F47J53 FAMILY 20.5.4.5 Clock Synchronization and CKP bit When the CKP bit is cleared, the SCLx output is forced to ‘0’. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has FIGURE 20-14: already asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx.
2010 Microchip Technology Inc.
DS39964B-page 328 2 1 3 1 4 1 5 0 Preliminary CKP (SSPxCON1<4>) UA (SSPxSTAT<1>) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) 6 7 A9 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR Cleared in software SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 Cleared in software 3 A5 7 A1 8 A0 Note: An update of the SSPxADD register before the falling edge of the ninth clock will have no effect on UA a
PIC18F47J53 FAMILY 20.5.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPxSR is transferred to the SSPxBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPxIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
PIC18F47J53 FAMILY The following events will cause the MSSP Interrupt Flag bit, SSPxIF, to be set (and MSSP interrupt, if enabled): The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete.
PIC18F47J53 FAMILY 20.5.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDAx while SCLx outputs the serial clock.
PIC18F47J53 FAMILY 20.5.7.1 Baud Rate and Module Interdependence Because this mode derives its basic clock source from the system clock, any changes to the clock will affect both modules in the same proportion. It may be possible to change one or both baud rates back to a previous value by changing the BRG reload value. Because MSSP1 and MSSP2 are independent, they can operate simultaneously in I2C Master mode at different baud rates. This is done by using different BRG reload values for each module.
PIC18F47J53 FAMILY 20.5.7.2 Clock Arbitration sampled high. When the SCLx pin is sampled high, the BRG is reloaded with the contents of SSPxADD<6:0> and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 20-20). Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCLx pin (SCLx allowed to float high).
PIC18F47J53 FAMILY 20.5.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPxCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCLx pin is asserted low. When the SCLx pin is sampled low, the BRG is loaded with the contents of SSPxADD<5:0> and begins counting.
PIC18F47J53 FAMILY 20.5.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the BRG to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted (see data hold time specification, parameter 106).
DS39964B-page 336 S Preliminary R/W PEN SEN BF (SSPxSTAT<0>) SSPxIF SCLx SDAx A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 After Start condition, SEN cleared by hardware SSPxBUF written 1 9 D7 1 SCLx held low while CPU responds to SSPxIF ACK = 0 R/W = 0 SSPxBUF written with 7-bit address and R/W, start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxBUF is written in software Cleared in software service routine from MSSP interrupt
2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 20.5.12 ACKNOWLEDGE SEQUENCE TIMING 20.5.13 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPxCON2<2>). At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the BRG is reloaded and counts down to 0.
PIC18F47J53 FAMILY 20.5.14 SLEEP OPERATION 20.5.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 20.5.15 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 20.5.
PIC18F47J53 FAMILY 20.5.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx is sampled low at the beginning of the Start condition (Figure 20-28). SCLx is sampled low before SDAx is asserted low (Figure 20-29). During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 20-30).
PIC18F47J53 FAMILY FIGURE 20-29: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF.
PIC18F47J53 FAMILY 20.5.17.2 Bus Collision During a Repeated Start Condition If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’; see Figure 20-31). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time.
PIC18F47J53 FAMILY 20.5.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the BRG is loaded with SSPxADD<6:0> and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 20-33).
PIC18F47J53 FAMILY TABLE 20-4: Name INTCON REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PMPIF (3) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF PIE1 PMPIE(3) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE IPR1 PMPIP(3) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF HLVDIF TMR3IF CCP2IF PIE2 OSCFIE CM2IE CM1IE USBIE
PIC18F47J53 FAMILY 21.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of two serial I/O modules. (Generically, the EUSART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers.
PIC18F47J53 FAMILY REGISTER 21-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER (1, ACCESS FADh; 2, FA8h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
PIC18F47J53 FAMILY REGISTER 21-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER (1, ACCESS FACh; 2, FC9h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port d
PIC18F47J53 FAMILY REGISTER 21-3: BAUDCONx: BAUD RATE CONTROL REGISTER (ACCESS F7Eh, F7Ch) R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in
PIC18F47J53 FAMILY 21.1 Baud Rate Generator (BRG) The BRG is a dedicated, 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) selects 16-bit mode. Writing a new value to the SPBRGHx:SPBRGx registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. 21.1.
PIC18F47J53 FAMILY EXAMPLE 21-1: CALCULATING BAUD RATE ERROR For a device with Fosc of 16 MHz, desired baud rate of 9600, Asynchronous mode, and 8-bit BRG: Desired Baud Rate = Fosc/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((Fosc/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate=16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.
PIC18F47J53 FAMILY TABLE 21-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error — — — — — 1.221 2.441 1.73 255 9.615 0.16 64 19.531 1.73 56.818 -1.36 125.000 8.51 Actual Rate (K) % Error 0.3 1.2 — — 2.4 9.6 19.2 57.6 115.2 SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error — 1.73 — 255 — 1.202 2.404 0.16 129 9.766 1.73 31 31 19.531 1.73 15 10 62.
PIC18F47J53 FAMILY TABLE 21-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG value (decimal) Actual Rate (K) % Error SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error FOSC = 8.000 MHz SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1.2 1.200 0.02 2082 1.200 -0.
PIC18F47J53 FAMILY 21.1.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source.
PIC18F47J53 FAMILY FIGURE 21-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh RXx pin 0000h 001Ch Start Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by User ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
PIC18F47J53 FAMILY 21.2 EUSART Asynchronous Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx register is empty and the TXxIF flag bit is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF will be set regardless of the state of TXxIE; it cannot be cleared in software.
PIC18F47J53 FAMILY FIGURE 21-4: ASYNCHRONOUS TRANSMISSION Write to TXREGx Word 1 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer Reg. Empty Flag) 1 TCY Word 1 Transmit Shift Reg TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 21-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREGx Word 2 Word 1 BRG Output (Shift Clock) TXx (pin) Start bit 1 TCY TXxIF bit (Interrupt Reg.
PIC18F47J53 FAMILY 21.2.2 EUSART ASYNCHRONOUS RECEIVER 21.2.3 The receiver block diagram is displayed in Figure 21-6. The data is received on the RXx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter, operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
PIC18F47J53 FAMILY FIGURE 21-7: ASYNCHRONOUS RECEPTION Start bit RXx (pin) bit 0 bit 1 bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg Start bit bit 0 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREGx Word 1 RCREGx Read Rcv Buffer Reg RCREGx bit 7/8 RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set.
PIC18F47J53 FAMILY 21.2.4.2 The WUE bit is automatically cleared once a low-to-high transition is observed on the RXx line following the wake-up event. At this point, the EUSART module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over. 21.2.4.1 The timing of WUE and RCxIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSART in an Idle mode.
PIC18F47J53 FAMILY 21.2.5 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN/J2602 bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTAx<3> and TXSTAx<5>) are set while the Transmit Shift Register is loaded with data.
PIC18F47J53 FAMILY 21.3 EUSART Synchronous Master Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF is set regardless of the state of enable bit, TXxIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREGx register.
PIC18F47J53 FAMILY FIGURE 21-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/CCP10/PMA4/RX1/DT1/ SDO1/RP18 Pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/CCP9/PMA5/TX1/CK1/ RP17 Pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit Note: This example is equally applicable to EUSART2 (RPn1/TX2/CK2 and RPn2/RX2/DT2).
PIC18F47J53 FAMILY 21.3.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTAx<5>) or the Continuous Receive Enable bit, CREN (RCSTAx<4>). Data is sampled on the RXx pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence.
PIC18F47J53 FAMILY TABLE 21-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name INTCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF (1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF PIE1 (1) PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE IPR1 PMPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP PIR1 PMPIF PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF PIE3 SSP2IE
PIC18F47J53 FAMILY 21.4 EUSART Synchronous Slave Mode e) Synchronous Slave mode is entered by clearing bit, CSRC (TXSTAx<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CKx pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 21.4.1 To set up a Synchronous Slave Transmission: 1. 2. 3. 4. 5.
PIC18F47J53 FAMILY 21.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit, SREN, which is a “don’t care” in Slave mode. 2. 3. 4. 5. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode.
PIC18F47J53 FAMILY 22.0 10/12-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module in the PIC18F47J53 family of devices has 10 inputs for the 28-pin devices and 13 inputs for the 44-pin devices. This module allows conversion of an analog input signal to a corresponding 10 or 12-bit digital number.
PIC18F47J53 FAMILY REGISTER 22-1: R/W-0 ADCON0: A/D CONTROL REGISTER 0 (ACCESS FC2h) R/W-0 VCFG1 VCFG0 R/W-0 CHS3 (2) R/W-0 CHS2 (2) R/W-0 CHS1 (2) R/W-0 CHS0 (2) R/W-0 R/W-0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = AVSS(4) bit 6 VCFG0: Voltage Reference Configuration bit (VREF+ sou
PIC18F47J53 FAMILY REGISTER 22-2: ADCON1: A/D CONTROL REGISTER 1 (ACCESS FC1h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ADCAL ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 ADCAL: A/D Calibration bit 1 = Calibration is performed on the next A/D conver
PIC18F47J53 FAMILY REGISTER 22-3: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) U-1 U-1 U-1 U-1 R/WO-1 U-0 R/WO-1 R/WO-1 — — — — MSSPMSK — ADCSEL IOL1WAY bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’ bit 3 MSSPMSK: MSSP 7-Bit Address Masking Mode Enable bit 1 = 7-
PIC18F47J53 FAMILY The ANCON0 and ANCON1 registers are used to configure the operation of the I/O pin associated with each analog channel. Setting any one of the PCFG bits configures the corresponding pin to operate as a digital only I/O. Clearing a bit configures the pin to operate as an analog input for either the A/D Converter or the comparator module. All digital peripherals are disabled and digital inputs read as ‘0’.
PIC18F47J53 FAMILY Each port pin associated with the A/D Converter can be configured as an analog input or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0<1>) is cleared and the A/D Interrupt Flag bit, ADIF, is set.
PIC18F47J53 FAMILY After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine acquisition time, see Section 22.1 “A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. 2.
PIC18F47J53 FAMILY 22.1 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is illustrated in Figure 22-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor, CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
PIC18F47J53 FAMILY 22.2 Selecting and Configuring Automatic Acquisition Time TABLE 22-1: The ADCON1 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit.
PIC18F47J53 FAMILY 22.5 A/D Conversions 22.6 Figure 22-3 displays the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. Figure 22-4 displays the operation of the A/D Converter after the GO/DONE bit has been set, the ACQT<2:0> bits are set to ‘010’ and selecting a 4 TAD acquisition time before the conversion starts.
PIC18F47J53 FAMILY FIGURE 22-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b9 b8 b3 b5 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit Next Q4: ADRESH/ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.
PIC18F47J53 FAMILY 22.8 Operation in Power-Managed Modes mode clock source until the conversion has been completed. If desired, the device may be placed into the corresponding power-managed Idle mode during the conversion. The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the power-managed mode clock frequency is less than 1 MHz, the A/D RC clock source should be selected.
PIC18F47J53 FAMILY 23.0 UNIVERSAL SERIAL BUS (USB) 23.1 PIC18F47J53 family devices contain a full-speed and low-speed, compatible USB Serial Interface Engine (SIE) that allows fast communication between any USB host and the PIC® MCU. The SIE can be interfaced directly to the USB, utilizing the internal transceiver. This section describes the details of the USB peripheral. Because of the very specific nature of the module, knowledge of USB is expected.
PIC18F47J53 FAMILY 23.2 USB Status and Control The operation of the USB module is configured and managed through three control registers. In addition, a total of 22 registers are used to manage the actual USB transactions. The registers are: • • • • • • USB Control register (UCON) USB Configuration register (UCFG) USB Transfer Status register (USTAT) USB Device Address register (UADDR) Frame Number registers (UFRMH:UFRML) Endpoint Enable registers 0 through 15 (UEPn) 23.2.
PIC18F47J53 FAMILY REGISTER 23-1: UCON: USB CONTROL REGISTER (ACCESS F65h) U-0 R/W-0 R-x R/C-0 R/W-0 R/W-0 R/W-0 U-0 — PPBRST(2) SE0 PKTDIS USBEN(1) RESUME SUSPND — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 PPBRST: Ping-Pong Buffers Reset bit(2) 1 = Reset all Ping-Pong Buffer Pointers to the Even Buf
PIC18F47J53 FAMILY The PPBRST bit (UCON<6>) controls the Reset status when Double-Buffering mode (ping-pong buffering) is used. When the PPBRST bit is set, all Ping-Pong Buffer Pointers are set to the Even buffers. PPBRST has to be cleared by firmware. This bit is ignored in buffering modes not using ping-pong buffering. The PKTDIS bit (UCON<4>) is a flag indicating that the SIE has disabled packet transmission and reception.
PIC18F47J53 FAMILY REGISTER 23-2: R/W-0 UCFG: USB CONFIGURATION REGISTER (BANKED F39h) R/W-0 UTEYE UOEMON U-0 — R/W-0 UPUEN (1,2) R/W-0 UTRDIS (1,3) R/W-0 (1) FSEN R/W-0 R/W-0 PPB1 PPB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test is enabled 0 = Eye pattern test is disabled bit 6 UOEMON: USB OE Moni
PIC18F47J53 FAMILY 23.2.2.2 23.2.2.4 Internal Pull-up Resistors The PIC18F47J53 family devices have built-in pull-up resistors designed to meet the requirements for low-speed and full-speed USB. The UPUEN bit (UCFG<4>) enables the internal pull-ups. Figure 23-1 shows the pull-ups and their control. Note: 23.2.2.3 A compliant USB device should never source any current onto the +5V VBUS line of the USB cable.
PIC18F47J53 FAMILY 23.2.3 USB STATUS REGISTER (USTAT) The USB Status register reports the transaction status within the SIE. When the SIE issues a USB transfer complete interrupt, USTAT should be read to determine the status of the transfer. USTAT contains the transfer endpoint number, direction and Ping-Pong Buffer Pointer value (if used). Note: The data in the USB Status register is valid only when the TRNIF interrupt flag is asserted.
PIC18F47J53 FAMILY 23.2.4 USB ENDPOINT CONTROL Each of the 16 possible bidirectional endpoints has its own independent control register, UEPn (where ‘n’ represents the endpoint number). Each register has an identical complement of control bits. Register 23-4 provides the prototype. The EPHSHK bit (UEPn<4>) controls handshaking for the endpoint; setting this bit enables USB handshaking. Typically, this bit is always set except when using isochronous endpoints.
PIC18F47J53 FAMILY 23.2.5 USB ADDRESS REGISTER (UADDR) FIGURE 23-4: The USB Address register contains the unique USB address that the peripheral will decode when active. UADDR is reset to 00h when a USB Reset is received, indicated by URSTIF, or when a Reset is received from the microcontroller. The USB address must be written by the microcontroller during the USB setup phase (enumeration) as part of the Microchip USB firmware support. 23.2.
PIC18F47J53 FAMILY 23.4 Buffer Descriptors and the Buffer Descriptor Table FIGURE 23-5: Address The registers in Bank 13 are used specifically for endpoint buffer control in a structure known as the Buffer Descriptor Table (BDT). This provides a flexible method for users to construct and control endpoint buffers of various lengths and configuration. The BDT is composed of Buffer Descriptors (BD) which are used to define and control the actual buffers in the USB RAM space.
PIC18F47J53 FAMILY The BDnSTAT byte of the BDT should always be the last byte updated when preparing to arm an endpoint. The SIE will clear the UOWN bit when a transaction has completed. No hardware mechanism exists to block access when the UOWN bit is set. Thus, unexpected behavior can occur if the microcontroller attempts to modify memory when the SIE owns it. Similarly, reading such memory may produce inaccurate data until the USB peripheral returns ownership to the microcontroller. 23.4.1.
PIC18F47J53 FAMILY REGISTER 23-5: R/W-x UOWN(1) BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH BD63STAT), CPU MODE R/W-x U-0 U-0 (2) (3) (3) DTS — — R/W-x R/W-x R/W-x R/W-x DTSEN BSTALL BC9 BC8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UOWN: USB Own bit(1) 0 = The microcontroller core owns the BD and its corresponding buffer bit 6 DTS: D
PIC18F47J53 FAMILY 23.4.1.3 BDnSTAT Register (SIE Mode) When the BD and its buffer are owned by the SIE, most of the bits in BDnSTAT take on a different meaning. The configuration is shown in Register 23-6. Once UOWN is set, any data or control settings previously written there by the user will be overwritten with data from the SIE. The BDnSTAT register is updated by the SIE with the token Packet Identifier (PID) which is stored in BDnSTAT<5:2>.
PIC18F47J53 FAMILY 23.4.4 PING-PONG BUFFERING the completion of a transaction (UOWN cleared by the SIE), the pointer is toggled to the Odd BD. After the completion of the next transaction, the pointer is toggled back to the Even BD and so on. An endpoint is defined to have a ping-pong buffer when it has two sets of BD entries: one set for an Even transfer and one set for an Odd transfer. This allows the CPU to process one BD while the SIE is processing the other BD.
PIC18F47J53 FAMILY TABLE 23-2: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT BUFFERING MODES BDs Assigned to Endpoint Mode 0 (No Ping-Pong) Endpoint Out Mode 1 (Ping-Pong on EP0 OUT) In Out Mode 2 (Ping-Pong on all EPs) In Out In Mode 3 (Ping-Pong on all other EPs, except EP0) Out In 0 0 1 0 (E), 1 (O) 2 0 (E), 1 (O) 2 (E), 3 (O) 0 1 1 2 3 3 4 4 (E), 5 (O) 6 (E), 7 (O) 2 (E), 3 (O) 4 (E), 5 (O) 2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O) 6 (E), 7 (O) 8 (E), 9 (O) 3 6
PIC18F47J53 FAMILY 23.5 USB Interrupts Figure 23-7 provides the interrupt logic for the USB module. There are two layers of interrupt registers in the USB module. The top level consists of overall USB status interrupts; these are enabled and flagged in the UIE and UIR registers, respectively. The second level consists of USB error conditions, which are enabled and flagged in the UEIR and UEIE registers. An interrupt condition in any of these triggers a USB Error Interrupt Flag (UERRIF) in the top level.
PIC18F47J53 FAMILY 23.5.1 USB INTERRUPT STATUS REGISTER (UIR) When the USB module is in the Low-Power Suspend mode (UCON<1> = 1), the SIE does not get clocked. When in this state, the SIE cannot process packets, and therefore, cannot detect new interrupt conditions other than the Activity Detect Interrupt, ACTVIF. The ACTVIF bit is typically used by USB firmware to detect when the microcontroller should bring the USB module out of the Low-Power Suspend mode (UCON<1> = 0).
PIC18F47J53 FAMILY 23.5.1.1 Bus Activity Detect Interrupt Bit (ACTVIF) The ACTVIF bit cannot be cleared immediately after the USB module wakes up from Suspend mode or while the USB module is suspended. A few clock cycles are required to synchronize the internal hardware state machine before the ACTVIF bit can be cleared by firmware. Clearing the ACTVIF bit before the internal hardware is synchronized may not have an effect on the value of ACTVIF.
PIC18F47J53 FAMILY 23.5.2 USB INTERRUPT ENABLE REGISTER (UIE) The USB Interrupt Enable (UIE) register (Register 23-8) contains the enable bits for the USB status interrupt sources. Setting any of these bits will enable the respective interrupt source in the UIR register. REGISTER 23-8: The values in this register only affect the propagation of an interrupt condition to the microcontroller’s interrupt logic.
PIC18F47J53 FAMILY 23.5.3 USB ERROR INTERRUPT STATUS REGISTER (UEIR) The USB Error Interrupt Status register (Register 23-9) contains the flag bits for each of the error sources within the USB peripheral. Each of these sources is controlled by a corresponding interrupt enable bit in the UEIE register. All of the USB error flags are ORed together to generate the USB Error Interrupt Flag (UERRIF) at the top level of the interrupt logic.
PIC18F47J53 FAMILY 23.5.4 USB ERROR INTERRUPT ENABLE REGISTER (UEIE) As with the UIE register, the enable bits only affect the propagation of an interrupt condition to the microcontroller’s interrupt logic. The flag bits are still set by their interrupt conditions, allowing them to be polled and serviced without actually generating an interrupt. The USB Error Interrupt Enable register (Register 23-10) contains the enable bits for each of the USB error interrupt sources.
PIC18F47J53 FAMILY 23.6 USB Power Modes Many USB applications will likely have several different sets of power requirements and configuration. The most common power modes encountered are Bus Power Only, Self-Power Only and Dual Power with Self-Power Dominance. The most common cases are presented here. Also provided is a means of estimating the current consumption of the USB transceiver. 23.6.1 The application should never source any current onto the 5V VBUS pin of the USB cable.
PIC18F47J53 FAMILY 23.6.4 USB TRANSCEIVER CURRENT CONSUMPTION The USB transceiver consumes a variable amount of current depending on the characteristic impedance of the USB cable, the length of the cable, the VUSB supply voltage and the actual data patterns moving across the USB cable. Longer cables have larger capacitances and consume more total energy when switching output states. Data patterns that consist of “IN” traffic consume far more current than “OUT” traffic.
PIC18F47J53 FAMILY EQUATION 23-2: CALCULATING USB TRANSCEIVER CURRENT† For this example, the following assumptions are made about the application: • 3.3V will be applied to VUSB and VDD, with the core voltage regulator enabled. • This is a full-speed application that uses one interrupt IN endpoint that can send one packet of 64 bytes every 1 ms, with no restrictions on the values of the bytes being sent. The application may or may not have additional traffic on OUT endpoints.
PIC18F47J53 FAMILY 23.7 Oscillator 23.8 The USB module has specific clock requirements. For full-speed operation, the clock source must be 48 MHz. Even so, the microcontroller core and other peripherals are not required to run at that clock speed. Available clocking options are described in detail in Section 3.3 “Oscillator Settings for USB”. TABLE 23-4: Name INTCON USB Firmware and Drivers Microchip provides a number of application-specific resources, such as USB firmware and driver support.
PIC18F47J53 FAMILY 23.9 Overview of USB 23.9.2 This section presents some of the basic USB concepts and useful information necessary to design a USB device. Although much information is provided in this section, there is a plethora of information provided within the USB specifications and class specifications. Thus, the reader is encouraged to refer to the USB specifications for more information (www.usb.org).
PIC18F47J53 FAMILY The USB Specification limits the power taken from the bus. Each device is ensured 100 mA at approximately 5V (one unit load). Additional power may be requested, up to a maximum of 500 mA. Note that power above one unit load is a request and the host or hub is not obligated to provide the extra current. Thus, a device capable of consuming more than one unit load must be able to maintain a low-power configuration of a one unit load or less, if necessary.
PIC18F47J53 FAMILY NOTES: DS39964B-page 406 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 24.0 COMPARATOR MODULE 24.1 The analog comparator module contains three comparators that can be independently configured in a variety of ways. The inputs can be selected from the analog inputs and two internal voltage references. The digital outputs are available at the pin level and can also be read through the control register. Multiple output and interrupt event generation is also available. Figure 24-1 provides a generic single comparator from the module.
PIC18F47J53 FAMILY REGISTER 24-1: CMxCON: COMPARATOR CONTROL 1/2/3 REGISTER (1, ACCESS FD2h; 2, FD1h; 3, BANKED F25h) R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 6 COE: Comparator Ou
PIC18F47J53 FAMILY REGISTER 24-2: CMSTAT: COMPARATOR STATUS REGISTER (ACCESS F70h) U-0 U-0 U-0 U-0 U-0 R-1 R-1 R-1 — — — — — COUT3 COUT2 COUT1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 COUT<3:1>: Comparator x Status bits (For example, COUT3 gives the status for Comparator 3.
PIC18F47J53 FAMILY 24.2 Comparator Operation 24.3 Comparator Response Time A single comparator is shown in Figure 24-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input, VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input, VIN-, the output of the comparator is a digital high level.
PIC18F47J53 FAMILY 24.5 Comparator Control and Configuration Each comparator has up to eight possible combinations of inputs: up to four external analog inputs and one of two internal voltage references. Both comparators allow a selection of the signal from pin, CxINA, or the voltage from the comparator reference (CVREF) on the non-inverting channel. This is compared to either CxINB, CxINC, CxIND, CTMU or the microcontroller’s fixed internal reference voltage (VIRV, 0.6V nominal) on the inverting channel.
PIC18F47J53 FAMILY 24.6 Comparator Interrupts When EVPOL<1:0> = 11, the comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMSTAT<1:0>, to determine the actual change that occurred. The CMxIF bits (PIR2<6:5>) are the Comparator x Interrupt Flags. The CMxIF bits must be reset by clearing them.
PIC18F47J53 FAMILY 24.7 Comparator Operation During Sleep 24.8 A device Reset forces the CMxCON registers to their Reset state. This forces both comparators and the voltage reference to the OFF state. When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional, if enabled. This interrupt will wake-up the device from Sleep mode when enabled. Each operational comparator will consume additional current.
PIC18F47J53 FAMILY NOTES: DS39964B-page 414 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 25.0 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. FIGURE 25-1: Figure 25-1 provides a block diagram of the module.
PIC18F47J53 FAMILY 25.1 Configuring the Comparator Voltage Reference The comparator voltage reference module is controlled through the CVRCON register (Register 25-1). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR<3:0>), with one range offering finer resolution.
PIC18F47J53 FAMILY 25.2 Voltage Reference Accuracy/Error The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. See Figure 25-2 for an example buffering technique. The full range of voltage reference cannot be realized due to the construction of the module.
PIC18F47J53 FAMILY NOTES: DS39964B-page 418 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 26.0 HIGH/LOW VOLTAGE DETECT (HLVD) The High/Low-Voltage Detect (HLVD) module can be used to monitor the absolute voltage on VDD or the HLVDIN pin. This is a programmable circuit that allows the user to specify both a device voltage trip point and the direction of change from that point. The High/Low-Voltage Detect Control register (Register 26-1) completely controls the operation of the HLVD module.
PIC18F47J53 FAMILY 26.1 Operation The trip point voltage is software programmable to any one of 16 values. The trip point is selected by programming the HLVDL<3:0> bits (HLVDCON<3:0>). When the HLVD module is enabled, a comparator uses an internally generated reference voltage as the set point. The set point is compared with the trip point, where each node in the resistor divider represents a trip point voltage.
PIC18F47J53 FAMILY 26.2 HLVD Setup 26.4 To set up the HLVD module: 1. 2. 3. 4. 5. 6. Disable the module by clearing the HLVDEN bit (HLVDCON<4>). Write the value to the HLVDL<3:0> bits that select the desired HLVD trip point. Set the VDIRMAG bit to detect one of the following: • High voltage (VDIRMAG = 1) • Low voltage (VDIRMAG = 0) Enable the HLVD module by setting the HLVDEN bit. Clear the HLVD Interrupt Flag, HLVDIF (PIR2<2>), which may have been set from a previous interrupt.
PIC18F47J53 FAMILY FIGURE 26-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) CASE 1: HLVDIF may not be set VDD VHLVD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is stable HLVDIF cleared in software CASE 2: VDD VHLVD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists DS39964B-page 422 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY FIGURE 26-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VHLVD VDD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VHLVD VDD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists 26.
PIC18F47J53 FAMILY 26.6 Operation During Sleep 26.7 When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 26-1: Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off.
PIC18F47J53 FAMILY 27.
PIC18F47J53 FAMILY 27.1 CTMU Operation The CTMU works by using a fixed current source to charge a circuit. The type of circuit depends on the type of measurement being made. In the case of charge measurement, the current is fixed and the amount of time the current is applied to the circuit is fixed. The amount of voltage read by the A/D is then a measurement of the capacitance of the circuit. In the case of time measurement, the current, as well as the capacitance of the circuit, is fixed.
PIC18F47J53 FAMILY 27.1.5 INTERRUPTS The CTMU sets its interrupt flag (PIR3<2>) whenever the current source is enabled, then disabled. An interrupt is generated only if the corresponding interrupt enable bit (PIE3<2>) is also set. If edge sequencing is not enabled (i.e., Edge 1 must occur before Edge 2), it is necessary to monitor the edge status bits and determine which edge occurred last and caused the interrupt. 27.
PIC18F47J53 FAMILY The CTMU current source may be trimmed with the trim bits in CTMUICON using an iterative process to get an exact desired current. Alternatively, the nominal value without adjustment may be used; it may be stored by the software for use in all subsequent capacitive or time measurements. To calculate the value for RCAL, the nominal current must be chosen and then the resistance can be calculated. For example, if the A/D Converter reference voltage is 3.3V, use 70% of full scale or 2.
PIC18F47J53 FAMILY EXAMPLE 27-1: SETUP FOR CTMU CALIBRATION ROUTINES #include
PIC18F47J53 FAMILY EXAMPLE 27-2: CURRENT CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 500 #define DELAY for(i=0;i
PIC18F47J53 FAMILY 27.3.2 CAPACITANCE CALIBRATION There is a small amount of capacitance from the internal A/D Converter sample capacitor as well as stray capacitance from the circuit board traces and pads that affect the precision of capacitance measurements. A measurement of the stray capacitance can be taken by making sure the desired capacitance to be measured has been removed. The measurement is then performed using the following steps: 1. 2. 3. 4. 5. 6. Initialize the A/D Converter and the CTMU.
PIC18F47J53 FAMILY EXAMPLE 27-3: CAPACITANCE CALIBRATION ROUTINE #include "p18cxxx.h" #define #define #define #define #define #define COUNT 25 ETIME COUNT*2.5 DELAY for(i=0;i
PIC18F47J53 FAMILY 27.4 Measuring Capacitance with the CTMU There are two separate methods of measuring capacitance with the CTMU. The first is the absolute method, in which the actual capacitance value is desired. The second is the relative method, in which the actual capacitance is not needed, rather an indication of a change in capacitance is required. 27.4.
PIC18F47J53 FAMILY EXAMPLE 27-4: ROUTINE FOR CAPACITIVE TOUCH SWITCH #include "p18cxxx.h" #define #define #define #define COUNT 500 DELAY for(i=0;i
PIC18F47J53 FAMILY 27.5 Measuring Time with the CTMU Module It is assumed that the time measured is small enough that the capacitance, COFFSET, provides a valid voltage to the A/D Converter. For the smallest time measurement, always set the A/D Channel Select register (AD1CHS) to an unused A/D channel; the corresponding pin for which is not connected to any circuit board trace. This minimizes added stray capacitance, keeping the total circuit capacitance close to that of the A/D Converter itself (4-5 pF).
PIC18F47J53 FAMILY 27.6 Creating a Delay with the CTMU Module An example use of this feature is for interfacing with variable capacitive-based sensors, such as a humidity sensor. As the humidity varies, the pulse width output on CTPLS will vary. The CTPLS output pin can be connected to an input capture pin and the varying pulse width is measured to determine the humidity in the application.
PIC18F47J53 FAMILY 27.9 Registers The CTMUCONH and CTMUCONL registers (Register 27-1 and Register 27-2) contain control bits for configuring the CTMU module edge source selection, edge source polarity selection, edge sequencing, A/D trigger, analog circuit capacitor discharge and enables. The CTMUICON register (Register 27-3) has bits for selecting the current source range and current source trim.
PIC18F47J53 FAMILY REGISTER 27-2: CTMUCONL: CTMU CONTROL REGISTER LOW (ACCESS FB2h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x R/W-x EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge response 0 = Edge 2 is programmed for a negative ed
PIC18F47J53 FAMILY REGISTER 27-3: CTMUICON: CTMU CURRENT CONTROL REGISTER (ACCESS FB1h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . .
PIC18F47J53 FAMILY NOTES: DS39964B-page 440 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 28.0 SPECIAL FEATURES OF THE CPU PIC18F47J53 family devices include several features intended to maximize reliability and minimize cost through elimination of external components. These are: • Oscillator Selection • Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) • Two-Speed Start-up • Code Protection • In-Circuit Serial Programming (ICSP) 28.1.
PIC18F47J53 FAMILY TABLE 28-1: MAPPING OF THE FLASH CONFIGURATION WORDS TO THE CONFIGURATION REGISTERS Configuration Register (Volatile) Configuration Register Address Flash Configuration Byte Address 300000h XXXF8h CONFIG1L CONFIG1H 300001h XXXF9h CONFIG2L 300002h XXXFAh CONFIG2H 300003h XXXFBh CONFIG3L 300004h XXXFCh CONFIG3H 300005h XXXFDh CONFIG4L 300006h XXXFEh CONFIG4H 300007h XXXFFh TABLE 28-2: CONFIGURATION BITS AND DEVICE IDs File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit
PIC18F47J53 FAMILY REGISTER 28-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 DEBUG XINST STVREN CFGPLLEN PLLDIV2 PLLDIV1 PLLDIV0 WDTEN bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled; RB6 and RB7 configured as
PIC18F47J53 FAMILY REGISTER 28-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) U-1 U-1 U-1 U-1 U-0 R/WO-1 R/WO-1 R/WO-1 — — — — — CP0 CPDIV1 CPDIV0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’ bit 3 Unimplemented: Maintain as ‘0’ bit 2 CP0: Code Protection bit
PIC18F47J53 FAMILY REGISTER 28-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) R/WO-1 R/WO-1 R/WO-1 IESO FCMEN CLKOEC R/WO-1 R/WO-1 SOSCSEL1 SOSCSEL0 R/WO-1 R/WO-1 R/WO-1 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit 1 = Two-Speed Start-up is e
PIC18F47J53 FAMILY REGISTER 28-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-1 U-1 U-1 U-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 — — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’ bit 3-0 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1
PIC18F47J53 FAMILY REGISTER 28-5: R/WO-1 DSWDTPS3 CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) R/WO-1 (1) R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 DSWDTPS2(1) DSWDTPS1(1) DSWDTPS0(1) DSWDTEN(1) DSBOREN RTCOSC DSWDTOSC(1) bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 DSWDTPS<3:0>: Deep Sleep Watchdog Timer Postscale Select bits(1) The DSWDT pre
PIC18F47J53 FAMILY REGISTER 28-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) U-1 U-1 U-1 U-1 R/WO-1 U-0 R/WO-1 R/WO-1 — — — — MSSPMSK — ADCSEL IOL1WAY bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’ bit 3 MSSPMSK: MSSP 7-Bit Address Masking Mode Enable bit 1 = 7-
PIC18F47J53 FAMILY REGISTER 28-8: CONFIG4H: CONFIGURATION REGISTER 4 HIGH (BYTE ADDRESS 300007h) U-1 U-1 U-1 U-1 R/WO-1 U-0 R/WO-1 R/WO-1 — — — — LS48MHZ — WPEND WPDIS bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’ bit 3 LS48MHZ: Low-Speed USB Clock Selection 1 = 48-MHz system cloc
PIC18F47J53 FAMILY REGISTER 28-10: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F47J53 FAMILY DEVICES (BYTE ADDRESS 3FFFFFh) R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown DEV<10:3>: Device ID bits These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.
PIC18F47J53 FAMILY 28.2 Watchdog Timer (WDT) PIC18F47J53 family devices have both a conventional WDT circuit and a dedicated, Deep Sleep capable Watchdog Timer. When enabled, the conventional WDT operates in normal Run, Idle and Sleep modes. This data sheet section describes the conventional WDT circuit. The dedicated, Deep Sleep capable WDT can only be enabled in Deep Sleep mode. This timer is described in Section 4.6.4 “Deep Sleep Watchdog Timer (DSWDT)”.
PIC18F47J53 FAMILY REGISTER 28-11: WDTCON: WATCHDOG TIMER CONTROL REGISTER (ACCESS FC0h) R/W-1 R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 REGSLP LVDSTAT(2) ULPLVL VBGOE DS(2) ULPEN ULPSINK SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 REGSLP: Voltage Regulator Low-Power Operation Enable bit 1 = On-chip regulator enters low-power operation when device ente
PIC18F47J53 FAMILY 28.3 On-Chip Voltage Regulator Note 1: The on-chip voltage regulator is only available in parts designated with an “F”, such as PIC18F26J53. The on-chip regulator is disabled on devices with “LF” in their part number. 2: The VDDCORE/VCAP pin must never be left floating. On “F” devices, it must be connected to a capacitor, of size CEFC, to ground. On “LF” devices, VDDCORE/VCAP must be connected to a power supply source between 2.0V and 2.7V.
PIC18F47J53 FAMILY FIGURE 28-2: CONNECTIONS FOR THE ON-CHIP REGULATOR PIC18FXXJ53 Devices (Regulator Enabled): 3.3V PIC18FXXJ53 VDD VDDCORE/VCAP CF VSS PIC18LFXXJ53 Devices (Regulator Disabled): 2.5V PIC18LFXXJ53 VDD VDDCORE/VCAP VSS OR 2.5V 3.3V PIC18LFXXJ53 VDD VDDCORE/VCAP VSS 28.3.2 ON-CHIP REGULATOR AND BOR When the on-chip regulator is enabled, PIC18F47J53 family devices also have a simple brown-out capability.
PIC18F47J53 FAMILY 28.4 Two-Speed Start-up The Two-Speed Start-up feature helps to minimize the latency period, from oscillator start-up to code execution, by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO Configuration bit.
PIC18F47J53 FAMILY FIGURE 28-4: FSCM BLOCK DIAGRAM Clock Monitor Latch (edge-triggered) Peripheral Clock INTRC Source (32 s) ÷ 64 S Q C Q The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block fails, no failure would be detected, nor would any action be possible. 488 Hz (2.048 ms) Clock Failure Detected Clock failure is tested for on the falling edge of the sample clock.
PIC18F47J53 FAMILY 28.5.2 EXITING FAIL-SAFE OPERATION The Fail-Safe Clock Monitor condition is terminated by either a device Reset or by entering a power-managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 2H (with any required start-up delays that are required for the oscillator mode, such as the OST or PLL timer). The INTRC oscillator provides the device clock until the primary clock source becomes ready (similar to a Two-Speed Start-up).
PIC18F47J53 FAMILY 28.7 In-Circuit Serial Programming™ (ICSP™) PIC18F47J53 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
PIC18F47J53 FAMILY 29.0 INSTRUCTION SET SUMMARY The PIC18F47J53 family of devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 29.
PIC18F47J53 FAMILY TABLE 29-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
PIC18F47J53 FAMILY TABLE 29-1: OPCODE FIELD DESCRIPTIONS (CONTINUED) Field Description [expr] Specifies bit n of the register indicated by the pointer expr. Assigned to. < > Register bit field. In the set of. italics User-defined term (font is Courier New).
PIC18F47J53 FAMILY TABLE 29-2: PIC18F47J53 FAMILY INSTRUCTION SET Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a
PIC18F47J53 FAMILY TABLE 29-2: PIC18F47J53 FAMILY INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None
PIC18F47J53 FAMILY TABLE 29-2: PIC18F47J53 FAMILY INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move literal (12-bit) 2nd word to FSR(f) 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Sub
PIC18F47J53 FAMILY 29.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z k Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18F47J53 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC Syntax: ANDLW Operands: 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: (W) + (f) + (C) dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da Operands: 0 k 255 Operation: (W) .AND. k W Status Affected: N, Z Encoding: ffff ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W.
PIC18F47J53 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: (W) .AND. (f) dest Status Affected: N, Z Encoding: 0001 Description: Operands: -128 n 127 Operation: if Carry bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Encoding: 01da ffff ffff 1110 Description: The contents of W are ANDed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
PIC18F47J53 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 f 255 0b7 a [0,1] f, b {,a} Operation: 0 f Status Affected: None Encoding: 1001 Description: Operands: -128 n 127 Operation: if Negative bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F47J53 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Carry bit is ‘0’, (PC) + 2 + 2n PC Operation: if Negative bit is ‘0’, (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0011 nnnn nnnn If the Carry bit is ‘0’, then the program will branch. Encoding: 1110 Description: The 2’s complement number ‘2n’ is added to the PC.
PIC18F47J53 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Overflow bit is ‘0’, (PC) + 2 + 2n PC Operation: if Zero bit is ‘0’, (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0101 nnnn nnnn If the Overflow bit is ‘0’, then the program will branch. Encoding: 1110 Description: The 2’s complement number ‘2n’ is added to the PC.
PIC18F47J53 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA Syntax: BSF Operands: -1024 n 1023 Operands: Operation: (PC) + 2 + 2n PC Status Affected: None 0 f 255 0b7 a [0,1] Operation: 1 f Status Affected: None Encoding: n 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.
PIC18F47J53 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 Description: bbba ffff ffff If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
PIC18F47J53 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if Overflow bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Operation: (f) f Status Affected: None Encoding: 0111 Description: Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in data memory location ‘f’ is inverted.
PIC18F47J53 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} n Operands: -128 n 127 Operands: Operation: if Zero bit is ‘1’, (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: Status Affected: None (PC) + 4 TOS, k PC<20:1>; if s = 1 (W) WS, (STATUS) STATUSS, (BSR) BSRS Status Affected: None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
PIC18F47J53 FAMILY CLRF Clear f Syntax: CLRF Operands: 0 f 255 a [0,1] f {,a} Operation: 000h f, 1Z Status Affected: Z Encoding: 0110 Description: 101a ffff ffff Clears the contents of the specified register.
PIC18F47J53 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: f dest Status Affected: N, Z Encoding: 0001 Description: 11da ffff ffff The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W.
PIC18F47J53 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) –W), skip if (f) > (W) (unsigned comparison) Operation: (f) –W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of the W by
PIC18F47J53 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1], then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0> 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> > 9] or [C = 1], then (W<7:4>) + 6 W<7:4>; C =1; else (W<7:4>) W<7:4> Status Affected: 0000 Description: C Encoding: 0000 0000 0000 DAW adjusts the e
PIC18F47J53 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest, skip if result = 0 Operation: (f) – 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18F47J53 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range.
PIC18F47J53 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 f 255 d [0,1] a [0,1] f {,d {,a}} Increment f, Skip if Not 0 f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register ‘f’ are incremented.
PIC18F47J53 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF Operands: 0 k 255 Operands: Operation: (W) .OR. k W Status Affected: N, Z 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
PIC18F47J53 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
PIC18F47J53 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR Status Affected: None Operation: (fs) fd Status Affected: None Encoding: 1st word (source) 2nd word (destin.) Encoding: 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18F47J53 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Encoding: 0000 Description: 1110 kkkk kkkk The eight-bit literal ‘k’ is loaded into W.
PIC18F47J53 FAMILY MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0 f 255 a [0,1] Operation: (W) x (f) PRODH:PRODL Status Affected: None k Operands: 0 k 255 Operation: (W) x k PRODH:PRODL Status Affected: None Encoding: 0000 Description: 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair.
PIC18F47J53 FAMILY NEGF Negate f Syntax: NEGF Operands: 0 f 255 a [0,1] f {,a} Operation: (f) + 1 f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: 110a ffff If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.
PIC18F47J53 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18F47J53 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET n Operands: -1024 n 1023 Operands: None Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
PIC18F47J53 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged Operation: k W, (TOS) PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: Encoding: 0000 Description: 0000 0001 Words: 1 Cycles: 2 Q Cycle Activity: kkkk kkkk W is loaded wi
PIC18F47J53 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF Operands: s [0,1] Operands: Operation: (TOS) PC; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Description: Encoding: 0000 0001 001s 0011 Description: Return from subroutine.
PIC18F47J53 FAMILY RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF Syntax: RRCF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) dest<0> Operation: Status Affected: N, Z (f) dest, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left.
PIC18F47J53 FAMILY RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF Syntax: SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) dest, (f<0>) dest<7> Status Affected: N, Z Encoding: 0100 Description: f {,d {,a}} 00da Operation: FFh f Status Affected: None Encoding: ffff ffff 0110 Description: The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18F47J53 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) – (f) – (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 0101 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set.
PIC18F47J53 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF Operands: 0 k 255 Operands: Operation: k – (W) W Status Affected: N, OV, C, DC, Z 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18F47J53 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) – (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method).
PIC18F47J53 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR – No Change if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) – 1 TBLPTR if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT Before Instruction TABLAT TBLPTR MEMORY(00A356h) After Instruction TABLAT TBLPTR Example 2: Status Affec
PIC18F47J53 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) Holding Register; TBLPTR – No Change if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) – 1 TBLPTR if TBLWT+*, (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register Status Affected: Example 2: None Encoding: Description: Before Instruction TABLAT = 55h TBLPTR = 00A35
PIC18F47J53 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Status Affected: N, Z Operation: skip if f = 0 Status Affected: None Encoding: Encoding: 0110 Description: 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
PIC18F47J53 FAMILY XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 Description: f {,d {,a}} 10da ffff ffff Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
PIC18F47J53 FAMILY 29.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table 29-3. Detailed descriptions are provided in Section 29.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 29-1 (page 460) apply to both the standard and extended PIC18 instruction sets.
PIC18F47J53 FAMILY 29.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 k 63 f [ 0, 1, 2 ] Operands: 0 k 63 Operation: Operation: FSR(f) + k FSR(f) FSR2 + k FSR2, (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
PIC18F47J53 FAMILY CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU 0 zs 127 0 fd 4095 Operation: ((FSR2) + zs) fd Status Affected: None Status Affected: None Encoding: 0000 Description 0000 0001 0100 First, the return address (PC + 2) is pushed onto the return stack.
PIC18F47J53 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 zs 127 0 zd 127 Operands: 0k 255 Operation: k (FSR2), FSR2 – 1 FSR2 Status Affected: None Operation: ((FSR2) + zs) ((FSR2) + zd) Status Affected: None Encoding: 1st word (source) 2nd word (dest.
PIC18F47J53 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 k 63 Operands: 0 k 63 f [ 0, 1, 2 ] Operation: Operation: FSRf – k FSRf FSR2 – k FSR2, (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
PIC18F47J53 FAMILY 29.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing (Section 6.6.1 “Indexed Addressing with Literal Offset”).
PIC18F47J53 FAMILY ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 k 95 d [0,1] Operands: 0 f 95 0b7 Operation: (W) + ((FSR2) + k) dest Operation: 1 ((FSR2) + k) Status Affected: N, OV, C, DC, Z Status Affected: None ADDWF Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the valu
PIC18F47J53 FAMILY 29.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set for the PIC18F47J53 family. This includes the MPLAB C18 C Compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
PIC18F47J53 FAMILY 30.0 DEVELOPMENT SUPPORT 30.
PIC18F47J53 FAMILY 30.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 30.
PIC18F47J53 FAMILY 30.7 MPLAB SIM Software Simulator 30.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC18F47J53 FAMILY 30.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 30.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC18F47J53 FAMILY 31.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any digital only I/O pin or MCLR with respect to VSS (except VDD) ....................................
PIC18F47J53 FAMILY FIGURE 31-1: PIC18F47J53 FAMILY VDD FREQUENCY GRAPH (INDUSTRIAL) 4.0V 3.6V Voltage (VDD) 3.5V Valid Operating Range 3.0V 2.5V 2.35V(1) 2.15V 48 MHz 8 MHz 0 Frequency Note 1: When the USB module is enabled, VUSB should be provided 3.0V-3.6V while VDD must be 2.35V. When the USB module is not enabled, the wider limits shaded in grey apply. VUSB should be maintained VDD, but may optionally be high-impedance when the USB module is not in use.
PIC18F47J53 FAMILY 31.1 DC Characteristics: Supply Voltage PIC18F47J53 Family (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F47J53 Family Param No. Symbol Characteristic Min Typ Max Units — 3.6 V PIC18F4XJ53, PIC18F2XJ53 PIC18LF4XJ53, PIC18LF2XJ53 PIC18LF4XJ53, PIC18LF2XJ53 D001 VDD Supply Voltage 2.15 D001A VDD Supply Voltage 2.0 — 3.6 V D001B VDDCORE External Supply for Microcontroller Core 2.
PIC18F47J53 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F47J53 Family (Industrial) PIC18LF47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Param No.
PIC18F47J53 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F47J53 Family (Industrial) (Continued) PIC18LF47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Param No. Device Typ Max Units Conditions 5.5 14.2 A -40°C 5.8 14.
PIC18F47J53 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F47J53 Family (Industrial) (Continued) PIC18LF47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Param No. Device Typ Max Units Conditions PIC18LFXXJ53 1.45 3.0 mA -40°C 1.48 3.
PIC18F47J53 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F47J53 Family (Industrial) (Continued) PIC18LF47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Param No. Device Typ Max Units Conditions PIC18LFXXJ53 0.41 0.98 mA -40°C 0.44 0.
PIC18F47J53 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F47J53 Family (Industrial) (Continued) PIC18LF47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Param No. Device Typ Max Units Conditions PIC18LFXXJ53 0.61 1.25 mA -40°C 0.62 1.
PIC18F47J53 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F47J53 Family (Industrial) (Continued) PIC18LF47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Param No. Note 1: 2: 3: 4: Device Typ Max Units Conditions PIC18LFXXJ53 0.18 0.70 mA -40°C 0.18 0.
PIC18F47J53 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F47J53 Family (Industrial) (Continued) PIC18LF47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Param No. Device Typ Max Units 6.9 11.0 mA -40°C 6.7 11.0 mA +25°C 6.4 10.0 mA +85°C 7.0 15.
PIC18F47J53 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F47J53 Family (Industrial) (Continued) PIC18LF47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Param No.
PIC18F47J53 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F47J53 Family (Industrial) (Continued) PIC18LF47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Param No.
PIC18F47J53 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F47J53 Family (Industrial) (Continued) PIC18LF47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Param No.
PIC18F47J53 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F47J53 Family (Industrial) (Continued) PIC18LF47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F47J53 Family Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Param No.
PIC18F47J53 FAMILY 31.3 DC Characteristics:PIC18F47J53 Family (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions VSS 0.15 VDD V VDD < 3.3V 3.3V < VDD <3.6V Input Low Voltage All I/O ports: with TTL Buffer(4) D030 (4) D030A with TTL Buffer VSS 0.8 V D031 with Schmitt Trigger Buffer VSS 0.2 VDD V — 0.
PIC18F47J53 FAMILY 31.3 DC Characteristics:PIC18F47J53 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial DC CHARACTERISTICS Param Symbol No. VOL D080 Characteristic Min Max Units Conditions PORTA (except RA6), PORTD(3), PORTE(3) — 0.4 V IOL = 4 mA, VDD = 3.3V, -40C to +85C PORTB, PORTC, RA6 — 0.4 V IOL = 8.5 mA, VDD = 3.
PIC18F47J53 FAMILY TABLE 31-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial DC CHARACTERISTICS Param No. Sym Characteristic Min Typ† Max Units Conditions Program Flash Memory D130 EP Cell Endurance 10K — — D131 VPR VDDcore for Read VMIN — 2.75 V D132B VPEW VDDCORE for Self-Timed Erase or Write 2.25 — 2.75 V D133A TIW Self-Timed Write Cycle Time — 2.
PIC18F47J53 FAMILY TABLE 31-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param No. Sym Note 1: Characteristics Min Typ Max VRGOUT Regulator Output Voltage 2.35 2.5 CEFC 5.4 10 External Filter Capacitor Value(1) Comments 2.7 V Regulator enabled, VDD = 3.0V 18 F ESR < 3 recommended ESR < 5 required CEFC applies for PIC18F devices in the family.
PIC18F47J53 FAMILY TABLE 31-7: USB MODULE SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param No. D313 Sym Characteristics Min Typ Max Units Comments Voltage on VUSB pin must be in this range for proper USB operation VUSB USB Voltage 3.0 — 3.6 V D314 IIL Input Leakage on D+ or D- — — +0.2 A VSS < VPIN < VUSB D315 VILUSB Input Low Voltage for USB Buffer — — 0.8 V For VUSB range D316 VIHUSB Input High Voltage for USB Buffer 2.
PIC18F47J53 FAMILY FIGURE 31-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS For VDIRMAG = 1: VDD VHLVD (HLVDIF set by hardware) (HLVDIF can be cleared in software) VHLVD For VDIRMAG = 0: VDD HLVDIF TABLE 31-8: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Param Symbol No. D420 Characteristic Min Typ Max Units HLVD Voltage on VDD HLVDL<3:0> = 1000 Transition High-to-Low HLVDL<3:0> = 1001 2.
PIC18F47J53 FAMILY 31.4 31.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC18F47J53 FAMILY 31.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 31-9 apply to all timing specifications unless otherwise noted. Figure 31-4 specifies the load conditions for the timing specifications. TABLE 31-9: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC AC CHARACTERISTICS FIGURE 31-4: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Operating voltage VDD range as described in Section 31.1 and Section 31.3.
PIC18F47J53 FAMILY TABLE 31-10: EXTERNAL CLOCK TIMING REQUIREMENTS Param. No. 1A Symbol FOSC Characteristic Min Max Units External CLKI Frequency(1) DC 48 MHz DC 48 4 16 4 16(4) 20.8 — 20.8 — 62.5 250 (1) Oscillator Frequency 1 TOSC External CLKI Period Oscillator Period (1) (1) 62.
PIC18F47J53 FAMILY FIGURE 31-6: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 19 14 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 31-4 for load conditions. TABLE 31-13: CLKO AND I/O TIMING REQUIREMENTS Param No.
PIC18F47J53 FAMILY FIGURE 31-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR PWRT Time-out 33 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 31-4 for load conditions. TABLE 31-14: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No. Characteristic Min Typ Max Units 2 — — s 2.67 4.0 5.
PIC18F47J53 FAMILY TABLE 31-15: LOW-POWER WAKE-UP TIME Param. Symbol No. Characteristic Min Typ Max Units Conditions — 500 — s REGSLP = 1 W1 WDS W2 WSLEEP Sleep — 35 — s REGSLP = 1, PLLEN = 0 FOSC = 8 MHz INTOSC W3 WDOZE1 Sleep — 12 — s REGSLP = 0, PLLEN = 0, FOSC = 8 MHz INTOSC W4 WDOZE2 Sleep — 1.
PIC18F47J53 FAMILY TABLE 31-16: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Symbol Characteristic 40 TT0H T0CKI High Pulse Width 41 TT0L T0CKI Low Pulse Width 42 TT0P T0CKI Period No prescaler Min Max Units 0.5 TCY + 20 — ns With prescaler No prescaler 10 — ns 0.
PIC18F47J53 FAMILY TABLE 31-17: ENHANCED CAPTURE/COMPARE/PWM REQUIREMENTS Param Symbol No. Characteristic 50 TCCL ECCPx Input Low Time 51 TCCH ECCPx Input High Time 52 TCCP ECCPx Input Period 3 TCY + 40 N 53 TCCR 54 TCCF No prescaler Min Max Units 0.5 TCY + 20 — ns With prescaler 10 — ns 0.
PIC18F47J53 FAMILY TABLE 31-18: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units PM1 PMALL/PMALH Pulse Width — 0.5 TCY — ns PM2 Address Out Valid to PMALL/PMALH Invalid (address setup time) — 0.75 TCY — ns PM3 PMALL/PMALH Invalid to Address Out Invalid (address hold time) — 0.25 TCY — ns PM5 PMRD Pulse Width — 0.
PIC18F47J53 FAMILY FIGURE 31-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SCKx (CKP = 0) 78 79 79 78 SCKx (CKP = 1) bit 6 - - - - - - 1 MSb SDOx LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 31-4 for load conditions. TABLE 31-20: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No. 73 Symbol TDIV2SCH, TDIV2SCL Characteristic Min Setup Time of SDIx Data Input to SCKx Edge 35 — ns VDD = 3.3V, VDDCORE = 2.5V 100 — ns VDD = 2.15V, VDDCORE = 2.
PIC18F47J53 FAMILY FIGURE 31-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) 81 SCKx (CKP = 0) 79 73 SCKx (CKP = 1) 78 MSb SDOx bit 6 - - - - - - 1 LSb bit 6 - - - - 1 LSb In 75, 76 SDIx MSb In 74 Note: Refer to Figure 31-4 for load conditions. TABLE 31-21: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No.
PIC18F47J53 FAMILY FIGURE 31-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SSx 70 SCKx (CKP = 0) 83 71 72 SCKx (CKP = 1) 80 MSb SDOx LSb bit 6 - - - - - - 1 75, 76 MSb In SDIx SDI 77 bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 31-4 for load conditions. TABLE 31-22: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No.
PIC18F47J53 FAMILY FIGURE 31-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SSx SCKx (CKP = 0) 70 83 71 72 73 SCKx (CKP = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 SDI SDIx 77 bit 6 - - - - 1 MSb In LSb In 74 Note: Refer to Figure 31-4 for load conditions. TABLE 31-23: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No. Symbol Characteristic Min Max Units 3 TCY — ns Continuous Single byte 3 TCY 1.
PIC18F47J53 FAMILY I2C™ BUS START/STOP BITS TIMING FIGURE 31-16: SCLx 91 93 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 31-4 for load conditions. TABLE 31-24: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC18F47J53 FAMILY TABLE 31-25: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH 101 TLOW 102 TR Characteristic Clock High Time Clock Low Time Min Max Units 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s MSSP modules 1.5 TCY — 100 kHz mode 4.7 — s s 400 kHz mode 1.3 — MSSP modules 1.5 TCY — — 1000 ns 20 + 0.
PIC18F47J53 FAMILY FIGURE 31-18: MSSPx I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCLx 93 91 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 31-4 for load conditions. TABLE 31-26: MSSPx I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
PIC18F47J53 FAMILY TABLE 31-27: MSSPx I2C™ BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Min Max Units Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — s 400 kHz mode 2(TOSC)(BRG + 1) — s 1 MHz mode(1) 2(TOSC)(BRG + 1) — s Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — s 400 kHz mode 2(TOSC)(BRG + 1) — s (1) 2(TOSC)(BRG + 1) — s — 1000 ns 20 + 0.
PIC18F47J53 FAMILY FIGURE 31-20: EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx pin 121 121 RXx/DTx pin 120 Note: 122 Refer to Figure 31-4 for load conditions. TABLE 31-28: EUSARTx SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC18F47J53 FAMILY TABLE 31-30: A/D CONVERTER CHARACTERISTICS: PIC18F47J53 FAMILY (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units — — 12 bit Conditions VREF 3.0V A01 NR Resolution A03 EIL Integral Linearity Error — <±1 ±2 LSb VREF 3.0V A04 EDL Differential Linearity Error — <±1 1.5 LSb VREF 3.0V A06 EOFF Offset Error — <±1 5 LSb VREF 3.0V A07 EGN Gain Error — — <±3.5 LSb VREF 3.0V A10 Guaranteed(1) — VSS VAIN VREF 2.
PIC18F47J53 FAMILY TABLE 31-31: 10-BIT A/D CONVERSION REQUIREMENTS Param Symbol No. Characteristic Min Max Units 130 TAD A/D Clock Period 0.7 25.0(1) s 131 TCNV Conversion Time (not including acquisition time)(2) 11 12 TAD 132 TACQ Acquisition Time(3) 1.4 — s 135 TSWC Switching Time from Convert Sample — (Note 4) 137 TDIS Discharge Time 0.2 — Note 1: 2: 3: Conditions TOSC based, VREF 3.
PIC18F47J53 FAMILY FIGURE 31-23: USB SIGNAL TIMING USB Data Differential Lines 90% VCRS 10% TLF, TFF TLR, TFR TABLE 31-33: USB LOW-SPEED TIMING REQUIREMENTS Param No. Symbol Characteristic Min Typ Max Units Conditions TLR Transition Rise Time 75 — 300 ns CL = 200 to 600 pF TLF Transition Fall Time 75 — 300 ns CL = 200 to 600 pF TLRFM Rise/Fall Time Matching 80 — 125 % Min Typ Max Units 4 — 20 ns CL = 50 pF CL = 50 pF TABLE 31-34: USB FULL-SPEED REQUIREMENTS Param No.
PIC18F47J53 FAMILY NOTES: DS39964B-page 554 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 32.0 PACKAGING INFORMATION 32.1 Package Marking Information 28-Lead QFN Example XXXXXXXX XXXXXXXX YYWWNNN 18F27J53 /ML e3 0910017 28-Lead SOIC (.300”) Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN PIC18F27J53/SO e3 PIC18F26J50/SO 0910017 Example 28-Lead SPDIP PIC18F27J53 -I/SP e3 0910017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example 28-Lead SSOP PICXXFXXXX -I/SS 0610017 XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC18F47J53 FAMILY Package Marking Information (Continued) 44-Lead QFN Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 18F47J53 -I/ML e3 0910017 44-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS39964B-page 556 18F47J53 -I/PT e3 0910017 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 32.2 Package Details The following sections give the technical details of the packages. ! " # $ %&'' ( ) ) $ * 2 % & % ! % * %% 133))) & &3 " ) * D ' % * $ % % " % D2 EXPOSED PAD e E b E2 2 2 1 1 K N N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 4 % & 5 & % 6!&( $ 55 , , 6 6 67 8 9 % :.
PIC18F47J53 FAMILY ! " # $ %&'' ( ) ) $ * 2 % & % ! % * %% 133))) & &3 DS39964B-page 558 " ) * ' % * Preliminary $ % % " % 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY * + , ) +, - .&'% !+,/(" 2 % & % ! % * %% 133))) & &3 " ) * ' % * $ % % " % D N E E1 NOTE 1 1 2 3 e b h α h c φ A2 A L A1 β L1 4 % & 5 & % 6!&( $ 55 , , 6 6 / 0 7 ; % * % " $$ ? 7 < "% " " * 8 9 % " " * 67 > > . > > > + , < "% 7 5 % :.
PIC18F47J53 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39964B-page 560 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY + )) * 0 /) ) + 1%% !+ 0/ " 2 % & % ! % * %% 133))) & &3 " ) * ' % * $ % % " % N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 4 % & 5 & % 6!&( $ 60;, 6 6 67 8 9 % / 0 % % > > +. . . > > ! " % ! " < "% , + ++.
PIC18F47J53 FAMILY * +$2 ) + , ) ++ '&1% !++, " 2 % & % ! % * %% 133))) & &3 " ) * ' % * $ % % " % D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 4 % & 5 & % 6!&( $ 55 , , 6 6 67 8 9 % :. / 0 7 ; % > > :. . 9. % " $$ . > > 7 < "% , 9 9 " " * " " * * , . .
PIC18F47J53 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 33 * ! " 2 % & % ! % * %% 133))) & &3 " ) * ' D % * $ % % " % D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 K L TOP VIEW BOTTOM VIEW A A3 A1 4 % & 5 & % 6!&( $ 55 , , 6 67 6 8 % :. / 0 7 ; % 9 % " $$ .
PIC18F47J53 FAMILY 33 * ! " 2 % & % ! % * %% 133))) & &3 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY 33 * 4$ ) 5 4 6% 6% 6 &%% !4 " 2 % & % ! % * %% 133))) & &3 " ) * ' % * $ % % " % D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 4 % & 5 & % 6!&( $ 5 5 " 55 , , 6 67 6 8 " % 9 / 0 7 ; % > > . . . > . 2 % 5 % 5 . : .
PIC18F47J53 FAMILY 33 * 4$ ) 5 4 6% 6% 6 &%% !4 " 2 % & % ! % * %% 133))) & &3 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY NOTES: DS39964B-page 568 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY APPENDIX A: REVISION HISTORY APPENDIX B: Revision A (December 2009) Original data sheet for PIC18F47J53 family devices. Revision B (June 2010) Updates typical and maximum DC current specifications in Section 31.2 “DC Characteristics: Power-Down and Supply Current PIC18F47J53 Family (Industrial)”. MIGRATION FROM PIC18F46J50 TO PIC18F47J53 Code for the devices in the PIC18F46J50 family can be migrated to the PIC18F47J53 without many changes.
PIC18F47J53 FAMILY NOTES: DS39964B-page 570 Preliminary 2010 Microchip Technology Inc.
PIC18F47J53 FAMILY INDEX Symbols ............................................................................................ 71 <$end ................................................................................ 101 <$start ................................................................................. 94 A A/D .................................................................................... 367 A/D Converter Interrupt, Configuring ........................ 373 Acquisition Requirements ............
PIC18F47J53 FAMILY USTAT FIFO ............................................................. 385 Watchdog Timer........................................................ 451 BN ..................................................................................... 468 BNC................................................................................... 469 BNN................................................................................... 469 BNOV .............................................................
PIC18F47J53 FAMILY Bits and Device IDs................................................... 442 Mapping Flash Configuration Words......................... 442 Core Features Easy Migration ............................................................ 12 Expanded Memory...................................................... 11 Extended Instruction Set............................................. 12 nanoWatt Technology ................................................. 11 Oscillator Options and Features ...........
PIC18F47J53 FAMILY Associated Registers, Reception ...................... 366 Associated Registers, Transmission................. 365 Reception.......................................................... 366 Transmission..................................................... 365 Extended Instruction Set ADDFSR ................................................................... 502 ADDULNK ................................................................. 502 CALLW.................................................
PIC18F47J53 FAMILY BNN .......................................................................... 469 BNOV........................................................................ 470 BNZ........................................................................... 470 BOV .......................................................................... 473 BRA........................................................................... 471 BSF ...........................................................................
PIC18F47J53 FAMILY Multiple Sleep Commands .......................................... 48 Run Modes.................................................................. 49 PRI_RUN ............................................................ 49 RC_RUN ............................................................. 50 SEC_RUN........................................................... 49 Sleep Mode ................................................................. 51 Summary (table) ..................................
PIC18F47J53 FAMILY VDDCORE/VCAP ...................................................... 29, 21 VSS1...................................................................... 21, 29 VSS2...................................................................... 21, 29 VUSB ...................................................................... 21, 29 Pinout I/O Descriptions PIC18F2XJ53 (28-Pin)................................................ 16 PIC18F4XJ53 (44-Pin)................................................
PIC18F47J53 FAMILY BDnSTAT (Buffer Descriptor n Status, CPU Mode) ....................................................... 390 BDnSTAT (Buffer Descriptor n Status, SIE Mode) ......................................................... 391 BDnSTAT (SIE Mode)............................................... 391 Buffer Descriptors, Summary .................................... 393 CCPTMRS0 (ECCP1/2/3 Select 0) ........................... 271 CCPxCON (CCPx CCP4-10 Control)........................
PIC18F47J53 FAMILY SSPxCON1 (MSSPx Control 1, I2C Mode)............... 312 SSPxCON1 (MSSPx Control 1, SPI Mode) .............. 294 SSPxCON2 (MSSPx Control 2, I2C Master Mode).................................................... 313 SSPxCON2 (MSSPx Control 2, I2C Slave Mode)...................................................... 314 SSPxMSK (I2C Slave Address Mask)....................... 314 SSPxSTAT (MSSPx Status, I2C Mode) .................... 311 SSPxSTAT (MSSPx Status, SPI Mode) ...................
PIC18F47J53 FAMILY Serial Data In ............................................................ 292 Serial Data Out ......................................................... 292 Slave Mode ............................................................... 298 Slave Select .............................................................. 292 Slave Select Synchronization ................................... 298 SPI Clock .................................................................. 297 SSPxBUF Register .........
PIC18F47J53 FAMILY I2C Slave Mode (10-Bit Reception, SEN = 0, ADMSK = 01001) ...................................................... 322 I2C Slave Mode (10-Bit Reception, SEN = 0) ........... 323 I2C Slave Mode (10-Bit Reception, SEN = 1) ........... 328 I2C Slave Mode (10-Bit Transmission)...................... 324 I2C Slave Mode (7-Bit Reception, SEN = 0, ADMSK = 01011).............................................. 320 I2C Slave Mode (7-Bit Reception, SEN = 0) .............
PIC18F47J53 FAMILY Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements............................................ 537, 538 Timer0 and Timer1 External Clock Requirements............................................................ 539 USB Full-Speed Requirements ................................. 553 USB Low-Speed Requirements ................................ 553 TSTFSZ.............................................................................
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PIC18F47J53 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC18F47J53 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Device Temperature Range = = -40C to +85C -40C to +125C = = = = = a) b) PIC18F26J53, PIC18F27J53, PIC18F46J53 and PIC18F47J53 VDD range 2.15V to 3.6V PIC18LF26J53, PIC18LF27J53, PIC18LF46J53 and PIC18LF47J53 VDD range 2.0V to 3.
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