Datasheet

 2010 Microchip Technology Inc. Preliminary DS39964B-page 551
PIC18F47J53 FAMILY
TABLE 31-30: A/D CONVERTER CHARACTERISTICS: PIC18F47J53 FAMILY (INDUSTRIAL)
FIGURE 31-22: A/D CONVERSION TIMING
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
A01 N
R Resolution — — 12 bit VREF  3.0V
A03 EIL Integral Linearity Error — <±1 ±2 LSb VREF  3.0V
A04 E
DL Differential Linearity Error — <±1 1.5 LSb VREF  3.0V
A06 EOFF Offset Error — <±1 5 LSb VREF  3.0V
A07 EGN Gain Error — — <±3.5 LSb VREF  3.0V
A10 Monotonicity Guaranteed
(1)
—VSS  VAIN  VREF
A20 VREF Reference Voltage Range
(V
REFH – VREFL)
2.0
3
—
—
—
—
V
V
V
DD  3.0V
V
DD  3.0V
A21 V
REFH Reference Voltage High
For 10-bit resolution
For 12-bit resolution
V
REFL
VSS + 3V
—
—
V
DD + 0.3V
V
DD + 0.3V
V
V
A22 V
REFL Reference Voltage Low
For 10-bit resolution
For 12-bit resolution
V
SS – 0.3V
V
SS – 0.3V
—
—
V
REFH
VDD - 3V
V
V
A25 V
AIN Analog Input Voltage VREFL —VREFH V
A30 ZAIN Recommended Impedance of
Analog Voltage Source
For 10-bit resolution
For 12-bit resolution
—
—
—
—
10
2.5
k
k
A50 I
REF VREF Input Current
(2)
—
—
—
—
5
150
A
A
During VAIN acquisition.
During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from RA3/AN3/VREF+/C1INB pin or VDD, whichever is selected as the VREFH source.
V
REFL current is from RA2/AN2/VREF-/CVREF/C2INB pin or VSS, whichever is selected as the VREFL source.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
987 21 0
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . .
. . .
TCY (Note 1)