Datasheet

PIC18F47J53 FAMILY
DS39964B-page 264 Preliminary  2010 Microchip Technology Inc.
FIGURE 18-2: COMPARE MODE OPERATION BLOCK DIAGRAM
CCPR5H CCPR5L
TMR1H TMR1L
Comparator
QS
R
Output
Logic
Special Event Trigger
Set CCP5IF
CCP5 Pin
TRIS
CCP5CON<3:0>
Output Enable
TMR5H TMR5L
1
0
Compare
4
(Timer1/5 Reset)
Match
Note: This block diagram uses CCP4 and CCP5 and their appropriate timers as an example. For details on all of
the CCP modules and their timer assignments, see Table 18-2 and Table 18-3.
TMR1H TMR1L
TMR5H TMR5L
CCPR4H CCPR4L
Comparator
C4TSEL1
Set CCP4IF
1
0
QS
R
Output
Logic
Special Event Trigger
CCP4 Pin
TRIS
CCP4CON<3:0>
Output Enable
4
(Timer1/Timer3 Reset, A/D Trigger)
Compare
Match
C5TSEL0
C4TSEL0