Datasheet

PIC18F47J53 FAMILY
DS39964B-page 292 Preliminary  2010 Microchip Technology Inc.
20.2 Control Registers
Each MSSP module has three associated control
registers. These include a status register (SSPxSTAT)
and two control registers (SSPxCON1 and SSPxCON2).
The use of these registers and their individual Configura-
tion bits differs significantly depending on whether the
MSSP module is operated in SPI or I
2
C mode.
Additional details are provided under the individual
sections.
20.3 SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported.
When MSSP2 is used in SPI mode, it can optionally be
configured to work with the SPI DMA submodule
described in Section 20.4 “SPI DMA Module”.
To accomplish communication, typically three pins are
used:
• Serial Data Out (SDOx) –
RC7/CCP10/RX1/DT1/SDO1/RP18 or
SDO2/Remappable
• Serial Data In (SDIx) –
RB5/CCP5/KBI1/SDI1/SDA1/RP8 or
SDI2/Remappable
• Serial Clock (SCKx) –
RB4/CCP4/KBI0/SCK1/SCL1/RP7 or
SCK2/Remappable
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SSx
) – RA5/AN4/C1INC/SS1/
HLVDIN/RCV/RP2 or SS2
/Remappable
Figure 20-1 depicts the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 20-1: MSSPx BLOCK DIAGRAM
(SPI MODE)
Note: In devices with more than one MSSP
module, it is very important to pay close
attention to the SSPxCON register names.
SSP1CON1 and SSP1CON2 control
different operational aspects of the same
module, while SSP1CON1 and
SSP2CON1 control the same features for
two different modules.
( )
Read Write
Internal
Data Bus
SSPxSR reg
SSPM<3:0>
bit 0
Shift
Clock
SSx
Control
Enable
Edge
Select
Clock Select
TMR2 Output
T
OSC
Prescaler
4, 8, 16, 64
2
Edge
Select
2
4
Data to TXx/RXx in SSPxSR
TRIS bit
2
SMP:CKE
SDOx
SSPxBUF reg
SDIx
SSx
SCKx
Note: Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.