Datasheet

 2010 Microchip Technology Inc. Preliminary DS39964B-page 451
PIC18F47J53 FAMILY
28.2 Watchdog Timer (WDT)
PIC18F47J53 family devices have both a conventional
WDT circuit and a dedicated, Deep Sleep capable
Watchdog Timer. When enabled, the conventional
WDT operates in normal Run, Idle and Sleep modes.
This data sheet section describes the conventional
WDT circuit.
The dedicated, Deep Sleep capable WDT can only be
enabled in Deep Sleep mode. This timer is described in
Section 4.6.4 “Deep Sleep Watchdog Timer
(DSWDT)”.
The conventional WDT is driven by the INTRC oscilla-
tor. When the WDT is enabled, the clock source is also
enabled. The nominal WDT period is 4 ms and has the
same stability as the INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from about 4 ms to 135 seconds (2.25 minutes
depending on voltage, temperature and WDT
postscaler). The WDT and postscaler are cleared
whenever a SLEEP or CLRWDT instruction is executed,
or a clock failure (primary or Timer1 oscillator) has
occurred.
28.2.1 CONTROL REGISTER
The WDTCON register (Register 28-11) is a readable
and writable register. The SWDTEN bit enables or dis-
ables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
LVDSTAT is a read-only status bit that is continuously
updated and provides information about the current
level of V
DDCORE. This bit is only valid when the on-chip
voltage regulator is enabled.
FIGURE 28-1: WDT BLOCK DIAGRAM
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
INTRC Oscillator
WDT
Wake-up from
Reset
WDT
WDT Counter
Programmable Postscaler
1:1 to 1:32,768
Enable WDT
WDTPS<3:0>
SWDTEN
CLRWDT
4
Power-Managed
Reset
All Device Resets
Sleep
INTRC Control
128
Modes