Datasheet

PIC18F47J53 FAMILY
DS39964B-page 134 Preliminary  2010 Microchip Technology Inc.
REGISTER 9-12: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 (ACCESS F8Eh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CCP10IE CCP9IE CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 CCP10IE:CCP4IE: CCP<10:4> Interrupt Enable bits
1 = Enabled
0 = Disabled
bit 0 CCP3IE: ECCP3 Interrupt Enable bit
1 = Enabled
0 = Disabled
REGISTER 9-13: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5 (ACCESS F91h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CM3IE TMR8IE TMR6IE TMR5IE TMR5GIE TMR1GIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 CM3IE: Comparator3 Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 TMR8IE: TMR8 to PR8 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 TMR5IE: TMR5 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 TMR5GIE: TMR5 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0 TMR1GIE: TMR1 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled