Datasheet

 2010 Microchip Technology Inc. Preliminary DS39964B-page 579
PIC18F47J53 FAMILY
SSPxCON1 (MSSPx Control 1, I
2
C Mode)............... 312
SSPxCON1 (MSSPx Control 1, SPI Mode) .............. 294
SSPxCON2 (MSSPx Control 2, I
2
C
Master Mode).................................................... 313
SSPxCON2 (MSSPx Control 2, I
2
C
Slave Mode)...................................................... 314
SSPxMSK (I
2
C Slave Address Mask)....................... 314
SSPxSTAT (MSSPx Status, I
2
C Mode).................... 311
SSPxSTAT (MSSPx Status, SPI Mode) ................... 293
STATUS.................................................................... 102
STKPTR (Stack Pointer) ............................................. 84
T0CON (Timer0 Control)........................................... 205
T1CON (Timer1 Control)........................................... 209
T1GCON (Timer1 Gate Control)............................... 210
T2CON (Timer2 Control)........................................... 219
TxCON (Timer3/5 Control)........................................ 222
TxCON (Timer4/6/8 Control)..................................... 234
TxGCON (Timer3/5 Gate Control) ............................ 223
TXSTAx (Transmit Status and Control) .................... 346
UADDR ..................................................................... 387
UCFG (USB Configuration)....................................... 383
UCON (USB Control)................................................ 381
UEIE (USB Error Interrupt Enable) ........................... 399
UEIR (USB Error Interrupt Status)............................ 398
UEPn (USB Endpoint n Control) ............................... 386
UFRMH:UFRML........................................................ 387
UIE (USB Interrupt Enable)....................................... 397
UIR (USB Interrupt Status) ....................................... 395
USTAT (USB Status) ................................................ 385
WDTCON (Watchdog Timer Control) ....................... 452
WKDY (Weekday Value)........................................... 244
YEAR (Year Value)................................................... 243
RESET .............................................................................. 489
Reset................................................................................... 65
Brown-out Reset ......................................................... 67
Brown-out Reset (BOR).............................................. 65
Configuration Mismatch (CM) ..................................... 65
Configuration Mismatch Reset.................................... 68
Deep Sleep ................................................................. 65
Fast Register Stack..................................................... 85
MCLR
.......................................................................... 67
MCLR
Reset, During Power-Managed Modes............ 65
MCLR
Reset, Normal Operation ................................. 65
Power-on Reset .......................................................... 67
Power-on Reset (POR) ............................................... 65
Power-up Timer .......................................................... 68
RESET Instruction ...................................................... 65
Stack Full Reset.......................................................... 65
Stack Underflow Reset ............................................... 65
State of Registers ....................................................... 70
Watchdog Timer (WDT) Reset.................................... 65
Resets............................................................................... 441
Brown-out Reset (BOR)............................................ 441
Oscillator Start-up Timer (OST) ................................ 441
Power-on Reset (POR) ............................................. 441
Power-up Timer (PWRT) .......................................... 441
RETFIE ............................................................................. 490
RETLW ............................................................................. 490
RETURN ........................................................................... 491
Return Address Stack ......................................................... 83
Associated Registers .................................................. 83
Revision History ................................................................ 569
RLCF................................................................................. 491
RLNCF .............................................................................. 492
RRCF ................................................................................ 492
RRNCF ............................................................................. 493
RTCC
Alarm ........................................................................ 253
Configuring ....................................................... 253
Interrupt ............................................................ 254
Mask Settings ................................................... 253
Alarm Value Register Mappings (ALRMVAL)........... 246
Control Registers...................................................... 239
Control/Value Register Maps.................................... 255
Low-Power Modes.................................................... 254
Operation
Calibration ........................................................ 252
Clock Source .................................................... 250
Digit Carry Rules .............................................. 250
General Functionality........................................ 251
Leap Year......................................................... 251
Register Mapping ............................................. 251
ALRMVAL................................................. 252
RTCVAL ................................................... 252
Safety Window for Register Reads
and Writes ................................................ 251
Write Lock......................................................... 251
Peripheral Module Disable (PMD) Register.............. 255
Register Interface ..................................................... 249
Reset ........................................................................ 254
Device .............................................................. 254
Power-on Reset (POR)..................................... 254
Value Register Mappings (RTCVAL)........................ 243
RTCEN Bit Write............................................................... 249
S
SCKx ................................................................................ 292
SDIx .................................................................................. 292
SDOx ................................................................................ 292
SEC_IDLE Mode ................................................................ 52
SEC_RUN Mode................................................................. 49
Serial Clock, SCKx ........................................................... 292
Serial Data In (SDIx)......................................................... 292
Serial Data Out (SDOx) .................................................... 292
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 493
Shoot-Through Current..................................................... 285
Slave Select (SSx
)............................................................ 292
SLEEP .............................................................................. 494
Software Simulator (MPLAB SIM) .................................... 511
Special Event Trigger. See Compare (CCP Module).
Special Event Trigger. See Compare (ECCP Mode).
Special Features of the CPU ............................................ 441
SPI Mode (MSSP) ............................................................ 292
Associated Registers................................................ 301
Bus Mode Compatibility............................................ 300
Clock Speed, Interactions......................................... 300
DMA Module............................................................. 302
I/O Pin Considerations...................................... 302
Idle, Sleep Considerations................................ 302
RAM to RAM Copy ........................................... 302
Registers .......................................................... 302
Effects of a Reset ..................................................... 300
Enabling SPI I/O ....................................................... 296
Master Mode............................................................. 297
Master/Slave Connection ......................................... 296
Operation.................................................................. 295
Open-Drain Output Option................................ 295
Operation in Power-Managed Modes....................... 300
Registers .................................................................. 293
Serial Clock .............................................................. 292