Datasheet

PIC18F47J53 FAMILY
DS39964B-page 70 Preliminary  2010 Microchip Technology Inc.
5.7 Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register (CM
, RI,
TO
, PD, POR and BOR) are set or cleared differently in
different Reset situations, as indicated in Table 5-1.
These bits are used in software to determine the nature
of the Reset.
Table 5-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
POR and BOR, MCLR
and WDT Resets and WDT
wake-ups.
TABLE 5-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition
Program
Counter
(1)
RCON Register STKPTR Register
CM
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 111100 0 0
RESET instruction 0000h u0uuuu u u
Brown-out Reset 0000h 1111u0 u u
Configuration Mismatch Reset 0000h 0uuuuu u u
MCLR
Reset during
power-managed Run modes
0000h uu1uuu u u
MCLR
Reset during
power-managed Idle modes and
Sleep mode
0000h uu10uu u u
MCLR
Reset during full-power
execution
0000h uuuuuu u u
Stack Full Reset (STVREN = 1) 0000h uuuuuu 1 u
Stack Underflow Reset
(STVREN = 1)
0000h uuuuuu u 1
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h uuuuuu u 1
WDT time-out during full-power
or power-managed Run modes
0000h uu0uuu u u
WDT time-out during
power-managed Idle or Sleep
modes
PC + 2 uu00uu u u
Interrupt exit from
power-managed modes
PC + 2 uuu0uu u u
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).