Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller DIL-16

November 2007 1/124

Rev 6

ST7LITE0xY0, ST7LITESxY0

8-bit microcontroller with single voltage

Flash memory, data EEPROM, ADC, timers, SPI

■ Memories

– 1K or 1.5 Kbytes single voltage Flash Pro-

gram memory with read-out protection, In-Cir-

cuit and In-Application Programming (ICP and

IAP). 10 K write/erase cycles guaranteed,

data retention: 20 years at 55 °C.

– 128 bytes RAM.

– 128 bytes data EEPROM with read-out pro-

tection. 300K write/erase cycles guaranteed,

data retention: 20 years at 55 °C.

■ Clock, Reset and Supply Management

– 3-level low voltage supervisor (LVD) and aux-

iliary voltage detector (AVD) for safe power-

on/off procedures

– Clock sources: internal 1MHz RC 1% oscilla-

tor or external clock

– PLL x4 or x8 for 4 or 8 MHz internal clock

– Four Power Saving Modes: Halt, Active-Halt,

Wait and Slow

■ Interrupt Management

– 10 interrupt vectors plus TRAP and RESET

– 4 external interrupt lines (on 4 vectors)

■ I/O Ports

– 13 multifunctional bidirectional I/O lines

– 9 alternate function lines

– 6 high sink outputs

■ 2 Timers

– One 8-bit Lite Timer (LT) with prescaler in-

cluding: watchdog, 1 realtime base and 1 in-

put capture.

– One 12-bit Auto-reload Timer (AT) with output

compare function and PWM

■ 1 Communication Interface

– SPI synchronous serial interface

■ A/D Converter

– 8-bit resolution for 0 to V

– Fixed gain Op-amp for 11-bit resolution in 0 to

250 mV range (@ 5V V

)

– 5 input channels

■ Instruction Set

– 8-bit data manipulation

– 63 basic instructions with illegal opcode de-

tection

– 17 main addressing modes

– 8 x 8 unsigned multiply instruction

■ Development Tools

– Full hardware/software development package

Device Summary

DIP16

SO16

150”

QFN20

Features

ST7LITESxY0 (ST7SUPERLITE) ST7LITE0xY0

ST7LITES2Y0 ST7LITES5Y0 ST7LITE02Y0 ST7LITE05Y0 ST7LITE09Y0

Program memory - bytes 1K 1K 1.5K 1.5K 1.5K

RAM (stack) - bytes 128 (64) 128 (64) 128 (64) 128 (64) 128 (64)

Data EEPROM - bytes----128

Peripherals

LT Timer w/ Wdg,

AT Timer w/ 1 PWM,

SPI

LT Timer w/ Wdg,

AT Timer w/ 1 PWM,

SPI, 8-bit ADC

LT Timer w/ Wdg,

AT Timer w/ 1 PWM,

SPI

LT Timer w/ Wdg,

AT Timer w/ 1 PWM, SPI,

8-bit ADC w/ Op-Amp

Operating Supply 2.4V to 5.5V

CPU Frequency 1MHz RC 1% + PLLx4/8MHz

Operating Temperature -40°C to +85°C

Packages SO16 150”, DIP16, QFN20

Summary of content (124 pages)

PAGE 1
ST7LITE0xY0, ST7LITESxY0 8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI ■ ■ ■ ■ ■ Memories – 1K or 1.5 Kbytes single voltage Flash Program memory with read-out protection, In-Circuit and In-Application Programming (ICP and IAP). 10 K write/erase cycles guaranteed, data retention: 20 years at 55 °C. – 128 bytes RAM. – 128 bytes data EEPROM with read-out protection. 300K write/erase cycles guaranteed, data retention: 20 years at 55 °C.
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Table of Contents ST7LITE0xY0, ST7LITESxY0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.3 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents To obtain the most recent version of this datasheet, please check at www.st.com Please also pay special attention to the Section “KNOWN LIMITATIONS” on page 121.
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ST7LITE0xY0, ST7LITESxY0 1 DESCRIPTION The ST7LITE0x and ST7SUPERLITE (ST7LITESx) are members of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST7LITE0x and ST7SUPERLITE feature FLASH memory with byte-by-byte In-Circuit Programming (ICP) and In-Application Programming (IAP) capability.
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ST7LITE0xY0, ST7LITESxY0 2 PIN DESCRIPTION PA0 (HS)/LTIC VSS VDD PB0/SS/AIN0 Figure 2. 20-Pin QFN Package Pinout 20 19 18 17 e3 e0 16 PA1 (HS) 2 15 PA2 (HS)/ATPWM0 NC 3 14 PA3 (HS) NC 4 13 NC MISO/AIN2/PB2 5 12 PA4 (HS) 11 PA5 (HS)/ICCDATA RESET 1 NC ei1 ei2 7 8 9 10 CLKIN/AIN4/PB4 PA7 MCO/ICCCLK/PA6 6 MOSI/AIN3/PB3 SCK/AIN1/PB1 (HS) 20mA High sink capability eix associated external interrupt vector Figure 3.
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ST7LITE0xY0, ST7LITESxY0 PIN DESCRIPTION (Cont’d) Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply In/Output level: C= CMOS 0.15VDD/0.85VDD with input trigger CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: – Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog – Output: OD = open drain, PP = push-pull Table 1.
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ST7LITE0xY0, ST7LITESxY0 Level Port / Control PP X X X Port A2 16 15 PA1 I/O CT HS X X X X Port A1 17 16 PA0/LTIC I/O CT HS X X X Port A0 ei0 ana X int I/O CT HS Pin Name Input 15 14 PA2/ATPWM0 QFN20 OD Main Function (after reset) wpu Output float Input Output Type SO16/DIP16 Pin n° Alternate Function Auto-Reload Timer PWM0 Lite Timer Input Capture Note: In the interrupt input column, “eix” defines the associated external interrupt vector.
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ST7LITE0xY0, ST7LITESxY0 3 REGISTER & MEMORY MAP As shown in Figure 4 and Figure 5, the MCU is capable of addressing 64K bytes of memories and I/ O registers. The available memory locations consist of up to 128 bytes of register locations, 128 bytes of RAM, 128 bytes of data EEPROM and up to 1.5 Kbytes of user program memory. The RAM space includes up to 64 bytes for the stack from 0C0h to 0FFh. The highest address bytes contain the user reset and interrupt vectors.
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ST7LITE0xY0, ST7LITESxY0 REGISTER AND MEMORY MAP (Cont’d) Figure 5. Memory Map (ST7SUPERLITE) 0000h 007Fh 0080h HW Registers (see Table 2) RAM (128 Bytes) 00FFh 0100h 0080h Short Addressing RAM (zero page) 00BFh 00C0h 64 Bytes Stack 00FFh Reserved 1K FLASH PROGRAM MEMORY FBFFh FC00h FC00h Flash Memory (1K) FDFFh FE00h FFFFh FFDFh FFE0h FFFFh Interrupt & Reset Vectors (see Table 6) 0.5 Kbytes SECTOR 1 0.5 Kbytes SECTOR 0 FFDEh RCCR0 FFDFh RCCR1 see section 7.
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ST7LITE0xY0, ST7LITESxY0 REGISTER AND MEMORY MAP (Cont’d) Legend: x=undefined, R/W=read/write Table 2.
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ST7LITE0xY0, ST7LITESxY0 Address Block 003Ah SI 003Bh to 007Fh Register Label SICSR Register Name System Integrity Control/Status Register Reset Status 0xh Remarks R/W Reserved area (69 bytes) Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value.
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ST7LITE0xY0, ST7LITESxY0 4 FLASH PROGRAM MEMORY 4.1 Introduction The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Programming. The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.
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ST7LITE0xY0, ST7LITESxY0 FLASH PROGRAM MEMORY (Cont’d) 4.4 ICC interface high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3.
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ST7LITE0xY0, ST7LITESxY0 FLASH PROGRAM MEMORY (Cont’d) 4.5 Memory Protection There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually. 4.5.1 Read out Protection Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory.
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ST7LITE0xY0, ST7LITESxY0 5 DATA EEPROM 5.1 INTRODUCTION 5.2 MAIN FEATURES The Electrically Erasable Programmable Read Only Memory can be used as a non-volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter. ■ ■ ■ ■ ■ ■ Up to 32 bytes programmed in the same cycle EEPROM mono-voltage (charge pump) Chained erase and programming cycles Internal control of the global programming cycle duration WAIT mode management Read-out protection Figure 7.
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ST7LITE0xY0, ST7LITESxY0 DATA EEPROM (Cont’d) 5.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 8 describes these different memory access modes. Read Operation (E2LAT = 0) The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared. On this device, Data EEPROM can also be used to execute machine code.
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ST7LITE0xY0, ST7LITESxY0 DATA EEPROM (Cont’d) Figure 9. Data E2PROM Write Operation ⇓ Row / Byte ⇒ ROW DEFINITION 0 1 2 3 ... 30 31 Physical Address 0 00h...1Fh 1 20h...3Fh ... Nx20h...
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ST7LITE0xY0, ST7LITESxY0 DATA EEPROM (Cont’d) 5.4 POWER SAVING MODES 5.5 ACCESS ERROR HANDLING Wait mode The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active Halt mode.The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode. If a read access occurs while E2LAT = 1, then the data bus will not be driven.
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ST7LITE0xY0, ST7LITESxY0 DATA EEPROM (Cont’d) 5.7 REGISTER DESCRIPTION EEPROM CONTROL/STATUS REGISTER (EECSR) Read/Write Reset Value: 0000 0000 (00h) 7 0 0 0 0 0 0 0 E2LAT E2PGM Bits 7:2 = Reserved, forced by hardware to 0. Bit 1 = E2LAT Latch Access Transfer This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared.
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ST7LITE0xY0, ST7LITESxY0 6 CENTRAL PROCESSING UNIT 6.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 6.2 MAIN FEATURES ■ ■ ■ ■ ■ ■ ■ ■ 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt 6.
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ST7LITE0xY0, ST7LITESxY0 CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx 7 1 0 1 1 H I N Z because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.
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ST7LITE0xY0, ST7LITESxY0 CPU REGISTERS (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 00 FFh 15 0 8 0 0 0 0 0 0 7 1 0 0 1 SP5 SP4 SP3 SP2 SP1 SP0 The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 12). Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware.
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ST7LITE0xY0, ST7LITESxY0 7 SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components.
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ST7LITE0xY0, ST7LITESxY0 Figure 13. PLL Output Frequency Timing Diagram LOCKED bit set 4/8 x input freq. Bit 1 = MCO Main Clock Out enable This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock. 0: MCO clock disabled, I/O port free for general purpose I/O. 1: MCO clock enabled. Output freq. tSTAB Bit 0 = SMS Slow Mode select This bit is read/write by software and cleared by hardware after a reset.
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ST7LITE0xY0, ST7LITESxY0 SUPPLY, RESET AND CLOCK MANAGEMENT (Cont’d) Figure 14.
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ST7LITE0xY0, ST7LITESxY0 7.4 RESET SEQUENCE MANAGER (RSM) 7.4.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 16: ■ External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to section 11.2.1 on page 53 for further details. These sources act on the RESET pin and it is always kept low during the delay phase.
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ST7LITE0xY0, ST7LITESxY0 RESET SEQUENCE MANAGER (Cont’d) 7.4.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details.
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ST7LITE0xY0, ST7LITESxY0 8 INTERRUPTS The ST7 core may be interrupted by one of two different methods: Maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 18. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection).
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ST7LITE0xY0, ST7LITESxY0 INTERRUPTS (Cont’d) Figure 18. Interrupt Processing Flowchart FROM RESET I BIT SET? N N Y Y FETCH NEXT INSTRUCTION N IRET? INTERRUPT PENDING? STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR Y EXECUTE INSTRUCTION RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT Table 6.
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ST7LITE0xY0, ST7LITESxY0 INTERRUPTS (Cont’d) EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h) 7 IS31 0 IS30 IS21 IS20 IS11 IS10 IS01 Notes: 1. These 8 bits can be written only when the I bit in the CC register is set. 2. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Refer to section “External interrupt function” on page 42.
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ST7LITE0xY0, ST7LITESxY0 8.4 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register. Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to section 12.2.1 on page 78 for further details. 8.4.
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ST7LITE0xY0, ST7LITESxY0 Figure 20.
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ST7LITE0xY0, ST7LITESxY0 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 8.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply voltage (VAVD). The VIT-(AVD) reference value for falling voltage is lower than the VIT+(AVD) reference value for rising voltage in order to avoid parasitic detection (hysteresis).
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ST7LITE0xY0, ST7LITESxY0 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 8.4.3 Low Power Modes Mode WAIT HALT set and the interrupt mask in the CC register is reset (RIM instruction). Description No effect on SI. AVD interrupts cause the device to exit from Wait mode. The SICSR register is frozen. The AVD remains active but the AVD interrupt cannot be used to exit from Halt mode. Interrupt Event AVD event Enable Event Control Flag Bit Exit from Wait Exit from Halt AVDF Yes No AVDIE 8.4.3.
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ST7LITE0xY0, ST7LITESxY0 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 8.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write If the AVDIE bit is set, an interrupt request is generated when the AVDF bit is set. Refer to Figure Reset Value: 0000 0x00 (0xh) 21 for additional details 0: VDD over AVD threshold 7 0 1: VDD under AVD threshold 0 0 0 0 LOCK ED LVDRF AVDF AVDIE Bit 7:4 = Reserved, must be kept cleared. Bit 3 = LOCKED PLL Locked Flag This bit is set by hardware.
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ST7LITE0xY0, ST7LITESxY0 9 POWER SAVING MODES 9.1 INTRODUCTION 9.2 SLOW MODE To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 22): SLOW, WAIT (SLOW WAIT), ACTIVE HALT and HALT. After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency (fOSC).
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ST7LITE0xY0, ST7LITESxY0 POWER SAVING MODES (Cont’d) 9.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is cleared, to enable all interrupts. All other registers and memory remain unchanged.
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ST7LITE0xY0, ST7LITESxY0 POWER SAVING MODES (Cont’d) 9.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the LTCSR/ATCSR register status as shown in the following table:. ATCSR LTCSR ATCSR ATCSR OVFIE TBIE bit CK1 bit CK0 bit bit 0 x x 0 0 0 x x 0 1 1 1 1 x x x x 1 0 1 Figure 25.
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ST7LITE0xY0, ST7LITESxY0 POWER SAVING MODES (Cont’d) 9.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when active halt mode is disabled. The MCU can exit HALT mode on reception of either a specific interrupt (see Table 6, “Interrupt Mapping,” on page 30) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 CPU cycle delay is used to stabilize the oscillator.
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ST7LITE0xY0, ST7LITESxY0 POWER SAVING MODES (Cont’d) 9.4.2.1 HALT Mode Recommendations – Make sure that an external event is available to wake up the microcontroller from Halt mode. – When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.
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ST7LITE0xY0, ST7LITESxY0 10 I/O PORTS 10.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 10.
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ST7LITE0xY0, ST7LITESxY0 – reset the interrupt mask with the RIM instruction (in cases where a pin level change could occur) Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain.
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ST7LITE0xY0, ST7LITESxY0 I/O PORTS (Cont’d) Figure 29. I/O Port General Block Diagram ALTERNATE OUTPUT REGISTER ACCESS 1 VDD 0 P-BUFFER (see table below) ALTERNATE ENABLE PULL-UP (see table below) DR VDD DDR PULL-UP CONDITION DATA BUS OR PAD If implemented OR SEL N-BUFFER DIODES (see table below) DDR SEL DR SEL ANALOG INPUT CMOS SCHMITT TRIGGER 1 0 EXTERNAL INTERRUPT SOURCE (eix) POLARITY SELECTION ALTERNATE INPUT FROM OTHER BITS Table 9.
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ST7LITE0xY0, ST7LITESxY0 I/O PORTS (Cont’d) Table 10.
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ST7LITE0xY0, ST7LITESxY0 I/O PORTS (Cont’d) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.
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ST7LITE0xY0, ST7LITESxY0 I/O PORTS (Cont’d) Table 12. I/O Port Register Map and Reset Values Address Register Label 7 6 5 4 3 2 1 0 0000h PADR Reset Value MSB 0 0 0 0 0 0 0 LSB 0 0001h PADDR Reset Value MSB 0 0 0 0 0 0 0 LSB 0 0002h PAOR Reset Value MSB 0 1 0 0 0 0 0 LSB 0 0003h PBDR Reset Value MSB 1 1 1 0 0 0 0 LSB 0 0004h PBDDR Reset Value MSB 0 0 0 0 0 0 0 LSB 0 0005h PBOR Reset Value MSB 0 0 0 0 0 0 0 LSB 0 (Hex.
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ST7LITE0xY0, ST7LITESxY0 11 ON-CHIP PERIPHERALS 11.1 LITE TIMER (LT) 11.1.1 Introduction ■ The Lite Timer can be used for general-purpose timing functions. It is based on a free-running 8-bit upcounter with two software-selectable timebase periods, an 8-bit input capture register and watchdog function. 11.1.
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ST7LITE0xY0, ST7LITESxY0 LITE TIMER (Cont’d) 11.1.3 Functional Description The value of the 8-bit counter cannot be read or written by software. After an MCU reset, it starts incrementing from 0 at a frequency of fOSC/32. A counter overflow event occurs when the counter rolls over from F9h to 00h. If fOSC = 8 MHz, then the time period between two counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the LTCSR register.
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ST7LITE0xY0, ST7LITESxY0 LITE TIMER (Cont’d) Figure 32.
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ST7LITE0xY0, ST7LITESxY0 LITE TIMER (Cont’d) Input Capture 11.1.5 Interrupts The 8-bit input capture register is used to latch the free-running upcounter after a rising or falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and the LTICR register contains the value of the free-running upcounter. An interrupt is generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.
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ST7LITE0xY0, ST7LITESxY0 LITE TIMER (Cont’d) 11.1.6 Register Description LITE TIMER CONTROL/STATUS REGISTER (LTCSR) Read / Write Reset Value: 0x00 0000 (x0h) 7 0 ICIE ICF TB TBIE TBF WDGR WDGE WDGD Bit 7 = ICIE Interrupt Enable This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled Bit 6 = ICF Input Capture Flag This bit is set by hardware and cleared by software by reading the LTICR register.
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ST7LITE0xY0, ST7LITESxY0 11.2 12-BIT AUTORELOAD TIMER (AT) 11.2.1 Introduction ■ The 12-bit Autoreload Timer can be used for general-purpose timing functions. It is based on a freerunning 12-bit upcounter with a PWM output channel. 11.2.
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ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) 11.2.3 Functional Description PWM Mode This mode allows a Pulse Width Modulated signals to be generated on the PWM0 output pin with minimum core processing overhead. The PWM0 output signal can be enabled or disabled using the OE0 bit in the PWMCR register. When this bit is set the PWM I/O pin is configured as output pushpull alternate function. Note: CMPF0 is available in PWM mode (see PWM0CSR description on page 57).
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ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) Figure 36. PWM Signal Example fCOUNTER PWM0 OUTPUT WITH OE0=1 AND OP0=0 ATR= FFDh COUNTER FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh DCR0=FFEh Output Compare Mode To use this function, the OE bit must be 0, otherwise the compare is done with the shadow register instead of the DCRx register. Software must then write a 12-bit value in the DCR0H and DCR0L registers. This value will be loaded immediately (without waiting for an OVF event).
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ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) 11.2.6 Register Description TIMER CONTROL STATUS REGISTER (ATCSR) Read / Write Reset Value: 0000 0000 (00h) 7 0 0 0 0 CK1 CK0 OVF OVFIE CMPIE hardware after a reset. It allows to mask the interrupt generation when CMPF bit is set. 0: CMPF interrupt disabled 1: CMPF interrupt enabled COUNTER REGISTER HIGH (CNTRH) Read only Reset Value: 0000 0000 (00h) 15 Bit 7:5 = Reserved, must be kept cleared. 0 Bit 4:3 = CK[1:0] Counter Clock Selection.
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ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) AUTO RELOAD REGISTER (ATRH) Read / Write Reset Value: 0000 0000 (00h) PWM0 DUTY CYCLE REGISTER LOW (DCR0L) Read / Write Reset Value: 0000 0000 (00h) 15 0 8 0 0 0 ATR11 ATR10 ATR9 ATR8 AUTO RELOAD REGISTER (ATRL) Read / Write Reset Value: 0000 0000 (00h) 0 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0 Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value This 12-bit value is written by software.
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ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) PWM OUTPUT CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h) 7 0 0 0 0 0 0 0 0 OE0 Bits 7:1 = Reserved, must be kept cleared. Bit 0 = OE0 PWM0 Output enable. This bit is set and cleared by software. 0: PWM0 output Alternate Function disabled (I/O pin free for general purpose I/O) 1: PWM0 output enabled Table 14.
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ST7LITE0xY0, ST7LITESxY0 11.3 SERIAL PERIPHERAL INTERFACE (SPI) 11.3.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can not be a master in a multi-master system. 11.3.
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ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 38. The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first). The communication is always initiated by the master.
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ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR register (see Figure 40) In software management, the external SS pin is free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
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ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
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ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 41). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
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ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.5 Error Flags 11.3.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: – The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set. – The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral. – The MSTR bit is reset, thus forcing the device into slave mode.
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ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.5.4 Single Master Systems A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 43). The master device selects the individual slave devices by using four pins of a parallel port to control the four SS pins of the slave devices. The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices.
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ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.6 Low Power Modes Mode WAIT HALT Description No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching).
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ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE 0 SPE SPR2 MSTR CPOL CPHA SPR1 SPR0 Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever SPIF=1, MODF=1 or OVR=1 in the SPICSR register Bit 6 = SPE Serial Peripheral Output Enable. This bit is set and cleared by software.
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ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF Bit 3 = Reserved, must be kept cleared. 0 WCOL OVR MODF - SOD SSM SSI Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the SPICR register.
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ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) Table 16. SPI Register Map and Reset Values Address Register Label 7 6 5 4 3 2 1 0 31 SPIDR Reset Value MSB x x x x x x x LSB x 32 SPICR Reset Value SPIE 0 SPE 0 SPR2 0 MSTR 0 CPOL x CPHA x SPR1 x SPR0 x 33 SPICSR Reset Value SPIF 0 WCOL 0 OVR 0 MODF 0 0 SOD 0 SSM 0 SSI 0 (Hex.
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ST7LITE0xY0, ST7LITESxY0 11.4 8-BIT A/D CONVERTER (ADC) 11.4.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 5 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 5 different sources. The result of the conversion is stored in a 8-bit Data Register.
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ST7LITE0xY0, ST7LITESxY0 Figure 44.
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ST7LITE0xY0, ST7LITESxY0 8-BIT A/D CONVERTER (ADC) (Cont’d) 11.4.3.3 Digital A/D Conversion Result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than or equal to VDDA (high-level voltage reference) then the conversion result in the DR register is FFh (full scale) without overflow indication.
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ST7LITE0xY0, ST7LITESxY0 8-BIT A/D CONVERTER (ADC) (Cont’d) 11.4.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write Reset Value: 0000 0000 (00h) DATA REGISTER (ADCDR) Read Only Reset Value: 0000 0000 (00h) 7 EOC SPEED ADON 0 0 CH2 CH1 0 7 CH0 D7 Bit 7 = EOC Conversion Complete This bit is set by hardware. It is cleared by software reading the result in the DR register or writing to the CSR register.
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ST7LITE0xY0, ST7LITESxY0 Table 17. ADC Register Map and Reset Values Address Register Label 7 6 5 4 3 2 1 0 34h ADCCSR Reset Value EOC 0 SPEED 0 ADON 0 0 0 CH2 0 CH1 0 CH0 0 35h ADCDR Reset Value D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 36h ADCAMP Reset Value 0 0 0 0 SLOW AMPSEL 0 0 0 0 (Hex.
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ST7LITE0xY0, ST7LITESxY0 12 INSTRUCTION SET 12.
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ST7LITE0xY0, ST7LITESxY0 ST7 ADDRESSING MODES (cont’d) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.
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ST7LITE0xY0, ST7LITESxY0 ST7 ADDRESSING MODES (cont’d) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode.
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ST7LITE0xY0, ST7LITESxY0 12.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions.
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ST7LITE0xY0, ST7LITESxY0 INSTRUCTION GROUPS (cont’d) Mnemo Description Function/Example Dst Src H I N Z C ADC Add with Carry A=A+M+C A M H N Z C ADD Addition A=A+M A M H N Z C AND Logical And A=A.M A M N Z BCP Bit compare A, Memory tst (A .
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ST7LITE0xY0, ST7LITESxY0 INSTRUCTION GROUPS (cont’d) Mnemo Description Function/Example Dst Src JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg MUL Multiply X,A = X * A A, X, Y X, Y, A NEG Negate (2's compl) neg $10 reg, M NOP No Operation OR OR operation A=A+M A M POP Pop from the Stack pop reg reg M pop CC CC M M reg, CC H I N Z N Z 0 H C 0 I N Z N Z N Z C C PUSH Push onto the Stack push Y RCF Reset carry flag C=0 RET
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ST7LITE0xY0, ST7LITESxY0 13 ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are referred to VSS. 13.1.1 Minimum and Maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25°C and TA=TAmax (given by the selected temperature range).
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ST7LITE0xY0, ST7LITESxY0 13.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi13.2.1 Voltage Characteristics Symbol VDD - VSS VIN VESD(HBM) tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Ratings Maximum value Supply voltage 7.0 Unit V Input voltage on any pin 1) & 2) VSS-0.
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ST7LITE0xY0, ST7LITESxY0 13.3 OPERATING CONDITIONS 13.3.1 General Operating Conditions: Suffix 6 Devices TA = -40 to +85°C unless otherwise specified. Symbol VDD fCLKIN Parameter Conditions Supply voltage External clock frequency on CLKIN pin Min Max fOSC = 8 MHz. max., 2.4 5.5 fOSC = 16 MHz. max. 3.3 5.5 3.3V≤ VDD≤5.5V up to 16 2.4V≤VDD<3.3V up to 8 Unit V MHz Figure 48.
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ST7LITE0xY0, ST7LITESxY0 13.3.2 Operating Conditions with Low Voltage Detector (LVD) TA = -40 to 85°C, unless otherwise specified Symbol Parameter Conditions Min 1) Typ Max Reset release threshold (VDD rise) High Threshold Med. Threshold Low Threshold 4.00 3.40 1) 2.65 1) 4.25 3.60 2.90 4.50 3.80 3.15 VIT-(LVD) Reset generation threshold (VDD fall) High Threshold Med. Threshold Low Threshold 3.80 3.20 2.40 4.05 3.40 2.70 4.30 1) 3.65 1) 2.
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ST7LITE0xY0, ST7LITESxY0 13.3.4 Internal RC Oscillator and PLL The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte). Symbol Parameter Conditions Min Typ Max VDD(RC) Internal RC Oscillator operating voltage 2.4 5.5 VDD(x4PLL) x4 PLL operating voltage 2.4 3.3 VDD(x8PLL) x8 PLL operating voltage 3.3 5.
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ST7LITE0xY0, ST7LITESxY0 OPERATING CONDITIONS (Cont’d) 13.3.4.2 Devices with ‘”6” order code suffix (tested for TA = -40 to +85°C) @ VDD = 2.7 to 3.3V Symbol Parameter Conditions fRC 1) Internal RC oscillator fre- RCCR = FF (reset value), TA=25°C, VDD= 3.0V quency RCCR=RCCR12) ,TA=25°C, VDD= 3V ACCRC Accuracy of Internal RC TA=25°C,VDD=3V oscillator when calibrated TA=25°C,VDD=2.7 to 3.
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ST7LITE0xY0, ST7LITESxY0 OPERATING CONDITIONS (Cont’d) Figure 51. Typical RC oscillator Accuracy vs temperature @ VDD=5V (Calibrated with RCCR0: 5V @ 25°C 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 2 (*) 1 RC Accuracy Output Freq (MHz) Figure 49. RC Osc Freq vs VDD @ TA=25°C (Calibrated with RCCR1: 3V @ 25°C) 0 (*) -1 -2 -3 -4 -5 ( ) * -45 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 0 4 25 85 125 Temperature (°C) VDD (V) (*) tested in production Figure 50.
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ST7LITE0xY0, ST7LITESxY0 OPERATING CONDITIONS (Cont’d) Figure 54. PLLx4 Output vs CLKIN frequency Figure 55. PLLx8 Output vs CLKIN frequency 7.00 5.00 3.3 4.00 3 2.7 3.00 2.00 1 1.5 2 2.5 External Input Clock Frequency (MHz) Note: fOSC = fCLKIN/2*PLL4 1 9.00 7.00 5.5 5 5.00 4.5 4 3.00 1.00 1.00 88/124 Output Frequency (MHz) Output Frequency (MHz) 11.00 6.00 3 0.85 0.9 1 1.5 2 External Input Clock Frequency (MHz) Note: fOSC = fCLKIN/2*PLL8 2.
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ST7LITE0xY0, ST7LITESxY0 13.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total de13.4.1 Supply Current TA = -40 to +85°C unless otherwise specified Symbol Conditions Supply current in RUN mode fCPU=8MHz 1) Supply current in WAIT mode Supply current in SLOW mode Supply current in SLOW WAIT mode Supply current in HALT mode 5) VDD=5.
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ST7LITE0xY0, ST7LITESxY0 SUPPLY CURRENT CHARACTERISTICS (Cont’d) Figure 58. Typical IDD in WAIT vs. fCPU Figure 60. Typical IDD vs. Temperature at VDD = 5V and fCPU = 8MHz 8MHz 2.0 5.00 1MHz 1.0 0.5 0.0 2.4 2.7 3.7 4.5 5 5.5 Vdd (V) Idd (mA) Idd (mA) 4MHz 1.5 4.50 4.00 3.50 3.00 RUN WAIT SLOW 2.50 2.00 1.50 SLOW WAIT 1.00 0.50 0.00 -45 25 Idd (mA) Figure 59. Typical IDD in SLOW-WAIT vs. fCPU 0.70 250kHz 0.60 125kHz 0.50 62.5kHz 90 130 Temperature (°C) 0.40 0.30 0.20 0.10 0.
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ST7LITE0xY0, ST7LITESxY0 13.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA. 13.5.1 General Timings Parameter 1) Symbol tc(INST) tv(IT) Conditions Instruction cycle time Interrupt reaction time tv(IT) = ∆tc(INST) + 10 fCPU=8MHz 3) fCPU=8MHz Min Typ 2) Max Unit 2 3 12 tCPU 250 375 1500 ns 10 22 tCPU 1.25 2.75 µs Max Unit 13.5.
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ST7LITE0xY0, ST7LITESxY0 13.6 MEMORY CHARACTERISTICS TA = -40°C to 105°C, unless otherwise specified 13.6.1 RAM and Hardware Registers Symbol VRM Parameter Data retention mode 1) Conditions HALT mode (or RESET) Min Typ Max 1.6 Unit V 13.6.2 FLASH Program Memory Symbol VDD tprog Parameter Min Programming time for 1~32 bytes 2) TA=−40 to +105°C Programming time for 1.5 kBytes TA=+25°C 4) tRET Data retention Write erase cycles Supply current Typ 2.
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ST7LITE0xY0, ST7LITESxY0 13.7 EMC (ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS Susceptibility tests are performed on a sample basis during product characterization. 13.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling two -+LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs).
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ST7LITE0xY0, ST7LITESxY0 EMC CHARACTERISTICS (Cont’d) 13.7.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. 13.7.3.1 Electro-Static Discharge (ESD) Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination.
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ST7LITE0xY0, ST7LITESxY0 13.8 I/O PORT PIN CHARACTERISTICS 13.8.1 General Characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Symbol Max Unit VIL Input low level voltage Parameter Conditions VSS - 0.3 Min Typ 0.3xVDD V VIH Input high level voltage 0.7xVDD VDD + 0.
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ST7LITE0xY0, ST7LITESxY0 I/O PORT PIN CHARACTERISTICS (Cont’d) 13.8.2 Output Driving Current Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
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ST7LITE0xY0, ST7LITESxY0 I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 64. Typical VOL at VDD=3.3V (standard) Figure 66. Typical VOL at VDD=5V (high-sink) 2.50 0.70 2.00 0.50 -45°C 0°C 25°C 90°C 130°C 0.40 0.30 0.20 Vol (V) at VDD=5V (HS) VOL at VDD=3.3V 0.60 -45 0°C 25°C 90°C 130°C 1.50 1.00 0.50 0.10 0.00 0.00 0.01 1 2 6 3 7 8 9 10 15 20 25 30 35 40 lio (mA) lio (mA) Figure 65. Typical VOL at VDD=5V (standard) Figure 67. Typical VOL at VDD=3V (high-sink) 1.20 0.
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ST7LITE0xY0, ST7LITESxY0 Figure 71. Typical VDD-VOH at VDD=4V Figure 69. Typical VDD-VOH at VDD=2.7V 1.20 2.50 1.00 -45°C 0°C 25°C 90°C 130°C 0.60 0.40 VDD-VOH at VDD=4V VDD-VOH at VDD=2.7V 2.00 0.80 -45°C 0°C 25°C 90°C 130°C 1.50 1.00 0.50 0.20 0.00 0.00 -0.01 -1 -2 -0.01 -1 -2 lio(mA) -3 -4 -5 lio (mA) Figure 72. Typical VDD-VOH at VDD=5V Figure 70. Typical VDD-VOH at VDD=3V 2.00 1.60 1.80 1.20 -45°C 0°C 25°C 90°C 130°C 1.00 0.80 0.60 VDD-VOH at VDD=5V VDD-VOH at VDD=3V 1.
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ST7LITE0xY0, ST7LITESxY0 Figure 74. Typical VOL vs. VDD (high-sink I/Os) 1.00 0.60 0.50 -45 0.40 0°C 25°C 0.30 90°C 130°C 0.20 0.10 VOL vs VDD (HS) at lio=20mA VOL vs VDD (HS) at lio=8mA 0.70 0.90 0.80 0.70 -45 0.60 0°C 0.50 25°C 0.40 90°C 0.30 0.20 130°C 0.10 0.00 0.00 2.4 3 2.4 5 3 5 VDD (V) VDD (V) Figure 75. Typical VDD-VOH vs. VDD 1.80 1.10 VDD-VOH at lio=-5mA 1.60 1.50 -45°C 0°C 25°C 90°C 130°C 1.40 1.30 1.20 1.10 1.00 VDD-VOH (V) at lio=-2mA 1.70 1.00 0.
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ST7LITE0xY0, ST7LITESxY0 13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin TA = -40°C to 105°C, unless otherwise specified Symbol Parameter Conditions Min Typ Max VIL Input low level voltage VSS - 0.3 0.3xVDD VIH Input high level voltage 0.7xVDD VDD + 0.3 Vhys Schmitt trigger voltage hysteresis 1) VOL RON Output low level voltage 2) VDD=5V Pull-up equivalent resistor 3) 1) th(RSTL)in External reset pulse hold time Filtered glitch duration 0.5 1.0 1.
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ST7LITE0xY0, ST7LITESxY0 CONTROL PIN CHARACTERISTICS (Cont’d) Figure 76. RESET pin protection when LVD is enabled.1)2)3)4) VDD Required Optional (note 3) ST72XXX RON EXTERNAL RESET INTERNAL RESET Filter 0.01µF 1MΩ PULSE GENERATOR WATCHDOG ILLEGAL OPCODE 5) LVD RESET Figure 77. RESET pin protection when LVD is disabled.1) VDD ST72XXX RON USER EXTERNAL RESET CIRCUIT INTERNAL RESET Filter 0.
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ST7LITE0xY0, ST7LITESxY0 13.10 COMMUNICATION INTERFACE CHARACTERISTICS 13.10.1 SPI - Serial Peripheral Interface Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Symbol Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO). Parameter Conditions Master fSCK = 1/tc(SCK) fCPU=8MHz SPI clock frequency Min Max fCPU/128 = 0.
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ST7LITE0xY0, ST7LITESxY0 COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 79. SPI Slave Timing Diagram with CPHA=11) SS INPUT SCK INPUT tsu(SS) tc(SCK) th(SS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) ta(SO) MISO OUTPUT see note 2 tv(SO) th(SO) MSB OUT HZ tsu(SI) BIT6 OUT LSB OUT tdis(SO) see note 2 th(SI) MSB IN MOSI INPUT tr(SCK) tf(SCK) BIT1 IN LSB IN Figure 80.
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ST7LITE0xY0, ST7LITESxY0 13.
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ST7LITE0xY0, ST7LITESxY0 ADC CHARACTERISTICS (Cont’d) Figure 82. RAIN max. vs fADC with CAIN=0pF1) Figure 83. Recommended CAIN/RAIN values2) 45 1000 Cain 10 nF 4 MHz 35 2 MHz 30 1 MHz 25 20 15 10 Cain 22 nF 100 Max. R AIN (Kohm) Max. R AIN (Kohm) 40 Cain 47 nF 10 1 5 0 0.1 0 10 30 70 CPARASITIC (pF) 0.01 0.1 1 10 fAIN(KHz) Notes: 1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3pF).
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ST7LITE0xY0, ST7LITESxY0 ADC CHARACTERISTICS (Cont’d) ADC Accuracy with VDD=5.0V TA = -40°C to 85°C, unless otherwise specified Symbol ET Parameter Total unadjusted error Conditions 2) Typ Offset error EG Gain Error 2) -0.5 / +1 fCPU=4MHz, fADC=2MHz ,VDD=5.0V ED Differential linearity error EL Integral linearity error 2) ET Total unadjusted error 2) Offset error EG Gain Error 2) ±1 2) ±1 LSB 1) ±11) ±2 2) EO Unit ±1 2) EO Max -0.5 / 3.5 fCPU=8MHz, fADC=4MHz ,VDD=5.
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ST7LITE0xY0, ST7LITESxY0 ADC CHARACTERISTICS (Cont’d) Figure 84. ADC Accuracy Characteristics with Amplifier disabled Digital Result ADCDR EG 255 254 1LSB 253 IDEAL V –V DDA SSA = ----------------------------------------256 ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one.
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ST7LITE0xY0, ST7LITESxY0 ADC CHARACTERISTICS (Cont’d) Vout (ADC input) Vmax Noise Vmin 0V Symbol 0V 250mV Parameter Conditions VDD(AMP) Amplifier operating voltage VIN Amplifier input voltage VOFFSET Amplifier offset voltage VSTEP Step size for monotonicity3) Output Voltage Response Linearity Vin (OPAMP input) VDD=5V Min Typ Max 5.
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ST7LITE0xY0, ST7LITESxY0 14 PACKAGE CHARACTERISTICS In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.
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ST7LITE0xY0, ST7LITESxY0 Figure 87. 16-Pin Plastic Dual In-Line Package, 300-mil Width Dim A2 A1 A L Min Typ A E c inches1) mm Max Min Typ Max 5.33 0.2098 A1 0.38 A2 2.92 3.30 4.95 0.1150 0.1299 0.1949 0.0150 b 0.36 0.46 0.56 0.0142 0.0181 0.0220 b2 1.14 1.52 1.78 0.0449 0.0598 0.0701 b3 0.76 0.99 1.14 0.0299 0.0390 0.0449 c 0.20 0.25 0.36 0.0079 0.0098 0.0142 D 18.67 19.18 19.69 0.7350 0.7551 0.7752 D1 0.13 E1 b2 D1 b eB e b3 D 0.0051 2.54 e 0.
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ST7LITE0xY0, ST7LITESxY0 14.2 THERMAL CHARACTERISTICS Symbol RthJA Ratings Package thermal resistance SO16 (junction to ambient) DIP16 Value Unit 95 TBD °C/W TJmax Maximum junction temperature 1) 150 °C PDmax Power dissipation 2) 500 mW Notes: 1. The maximum chip-junction temperature is based on technology characteristics. 2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA.
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ST7LITE0xY0, ST7LITESxY0 15 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (FASTROM). ST7PLITE0x and ST7PLITES2/S5 devices are Factory Advanced Service Technique ROM (FASTROM) versions: they are factory-programmed XFlash devices. ST7FLITE0x and ST7FLITES2/S5 XFlash devices are shipped to customers with a default program memory content (FFh). The OSC option bit is programmed to 0 by default.
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ST7LITE0xY0, ST7LITESxY0 OPTION BYTES (Cont’d) OPTION BYTE 1 Bit 7 = PLLx4x8 PLL Factor selection. 0: PLLx4 1: PLLx8 Bit 4 = OSC RC Oscillator selection 0: RC oscillator on 1: RC oscillator off Note: If the RC oscillator is selected, then to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.
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ST7LITE0xY0, ST7LITESxY0 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE Customer code is made up of the FASTROM contents and the list of the selected options (if any). The FASTROM contents are to be sent on diskette, or by electronic means, with the S19 hexadecimal file generated by the development tool. All unused bytes must be set to FFh. The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended.
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ST7LITE0xY0, ST7LITESxY0 Figure 89. Ordering information scheme Example: ST7 F LITES5 Y 0 M 6 TR Family ST7 Microcontroller Family Memory type F: Flash P: FASTROM Sub-family LITES2, LITES5, LITE02, LITE05 or LITE09 No. of pins Y = 16 Memory size 0 = 1K (LITESx versions) or 1.5K (LITE0x versions) Package B = DIP M = SO U = QFN Temperature range 6 = -40 °C to 85 °C Shipping Option TR = Tape & Reel packing Blank = Tube (DIP16 or SO16) or Tray (QFN20) For a list of available options (e.g.
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ST7LITE0xY0, ST7LITESxY0 ST7LITE0xY0 AND ST7LITESxY0 FASTROM MICROCONTROLLER OPTION LIST (Last update: November 2007) Customer Address .......................................................................... .......................................................................... .......................................................................... Contact .......................................................................... Phone No ..........................................................
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ST7LITE0xY0, ST7LITESxY0 15.3 DEVELOPMENT TOOLS Development tools for the ST7 microcontrollers include a complete range of hardware systems and software tools from STMicroelectronics and thirdparty tool suppliers. The range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers. 15.3.1 Starter kits ST offers complete, affordable starter kits.
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ST7LITE0xY0, ST7LITESxY0 15.4 ST7 APPLICATION NOTES Table 24.
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ST7LITE0xY0, ST7LITESxY0 Table 24.
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ST7LITE0xY0, ST7LITESxY0 Table 24.
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ST7LITE0xY0, ST7LITESxY0 16 KNOWN LIMITATIONS 16.1 Execution of BTJX Instruction Description Executing a BTJx instruction jumps to a random address in the following conditions: the jump goes to a lower address (jump backward) and the test is performed on a data located at the address 00FFh. 16.
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ST7LITE0xY0, ST7LITESxY0 17 REVISION HISTORY Table 25. Revision History Date 27-Oct-04 21-July-06 Revision Description of changes 3 Revision number incremented from 2.5 to 3.0 due to Internal Document Management System change Changed all references of ADCDAT to ADCDR Added EMU3 Emulator Programming Capability in Table 23 Clarification of read-out protection Altered note 1 for section 13.2.3 on page 82 removing references to RESET Alteration of fCPU for SLOW and SLOW-WAIT modes in Section 13.4.
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ST7LITE0xY0, ST7LITESxY0 09-Oct-06 19-Nov-07 5 Removed QFN20 pinout and mechanical data. Modified text in External Interrupt Function section in section 10.2.1 on page 42 Modified Table 24 on page 116 (and QFN20 rows in grey). Added “External Clock Source” on page 91 and Figure 61 on page 91 Modified description of CNTR[11:0] bits in section 11.2.6 on page 56 Updated option list on page 116 Changed section 15.3 on page 117 6 Title of the document modified Modified LOCKED bit description in section 8.
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ST7LITE0xY0, ST7LITESxY0 Notes: Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.