Datasheet

ST7LITE0xY0, ST7LITESxY0
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11.3 SERIAL PERIPHERAL INTERFACE (SPI)
11.3.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
11.3.2 Main Features
■ Full duplex synchronous transfers (on 3 lines)
■ Simplex synchronous transfers (on 2 lines)
■ Master or slave operation
■ Six master mode frequencies (f
CPU
/4 max.)
■ f
CPU
/2 max. slave mode frequency (see note)
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
■ Write collision, Master Mode Fault and Overrun
flags
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
11.3.3 General Description
Figure 37 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
The SPI is connected to external devices through
3 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
–SS
: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS
inputs can be driven by stand-
ard I/O ports on the master MCU.
Figure 37. Serial Peripheral Interface Block Diagram
SPIDR
Read Buffer
8-Bit Shift Register
Write
Read
Data/Address Bus
SPI
SPIE SPE
MSTR
CPHA
SPR0
SPR1
CPOL
SERIAL CLOCK
GENERATOR
MOSI
MISO
SS
SCK
CONTROL
STATE
SPICR
SPICSR
Interrupt
request
MASTER
CONTROL
SPR2
07
07
SPIF WCOL MODF
0
OVR SSISSMSOD
SOD
bit
SS
1
0
1