Datasheet

ST7LITE0xY0, ST7LITESxY0
27/124
7.4 RESET SEQUENCE MANAGER (RSM)
7.4.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in Figure 16:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to section 11.2.1 on page 53 for further details.
These sources act on the RESET
pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 15:
■ Active Phase depending on the RESET source
■ 256 CPU clock cycle delay
■ RESET vector fetch
The 256 CPU clock cycle delay allows the oscilla-
tor to stabilise and ensures that recovery has tak-
en place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of t
STARTUP
(see
Figure 13).
Figure 15. RESET Sequence Phases
Figure 16.Reset Block Diagram
RESET
Active Phase
INTERNAL RESET
256 CLOCK CYCLES
FETCH
VECTOR
RESET
R
ON
V
DD
INTERNAL
RESET
PULSE
GENERATOR
FILTER
Note 1: See “Illegal Opcode Reset” on page 78. for more details on illegal opcode reset conditions.
LVD RESET
WATCHDOG RESET
ILLEGAL OPCODE RESET
1)
1