Datasheet

ST7LITE0xY0, ST7LITESxY0
25/124
Figure 13. PLL Output Frequency Timing
Diagram
When the PLL is started, after reset or wakeup
from Halt mode or AWUFH mode, it outputs the
clock after a delay of t
STARTUP
.
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
is set. Full PLL accuracy (ACC
PLL
) is reached after
a stabilization time of t
STAB
(see Figure 13 and
13.3.4 Internal RC Oscillator and PLL)
Refer to section 8.4.4 on page 36 for a description
of the LOCKED bit in the SICSR register.
7.3 REGISTER DESCRIPTION
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by
hardware after a reset. This bit allows to enable
the MCO output clock.
0: MCO clock disabled, I/O port free for general
purpose I/O.
1: MCO clock enabled.
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the input
clock f
OSC
or f
OSC
/32.
0: Normal mode (f
CPU =
f
OSC
1: Slow mode (f
CPU =
f
OSC
/32)
RC CONTROL REGISTER (RCCR)
Read / Write
Reset Value: 1111 1111 (FFh)
Bits 7:0 = CR[7:0] RC Oscillator Frequency Ad-
justment Bits
These bits must be written immediately after reset
to adjust the RC oscillator frequency and to obtain
an accuracy of 1%. The application can store the
correct value for each voltage range in EEPROM
and write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
Note: To tune the oscillator, write a series of differ-
ent values in the register until the correct frequen-
cy is reached. The fastest method is to use a di-
chotomy starting with 80h.
Table 5. Clock Register Map and Reset Values
70
000000
MCO SMS
4/8 x
freq.
LOCKED bit set
t
STAB
t
LOCK
input
Output freq.
t
STARTUP
t
70
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
Address
(Hex.)
Register
Label
76543210
0038h
MCCSR
Reset Value
000000
MCO
0
SMS
0
0039h
RCCR
Reset Value
CR7
1
CR6
1
CR5
1
CR4
1
CR3
1
CR2
1
CR1
1
CR0
1
1