PIC16(L)F1946/1947 Data Sheet 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology 2010-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16(L)F1946/47 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology High-Performance RISC CPU: PIC16LF1946/47 Low-Power Features: • Only 49 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 32 MHz oscillator/clock input - DC – 125 ns instruction cycle • Up to 16K x 14 Words of Flash Program Memory • Up to 1024 Bytes of Data Memory (RAM) • Interrupt Capability with Automatic Context Saving • 16-Level Deep Hardware Stack
PIC16(L)F1946/47 Peripheral Features (Continued): • Two Master Synchronous Serial Ports (MSSPs) with SPI and I2 CTM with: - 7-bit address masking - SMBus/PMBusTM compatibility - Auto-wake-up on start • Two Enhanced Universal Synchronous: Asynchronous Receiver Transmitters (EUSARTs) - RS-232, RS-485 and LIN compatible - Auto-Baud Detect • SR Latch (555 Timer): - Multiple Set/Reset input options - Emulates 555 Timer applications • Three Comparators: - Rail-to-rail inputs/outputs - Power mode control - Softwar
PIC16(L)F1946/47 Pin Diagram – 64-Pin TQFP/QFN (PIC16(L)F1946/47) RE2 RE3 RE4 RE5 RE6 RE7 RD0 VDD VSS RD1 RD2 RD3 RD4 RD5 RD6 RD7 64-pin TQFP, QFN 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1 RE0 RG0 RG1 RG2 RG3 VPP/MCLR/RG5 RG4 VSS VDD RF7 RF6 RF5 RF4 RF3 RF2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC16(L)F1946/47 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RB0 RB1 RB2 RB3 RB4 RB5 RB6 VSS RA6 RA7 VDD RB7 RC5 RC4 RC3 RC2 Note 1: 2: 3: AVSS RA3 RA2 RA1 RA0 VSS VDD RA5 RA4 RC1 RC0 RC6 RC7
PIC16(L)F1946/47 Reference Cap Sense Comparator SR Latch Timers CCP USART MSSP LCD Y AN0 — CPS0 — — — — — — SEG33 — — — 23 Y AN1 — CPS1 — — — — — — SEG18 — — — Basic A/D 24 Pull-up ANSEL RA0 RA1 Interrupt 64-Pin TQFP, QFN 64-PIN SUMMARY(PIC16(L)F1946/47) I/O TABLE 1: RA2 22 Y AN2 VREF- CPS2 — — — — — — SEG34 — — — RA3 21 Y AN3 VREF+ CPS3 — — — — — — SEG35 — — — RA4 28 — — — — — — T0CKI — — — SEG14 — — — RA5 27
PIC16(L)F1946/47 Cap Sense Comparator SR Latch Timers CCP USART MSSP — — — — — — — — SS2 Y — — — — — — P2D(1) — RE1 1 Y — — — — — — P2C(1) — RE2 64 Y — — — — — — P2B(1) RE3 63 — — — — — — — P3C(1) Basic Reference — 2 Pull-up A/D 49 RE0 Interrupt ANSEL RD7 LCD 64-Pin TQFP, QFN 64-PIN SUMMARY(PIC16(L)F1946/47) (Continued) I/O TABLE 1: SEG7 — — — VLCD1 — — — — VLCD2 — — — — — VLCD3 — — — — — COM0 — — — RE4 62 —
PIC16(L)F1946/47 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 19 3.0 Memory Organization ..............................................................................
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PIC16(L)F1946/47 NOTES: DS41414D-page 10 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 1.0 DEVICE OVERVIEW The PIC16(L)F1946/47 are described within this data sheet. They are available in 64-pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F1946/47 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device.
PIC16(L)F1946/47 FIGURE 1-1: PIC16(L)F1946/47 BLOCK DIAGRAM Program Flash Memory RAM EEPROM PORTA OSC2/CLKOUT OSC1/CLKIN Timing Generation PORTB CPU INTRC Oscillator Figure 2-1 PORTC MCLR PORTD PORTE PORTF SR Latch ADC 10-Bit Timer0 Timer1 Timer2 Timer4 Timer6 Comparators LCD ECCP1 ECCP2 ECCP3 CCP4 CCP5 MSSPx EUSARTx Note 1: DS41414D-page 12 PORTG See applicable chapters for more information on peripherals. 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION Name RA0/AN0/CPS0/SEG33 RA1/AN1/CPS1/SEG18 RA2/AN2/VREF-/CPS2/SEG34 RA3/AN3/VREF+/CPS3/SEG35 RA4/T0CKI/SEG14 RA5/AN4/CPS4/SEG15 RA6/OSC2/CLKOUT/SEG36 RA7/OSC1/CLKIN/SEG37 RB0/INT/SRI/FLT0/SEG30 RB1/SEG8 Function Input Type RA0 TTL AN0 AN Output Type Description CMOS General purpose I/O. — A/D Channel input. CPS0 AN — Capacitive sensing input 0. SEG33 — AN LCD Analog output.
PIC16(L)F1946/47 TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION (CONTINUED) Name RB2/SEG9 RB3/SEG10 RB4/SEG11 RB5/T1G/SEG29 RB6/ICSPCLK/ICDCLK/SEG38 RB7/ICSPDAT/ICDDAT/SEG39 RC0/T1OSO/T1CKI/SEG40 RC1/T1OSI/P2A(1)/CCP2(1)/ SEG32 RC2/CCP1/P1A/SEG13 RC3/SCK/SCL/SEG17 RC4/SDI1/SDA1/SEG16 Function Input Type RB2 TTL SEG9 — RB3 TTL SEG10 — RB4 TTL SEG11 — RB5 TTL Output Type Description CMOS General purpose I/O. Individually controlled interrupt-on-change.
PIC16(L)F1946/47 TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION (CONTINUED) Name RC5/SDO1/SEG12 RC6/TX1/CK1/SEG27 RC7/RX1/DT1/SEG28 RD0/P2D(1)/SEG0 RD1/P2C(1)/SEG1 (1) RD2/P2B /SEG2 RD3/P3C(1)/SEG3 RD4/SDO2/P3B(1)/SEG4 RD5/SDI2/SDA2/P1C(1)/SEG5 RD6/SCK2/SCL2/P1B(1)/SEG6 RD7/SS2/SEG7 RE0/P2D(1)/VLCD1 Function Input Type Output Type RC5 ST CMOS General purpose I/O. CMOS SPI data output. Description SDO1 — SEG12 — RC6 ST CMOS General purpose I/O.
PIC16(L)F1946/47 TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION (CONTINUED) Name RE1/P2C(1)/VLCD2 RE2/P2B(1)/VLCD3 RE3/P3C(1)/COM0 RE4/P3B(1)/COM1 RE5/P1C(1)/COM2 RE6/P1B(1)/COM3 RE7/CCP2(1)/P2A(1)/SEG31 RF0/AN16/CPS16/C12IN0-/ SEG41/VCAP RF1/AN6/CPS6/C2OUT/SRNQ/ SEG19 RF2/AN7/CPS7/C1OUT/SRQ/ SEG20 Function Input Type Output Type RE1 ST CMOS General purpose I/O. CMOS PWM output. Description P2C — VLCD2 AN RE2 ST CMOS General purpose I/O. P2B — CMOS PWM output.
PIC16(L)F1946/47 TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION (CONTINUED) Name RF3/AN8/CPS8/C123IN2-/ SEG21 RF4/AN9/CPS9/C2IN+/SEG22 RF5/AN10/CPS10/C12IN1-/ DACOUT/SEG23 RF6/AN11/CPS11/C1IN+/SEG24 RF7/AN5/CPS5/C123IN3-/SS1/ SEG25 RG0/CCP3/P3A/SEG42 RG1/AN15/CPS15/TX2/CK2/ C3OUT/SEG43 Function Input Type RF3 ST Output Type Description CMOS General purpose I/O. AN8 AN — CPS8 AN — A/D Channel input. Capacitive sensing input. C1IN2- AN — Comparator negative input.
PIC16(L)F1946/47 TABLE 1-2: PIC16(L)F1946/47 PINOUT DESCRIPTION (CONTINUED) Name RG2/AN14/CPS14/RX2/DT2/ C3IN+/SEG44 RG3/AN13/CPS13/C3IN0-/ CCP4/P3D/SEG45 RG4/AN12/CPS12/C3IN1-/ CCP5/P1D/SEG26 Function Input Type RG2 ST AN14 AN — A/D Channel input. CPS14 AN — Capacitive sensing input. — USART2 asynchronous input. RX2 ST DT2 ST Output Type Description CMOS General purpose I/O. CMOS USART2 synchronous data. C3IN+ AN — Comparator positive input. SEG44 — AN LCD Analog output.
PIC16(L)F1946/1947 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.
PIC16(L)F1946/1947 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Indirect Addr 12 12 Direct Addr 7 5 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 Power-up Timer OSC1/CLKIN OSC2/CLKOUT Instruction Decodeand & Decode Control Timing Gene
PIC16(L)F1946/1947 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM • Data EEPROM memory(1) The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3.
PIC16(L)F1946/1947 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1946 FIGURE 3-2: PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE PC<14:0> 15 Stack Level 0 Stack Level 1 CALL, CALLW 15 RETURN, RETLW Interrupt, RETFIE Stack Level 0 Stack Level 1 Stack Level 15 Stack Level 15 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h 0005h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h On-chip Program Memory PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1947 Page 1 0FFFh 1000h P
PIC16(L)F1946/1947 3.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.
PIC16(L)F1946/1947 3.1.1.2 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower 8 bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.
PIC16(L)F1946/1947 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC16(L)F1946/1947 3.3.1 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.3.
PIC16(L)F1946/47 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 MEMORY MAP, BANKS 8-15 BANK 8 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 MEMORY MAP, BANKS 16-23 BANK 16 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 MEMORY MAP, BANKS 24-31 BANK 24 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/1947 TABLE 3-8: PIC16(L)F1946/47 MEMORY MAP, BANK 15 TABLE 3-9: Bank 15 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h 7A1h 7A2h 7A3h 7A4h 7A5h 7A6h 7A7h 7A8h 7A9h 7AAh 7ABh 7ACh 7ADh 7AEh 7AFh 7B0h 7B1h 7B2h 7B3h 7B4h 7B5h 7B6h 7B7h 7B8h LCDCON LCDPS LCDREF LCDCST LCDRL — — LCDSE0 LCDSE1 LCDSE2 LCDSE3 LCDSE4 LCDSE5 — — LCDDATA0 LCDDATA1 LCDDATA2 LCDDATA3 LCDDATA4 LCDDATA5 LCDDATA6 LCDDATA7 LCDDATA8 LCDDATA9 LCDDATA10 LCDDATA11 LCDDATA12 LCDDATA13 LCDDATA14
PIC16(L)F1946/1947 3.3.5 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register Summary for the device family are as follows: Device PIC16(L)F1946/1947 DS41414D-page 32 Bank(s) Page No. 0 33 1 34 2 35 3 36 4 37 5 38 6 39 7 40 8 41 9-14 43 15 44 16-30 46 31 47 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/1947 TABLE 3-10: Address Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 000h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 001h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 002h(2) PCL Program Counter (PC) Least
PIC16(L)F1946/1947 TABLE 3-10: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 1 080h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 081h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 082h(2) PCL Program Counte
PIC16(L)F1946/1947 TABLE 3-10: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 100h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 102h(2) PCL Program Counter
PIC16(L)F1946/1947 TABLE 3-10: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 3 180h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 181h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 182h(2) PCL Program Counte
PIC16(L)F1946/1947 TABLE 3-10: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 4 200h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 201h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 202h(2) PCL Program Counte
PIC16(L)F1946/1947 TABLE 3-10: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 5 280h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 281h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 282h(2) PCL Program Counte
PIC16(L)F1946/1947 TABLE 3-10: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 6 300h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 301h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 302h(2) PCL Program Counte
PIC16(L)F1946/1947 TABLE 3-10: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 7 380h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 381h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 382h(2) PCL Program Counter
PIC16(L)F1946/1947 TABLE 3-10: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 8 400h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 401h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 402h(2) PCL Program Counter
PIC16(L)F1946/1947 TABLE 3-10: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 9 480h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 481h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 482h(2) PCL Program Counte
PIC16(L)F1946/1947 TABLE 3-10: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Banks 10-14 x00h/ x80h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x00h/ x81h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x02h/ x82h(2
PIC16(L)F1946/1947 TABLE 3-10: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 15 780h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 781h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 782h(2) PCL Program Count
PIC16(L)F1946/1947 TABLE 3-10: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 15 (Continued) 7A6h LCDDATA6 SEG7 COM2 SEG6 COM2 SEG5 COM2 SEG4 COM2 SEG3 COM2 SEG2 COM2 SEG1 COM2 SEG0 COM2 xxxx xxxx uuuu uuuu 7A7h LCDDATA7 SEG15 COM2 SEG14 COM2 SEG13 COM2 SEG12 COM2 SEG11 COM2 SEG10 COM2 SEG9 COM2 SEG8 COM2 xxxx xxxx uuuu uuuu 7A8h LCDDATA8 SEG23 COM2 SEG22 COM2 S
PIC16(L)F1946/1947 TABLE 3-10: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Banks 16-30 x00h/ x80h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x00h/ x81h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x02h/ x82h(2
PIC16(L)F1946/1947 TABLE 3-10: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 31 F80h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F81h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F82h(2) PCL Program Count
PIC16(L)F1946/1947 3.4 PCL and PCLATH 3.4.3 COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC.
PIC16(L)F1946/1947 3.5 Stack 3.5.1 The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow.
PIC16(L)F1946/1947 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).
PIC16(L)F1946/1947 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.5.
PIC16(L)F1946/1947 FIGURE 3-9: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x1FFF 0x0FFF Reserved 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range 0x7FFF 0x8000 Reserved 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS41414D-page 52 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/1947 3.6.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.
PIC16(L)F1946/1947 3.6.2 3.6.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.
PIC16(L)F1946/1947 4.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Word 2 is managed automatically by device development tools including debuggers and programmers.
PIC16(L)F1946/1947 4.
PIC16(L)F1946/1947 REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED) bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.
PIC16(L)F1946/1947 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 (1) LVP R/P-1 DEBUG U-1 (2) — R/P-1 (3) BORV R/P-1 R/P-1 STVREN PLLEN bit 13 bit 8 U-1 U-1 U-1 R/P-1/1 U-1 U-1 — — — VCAPEN — — R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabl
PIC16(L)F1946/1947 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data EEPROM protection are controlled independently. Internal access to the program memory and data EEPROM are unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words.
PIC16(L)F1946/1947 4.6 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. 4.
PIC16(L)F1946/47 5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 5.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits.
PIC16(L)F1946/47 SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 5-1: External Oscillator LP, XT, HS, RC, EC OSC2 Sleep 4 x PLL Oscillator Timer1 FOSC<2:0> = 100 T1OSO IRCF<3:0> HFPLL 500 kHz Source 16 MHz (HFINTOSC) Postscaler Internal Oscillator Block 500 kHz (MFINTOSC) 31 kHz Source 31 kHz 31 kHz (LFINTOSC) DS41414D-page 62 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.
PIC16(L)F1946/47 5.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. Internal clock sources are contained within the oscillator module.
PIC16(L)F1946/47 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 5-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN C1 C1 To Internal Logic Quartz Crystal C2 OSC1/CLKIN RS(1) RF(2) Sleep RP(3) OSC2/CLKOUT Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M.
PIC16(L)F1946/47 5.2.1.5 5.2.1.6 TIMER1 Oscillator External RC Mode The Timer1 Oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins. The external Resistor-Capacitor (RC) modes support the use of an external RC circuit.
PIC16(L)F1946/47 5.2.2 INTERNAL CLOCK SOURCES The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the FOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.
PIC16(L)F1946/47 5.2.2.3 Internal Oscillator Frequency Adjustment The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 5-3). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator a change in the OSCTUNE register value will apply to both. The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number.
PIC16(L)F1946/47 5.2.2.6 32 MHz Internal Oscillator Frequency Selection The Internal Oscillator Block can be used with the 4x PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz internal clock source: • The FOSC bits in Configuration Words must be set to use the INTOSC source as the device system clock (FOSC<2:0> = 100).
PIC16(L)F1946/47 FIGURE 5-7: HFINTOSC/ MFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC/ MFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC/ MFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC/ MFINTO
PIC16(L)F1946/47 5.3 Clock Switching 5.3.3 TIMER1 OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The Timer1 oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins.
PIC16(L)F1946/47 5.4 Two-Speed Clock Start-up Mode 5.4.1 Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device.
PIC16(L)F1946/47 5.4.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 5.4.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
PIC16(L)F1946/47 5.5 Fail-Safe Clock Monitor 5.5.3 The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Timer1 Oscillator and RC).
PIC16(L)F1946/47 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: DS41414D-page 74 Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 5.
PIC16(L)F1946/47 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN = 1: 1 = Timer1 oscillato
PIC16(L)F1946/47 REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 100000 = Minimum frequency • • • 111111 = 000000 = Osc
PIC16(L)F1946/47 NOTES: DS41414D-page 78 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 6.0 RESETS There are multiple ways to reset this device: • • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 6-1.
PIC16(L)F1946/47 6.1 Power-on Reset (POR) 6.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level.
PIC16(L)F1946/47 FIGURE 6-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: 6.3 TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’.
PIC16(L)F1946/47 6.4 MCLR 6.8 The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table 6-2). TABLE 6-2: MCLR CONFIGURATION MCLRE LVP MCLR 0 0 Disabled 1 0 Enabled x 1 Enabled 6.4.1 MCLR ENABLED When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up.
PIC16(L)F1946/47 FIGURE 6-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power Up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start Up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 6.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers.
PIC16(L)F1946/47 6.12 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) Stack Overflow Reset (STKOVF) Stack Underflow Reset (STKUNF) MCLR Reset (RMCLR) The PCON register bits are shown in Register 6-2. 6.
PIC16(L)F1946/47 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN — — — — — — BORRDY 81 PCON STKOVF STKUNF — — RMCLR RI POR BOR 85 STATUS — — — TO PD Z DC C 25 WDTCON — — SWDTEN 109 WDTPS<4:0> Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
PIC16(L)F1946/47 7.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details.
PIC16(L)F1946/47 7.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1, PIE2, PIE3 and PIE4 registers) 7.
PIC16(L)F1946/47 FIGURE 7-2: INTERRUPT LATENCY OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKOUT Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst
PIC16(L)F1946/47 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Dummy Cycle 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) INTF flag is sampled here (every Q1).
PIC16(L)F1946/47 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC16(L)F1946/47 7.
PIC16(L)F1946/47 REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 G
PIC16(L)F1946/47 REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OSFIE C2IE C1IE EEIE BCLIE LCDIE C3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator
PIC16(L)F1946/47 REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 CCP5IE: CCP5 Interrupt Enable bit 1 = Enables the CC
PIC16(L)F1946/47 REGISTER 7-5: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 — — RC2IE TX2IE — — BCL2IE SSP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IE: USART2 Receive Interrupt Enable bit 1 = Enables the US
PIC16(L)F1946/47 REGISTER 7-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 =
PIC16(L)F1946/47 REGISTER 7-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interr
PIC16(L)F1946/47 REGISTER 7-8: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 CCP5IF: CCP5 Interrupt Flag bit 1 = Int
PIC16(L)F1946/47 REGISTER 7-9: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4 U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 — — RC2IF TX2IF — — BCL2IF SSP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IF: USART2 Receive Interrupt Flag bit 1 = Interrupt is pe
PIC16(L)F1946/47 TABLE 7-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92 INTEDG T0CS T0SE PSA ADIE RCIE TXIE SSPIE CCP1IE OPTION_REG WPUEN PIE1 TMR1GIE PIE2 OSFIE C2IE C1IE EEIE BCLIE PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE PIE4 — — RC2IE TX2IE PIR1 TMR1GIF ADIF RCIF TXIF PIR2 OSFIF C2IF C1IF PIR3 — CCP5IF CCP4IF PIR4 — — RC
PIC16(L)F1946/47 NOTES: DS41414D-page 102 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 8.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR The PIC16F1946/47 has an internal Low Dropout Regulator (LDO) which provides operation above 3.6V. The LDO regulates a voltage for the internal device logic while permitting the VDD and I/O pins to operate at a higher voltage. There is no user enable/disable control available for the LDO, it is always active. The PIC16LF1946/47 operates at a maximum VDD of 3.6V and does not incorporate an LDO.
PIC16(L)F1946/47 NOTES: DS41414D-page 104 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 9.0 POWER-DOWN MODE (SLEEP) 9.1 Wake-up from Sleep The Power-Down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. WDT will be cleared but keeps running, if enabled for operation during Sleep. 2. PD bit of the STATUS register is cleared. 3. TO bit of the STATUS register is set. 4. CPU clock is disabled. 5.
PIC16(L)F1946/47 9.1.1 WAKE-UP USING INTERRUPTS • If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared.
PIC16(L)F1946/47 10.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.
PIC16(L)F1946/47 10.1 Independent Clock Source 10.3 Time-Out Period The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 30.0 “Electrical Specifications” for the LFINTOSC tolerances. The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is 2 seconds. 10.
PIC16(L)F1946/47 10.
PIC16(L)F1946/47 TABLE 10-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Bit 7 Bit 6 OSCCON — STATUS — — — — WDTCON Legend: CONFIG1 Legend: Bit 4 Bit 3 IRCF<3:0> — Bit 2 Bit 1 — TO PD Bit 0 SCS<1:0> Z DC WDTPS<4:0> Register on Page 75 C 25 SWDTEN 109 x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
PIC16(L)F1946/47 11.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL The data EEPROM and Flash program memory are readable and writable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers (SFRs).
PIC16(L)F1946/47 11.2 Using the Data EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM without exceeding the total number of write cycles to a single byte. Refer to Section 30.
PIC16(L)F1946/47 Required Sequence EXAMPLE 11-2: DATA EEPROM WRITE BANKSEL MOVLW MOVWF MOVLW MOVWF BCF BCF BSF EEADRL DATA_EE_ADDR EEADRL DATA_EE_DATA EEDATL EECON1, CFGS EECON1, EEPGD EECON1, WREN ; ; ;Data Memory Address to write ; ;Data Memory Value to write ;Deselect Configuration space ;Point to DATA memory ;Enable writes BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF BTFSC GOTO INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, EECON1, $-2 ;Disable INTs.
PIC16(L)F1946/47 11.3 Flash Program Memory Overview It is important to understand the Flash program memory structure for erase and programming operations. Flash Program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum block size that can be erased by user software.
PIC16(L)F1946/47 EXAMPLE 11-3: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI: PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWL EEADRL PROG_ADDR_LO EEADRL PROG_ADDR_HI EEADRH ; Select Bank for EEPROM registers ; ; Store LSB of address ; ; Store MSB of address BCF BSF BCF BSF NOP NOP BSF EECON1,CFGS EECON1,EEPGD INTCON,GIE EECON1,RD INTCON,GIE ; ; ; ; ; ; ; Do not
PIC16(L)F1946/47 11.3.2 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. 6. Load the EEADRH:EEADRL register pair with the address of new row to be erased. Clear the CFGS bit of the EECON1 register. Set the EEPGD, FREE, and WREN bits of the EECON1 register. Write 55h, then AAh, to EECON2 (Flash programming unlock sequence). Set control bit WR of the EECON1 register to begin the erase operation.
PIC16(L)F1946/47 After the “BSF EECON1,WR” instruction, the processor requires two cycles to set up the write operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms, only during the cycle in which the write takes place (i.e., the last word of the block write). This is not Sleep mode as the clocks and peripherals will FIGURE 11-2: continue to run. The processor does not stall when LWLO = 1, loading the write latches.
PIC16(L)F1946/47 EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY - Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase block is loaded in ADDRH:ADDRL ; 2.
PIC16(L)F1946/47 EXAMPLE 11-5: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL 4.
PIC16(L)F1946/47 11.4 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. 8. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory.
PIC16(L)F1946/47 11.6 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example 11-6) to the desired value to be written. Example 11-6 shows how to verify a write to EEPROM.
PIC16(L)F1946/47 11.
PIC16(L)F1946/47 REGISTER 11-3: R/W-0/0 EEADRL: EEPROM ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 EEADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address REGISTER 11-4: U-1
PIC16(L)F1946/47 REGISTER 11-5: EECON1: EEPROM CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 EEPGD CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 EEPGD: Flash Program/Data EEPROM Memory Sel
PIC16(L)F1946/47 REGISTER 11-6: W-0/0 EECON2: EEPROM CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 EEPROM Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR
PIC16(L)F1946/47 NOTES: DS41414D-page 126 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 12.0 I/O PORTS FIGURE 12-1: GENERIC I/O PORT OPERATION Each port has three standard registers for its operation. These registers are: • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) Some ports may have one or more of the following additional registers.
PIC16(L)F1946/47 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 12-1. For this device family, the following functions can be moved between different pins.
PIC16(L)F1946/47 12.
PIC16(L)F1946/47 12.3 PORTA Registers PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 12-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). Example 12-1 shows how to initialize PORTA.
PIC16(L)F1946/47 12.
PIC16(L)F1946/47 REGISTER 12-5: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 ANSA5: Analog Select between Analog or Digital Function on pin
PIC16(L)F1946/47 12.5 PORTB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 12-7). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1946/47 12.
PIC16(L)F1946/47 REGISTER 12-9: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: 2: WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pu
PIC16(L)F1946/47 12.7 PORTC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 12-11). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1946/47 12.
PIC16(L)F1946/47 TABLE 12-8: Name APFCON LATC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page P3CSEL P3BSEL P2DSEL P2CSEL P2BSEL CCP2SEL P1CSEL P1BSEL 129 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 137 LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 341 LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 341 LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 341 LCDSE4 SE39 SE38 SE37 SE36 SE35
PIC16(L)F1946/47 12.9 PORTD Registers PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 12-13). Setting a TRISD bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1946/47 12.
PIC16(L)F1946/47 TABLE 12-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name APFCON CCPxCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page P3CSEL P3BSEL P2DSEL P2CSEL P2BSEL CCP2SEL P1CSEL P1BSEL 129 PxM<1:0>(1) DCxB<1:0> LATD LATD7 LATD6 LATD5 LATD4 LCDCON LCDEN SLPEN WERR — LCDSE0 SE7 SE6 SE5 SE4 CCPxM<3:0> LATD3 LATD2 CS<1:0> SE3 SE2 LATD1 238 LATD0 LMUX<1:0> SE1 140 337 SE0 341 PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 140 TRISD TRI
PIC16(L)F1946/47 12.11 PORTE Registers PORTE is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 12-1 shows how to initialize an I/O port.
PIC16(L)F1946/47 12.
PIC16(L)F1946/47 REGISTER 12-18: LATE: PORTE DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared LATE<7:0>: PORTE Output Latch Value bits(1) bit 7-0 Note 1: Writes to PORTE are actual
PIC16(L)F1946/47 12.13 PORTF Registers PORTF is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISF (Register 12-21). Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1946/47 12.
PIC16(L)F1946/47 REGISTER 12-23: ANSELF: PORTF ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 ANSF7 ANSF6 ANSF5 ANSDF4 ANSF3 ANSF2 ANSDF1 ANSF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: ANSF<7:0>: Analog Select between Analog or Digital Function on
PIC16(L)F1946/47 12.15 PORTG Registers PORTG is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISG (Register 12-25). Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISG bit (= 0) will make the corresponding PORTG pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1946/47 12.16 Register Definitions: PORTG REGISTER 12-24: PORTG: PORTG REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — RG5 RG4 RG3 RG2 RG1 RG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’.
PIC16(L)F1946/47 REGISTER 12-27: ANSELG: PORTG ANALOG SELECT REGISTER U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 — — — ANSG4 ANSG3 ANSG2 ANSG1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’.
PIC16(L)F1946/47 TABLE 12-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Name Bit 7 ADCON0 — ANSELG — CCPxCON Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> — PxM<1:0>(1) — ANSG4 ANSG3 ANSG2 DCxB<1:0> Bit 1 Bit 0 Register on Page GO/DONE ADON 168 ANSG1 — 150 CCPxM<3:0> — — — — — MC3OUT CM1CON1 C1INTP C1INTN C1PCH1 C1PCH0 — — C1NCH<1:0> 186 CM2CON1 C2INTP C2INTN C2PCH1 C2PCH0 — — C2NCH<1:0> 186 CPSCON0 CPSON CPSRM — — CPSCON1 — — — — LATG — — — LATG4
PIC16(L)F1946/47 NOTES: DS41414D-page 152 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 13.0 INTERRUPT-ON-CHANGE The PORTB pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTB pin, or combination of PORTB pins, can be configured to generate an interrupt.
PIC16(L)F1946/47 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx D Q4Q1 Q CK edge detect R RBx IOCBPx D data bus = 0 or 1 Q write IOCBFx CK D S Q to data bus IOCBFx CK IOCIE R Q2 from all other IOCBFx individual pin detectors Q1 Q3 Q4 Q4Q1 DS41414D-page 154 Q1 Q1 Q2 Q2 Q2 Q3 Q4 Q4Q1 IOC interrupt to CPU core Q3 Q4 Q4 Q4Q1 Q4Q1 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 13.
PIC16(L)F1946/47 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 155 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 155 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 155 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRI
PIC16(L)F1946/47 14.0 FIXED VOLTAGE REFERENCE (FVR) 14.1 The output of the FVR supplied to the ADC, Comparators, DAC and CPS module is routed through two independent programmable gain amplifiers. Each amplifier can be configured to amplify the reference voltage by 1x, 2x or 4x, to produce the three possible voltage levels. The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels.
PIC16(L)F1946/47 14.
PIC16(L)F1946/47 15.0 TEMPERATURE INDICATOR MODULE FIGURE 15-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.
PIC16(L)F1946/47 15.4 ADC Acquisition Time To ensure accurate temperature measurements, the user must wait at least 200 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 s between sequential conversions of the temperature indicator output.
PIC16(L)F1946/47 16.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC16(L)F1946/47 FIGURE 16-1: ADC BLOCK DIAGRAM ADNREF = 1 VREF- ADNREF = 0 VDD VSS ADPREF = 00 ADPREF = 11 VREF+ AN0 00000 AN1 00001 VREF-/AN2 00010 VREF+/AN2 00011 AN4 00100 AN5 00101 AN6 00110 AN7 00111 AN8 01000 AN9 01001 AN10 01010 AN11 01011 AN12 01100 AN13 01101 AN14 01110 AN15 01111 AN16 10000 Temp Indicator DAC Output 11101 11110 FVR Buffer1 11111 ADPREF = 10 Ref+ RefADC 10 GO/DONE ADFM 0 = Left Justify 1 = Right Justify 16 ADON VSS ADRESH ADRESL C
PIC16(L)F1946/47 16.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 16.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 12.
PIC16(L)F1946/47 TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s Fosc/4 100 125 ns (2) (2) (2) (2) Fosc/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) Fosc/16 101 800 ns 800 ns 1.0 s Fosc/32 1.0 s 010 200 ns 1.6 s 250 ns 2.0 s Fosc/64 110 2.0 s 3.2 s 4.
PIC16(L)F1946/47 16.1.5 INTERRUPTS 16.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format.
PIC16(L)F1946/47 16.2 16.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 16.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 16.3.2 “A/D Conversion Procedure”.
PIC16(L)F1946/47 16.3.2 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC16(L)F1946/47 16.
PIC16(L)F1946/47 REGISTER 16-2: R/W-0/0 ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 R/W-0/0 — ADNREF R/W-0/0 R/W-0/0 ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified.
PIC16(L)F1946/47 REGISTER 16-3: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 16-4: R/W-x/u A
PIC16(L)F1946/47 REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use.
PIC16(L)F1946/47 16.5 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 16-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 16-4.
PIC16(L)F1946/47 Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. FIGURE 16-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.
PIC16(L)F1946/47 TABLE 16-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 Bit 5 — ADCON0 ADCON1 Bit 6 Bit 4 Bit 3 CHS<4:0> ADFM — ADCS<2:0> ADRESH A/D Result Register High ADRESL A/D Result Register Low — ANSA5 ANSELF ANSELF7 ANSELF6 ANSELF5 ANSELF4 ANSELF3 ANSELG — — — ANSELG4 ANSELG3 INTCON Bit 0 Register on Page GO/DONE ADON 168 ADPREF<1:0> 169 170 — P1M<1:0> ADNREF Bit 1 170 ANSELA CCP1CON Bit 2 — ANSA3 DC1B<1:0> ANSA2 ANSA1 ANSA0 132 ANSELF2 A
PIC16(L)F1946/47 17.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. The input of the DAC can be connected to: 17.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register.
PIC16(L)F1946/47 FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) FVR BUFFER2 VSOURCE+ VDD 5 VREF+ DACR<4:0> R R DACPSS<1:0> 2 R DACEN DACLPS R 32 Steps R 32-to-1 MUX R DAC Output R (To Comparator, CPS and ADC Modules) DACOUT R DACOE DACNSS VREF- VSOURCE- VSS FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance DS41414D-page 176 DACOUT + – Buffered DAC Output 2010-2012 Microchi
PIC16(L)F1946/47 17.4 Low-Power Voltage State In order for the DAC module to consume the least amount of power, one of the two voltage reference input sources to the resistor ladder must be disconnected. Either the positive voltage source, (VSOURCE+), or the negative voltage source, (VSOURCE-) can be disabled. The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the DACLPS bit in the DACCON0 register disables the positive voltage source. 17.4.
PIC16(L)F1946/47 17.
PIC16(L)F1946/47 18.0 COMPARATOR MODULE FIGURE 18-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution.
PIC16(L)F1946/47 FIGURE 18-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM CxNCH<1:0> CxON(1) 2 CxINTP Interrupt det CXIN0- 0 CXIN1- 1 MUX 2 (2) CXIN2CXIN3- 3 Set CxIF det CXPOL CxVN D Cx(3) CxVP DAC Output 0 MUX 1 (2) FVR Buffer2 2 CXIN+ to CMXCON0 (CXOUT) and CM2CON1 (MCXOUT) Q + EN Q1 CxHYS CxSP async_CxOUT 3 CXSYNC CxON VSS CxINTN Interrupt CXPCH<1:0> CXOE to PWM TRIS bit CXOUT 0 2 D (from Timer1) T1CLK Note 1: 2: 3: Q 1 sync_CxOUT To Timer1 or SR Latch When Cx
PIC16(L)F1946/47 18.2 Comparator Control Each comparator has 2 control registers: CMxCON0 and CMxCON1.
PIC16(L)F1946/47 18.3 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. 18.5 Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a Falling edge detector are present. See Section 30.
PIC16(L)F1946/47 18.7 Comparator Negative Input Selection The CxNCH<1:0> bits of the CMxCON0 register direct one of four analog pins to the comparator inverting input. Note: 18.8 To use CxIN+ and CxINx- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers.
PIC16(L)F1946/47 FIGURE 18-3: ANALOG INPUT MODEL VDD Rs < 10K Analog Input pin VT 0.6V RIC To Comparator VA CPIN 5 pF VT 0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Source Impedance RS = Analog Voltage VA = Threshold Voltage VT Note 1: See Section 30.0 “Electrical Specifications” DS41414D-page 184 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 18.
PIC16(L)F1946/47 REGISTER 18-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 CxPCH<1:0> U-0 U-0 — — R/W-0/0 R/W-0/0 CxNCH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt
PIC16(L)F1946/47 TABLE 18-3: Name ANSELF ANSELG SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSF7 ANSF6 ANSF5 ANSF4 ANSF3 ANSF2 ANSF1 ANSF0 147 — — — ANSG4 ANSG3 ANSG2 ANSG1 — 150 CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 185 CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC CM1CON1 C1NTP C1INTN C1PCH<1:0> — — CM2CON1 C2NTP C2INTN C2PCH<1:0> — — CM3CON0 C3ON C3OUT
PIC16(L)F1946/47 NOTES: DS41414D-page 188 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 19.0 SR LATCH The module consists of a single SR Latch with multiple Set and Reset inputs as well as separate latch outputs. The SR Latch module includes the following features: • • • • Programmable input selection SR Latch output is available externally Separate Q and Q outputs Firmware Set and Reset The SR Latch can be used in a variety of analog applications, including oscillator circuits, one-shot circuit, hysteretic controllers, and analog timing applications. 19.
PIC16(L)F1946/47 FIGURE 19-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM SRPS Pulse Gen(2) SRLEN SRQEN SRI S SRSPE SRCLK Q SRQ SRSCKE sync_C2OUT(3) SRSC2E sync_C1OUT(3) SRSC1E SRPR SR Latch(1) Pulse Gen(2) SRI SRRPE SRCLK SRRCKE sync_C2OUT(3) SRRC2E R Q SRNQ SRLEN SRNQEN sync_C1OUT(3) SRRC1E Note 1: 2: 3: DS41414D-page 190 If R = 1 and S = 1 simultaneously, Q = 0, Q = 1. Pulse generator causes a 1 Q-state pulse width. Name denotes the connection point at the comparator output.
PIC16(L)F1946/47 TABLE 19-1: SRCLK FREQUENCY TABLE SRCLK Divider FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz FOSC = 1 MHz 111 512 110 256 62.5 kHz 39.0 kHz 31.3 kHz 7.81 kHz 1.95 kHz 125 kHz 78.1 kHz 62.5 kHz 15.6 kHz 3.90 kHz 101 100 128 250 kHz 156 kHz 125 kHz 31.25 kHz 7.81 kHz 64 500 kHz 313 kHz 250 kHz 62.5 kHz 15.6 kHz 011 32 1 MHz 625 kHz 500 kHz 125 kHz 31.3 kHz 010 16 2 MHz 1.25 MHz 1 MHz 250 kHz 62.5 kHz 001 8 4 MHz 2.
PIC16(L)F1946/47 19.
PIC16(L)F1946/47 REGISTER 19-2: SRCON1: SR LATCH CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = SR Latch is set when th
PIC16(L)F1946/47 NOTES: DS41414D-page 194 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 20.0 TIMER0 MODULE When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. The Timer0 module is an 8-bit timer/counter with the following features: • • • • • • Note: 8-bit timer/counter register (TMR0) 8-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow TMR0 can be used to gate Timer1 20.1.
PIC16(L)F1946/47 20.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register.
PIC16(L)F1946/47 20.
PIC16(L)F1946/47 NOTES: DS41414D-page 198 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 21.0 TIMER1 MODULE WITH GATE CONTROL • • • • The Timer1 module is a 16-bit timer/counter with the following features: Figure 21-1 is a block diagram of the Timer1 module.
PIC16(L)F1946/47 21.1 Timer1 Operation 21.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 21-2 displays the clock source selections. 21.2.1 When used with an internal clock source, the module is a timer and increments on every instruction cycle.
PIC16(L)F1946/47 21.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 21.4 Timer1 Oscillator 21.5.
PIC16(L)F1946/47 21.6.2 TIMER1 GATE SOURCE SELECTION Timer1 gate source selections are shown in Table 21-4. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register.
PIC16(L)F1946/47 21.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine.
PIC16(L)F1946/47 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 21-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 DS41414D-page 204 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 21-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF N Cleared by software 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 21-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF DS41414D-page 206 N Cleared by software N+1 N+2 N+3 Set by hardware on falling edge of T1GVAL N+4 Cleared by software 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 21.
PIC16(L)F1946/47 REGISTER 21-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0/u R/W-0/u T1GSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit I
PIC16(L)F1946/47 TABLE 21-5: Name CCP1CON CCP2CON INTCON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 P1M<1:0> P2M<1:0> Bit 5 Bit 4 Bit 3 DC1B<1:0> Bit 2 Bit 1 Bit 0 CCP1M<3:0> DC2B<1:0> Register on Page 238 CCP2M<3:0> 238 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 93 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 97 TMR1H Holding Register for the Most Significant Byte of the 16-bit T
PIC16(L)F1946/47 NOTES: DS41414D-page 210 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 22.0 TIMER2/4/6 MODULES There are up to three identical Timer2-type modules available. To maintain pre-existing naming conventions, the Timers are called Timer2, Timer4 and Timer6 (also Timer2/4/6). Note: The ‘x’ variable used in this section is used to designate Timer2, Timer4, or Timer6. For example, TxCON references T2CON, T4CON or T6CON. PRx references PR2, PR4 or PR6.
PIC16(L)F1946/47 22.1 Timer2/4/6 Operation The clock input to the Timer2/4/6 modules is the system instruction clock (FOSC/4). TMRx increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, TxCKPS<1:0> of the TxCON register. The value of TMRx is compared to that of the Period register, PRx, on each clock cycle.
PIC16(L)F1946/47 22.
PIC16(L)F1946/47 TABLE 22-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6 Bit 7 CCP2CON Bit 6 P2M<1:0> Bit 5 Bit 4 Bit 3 DC2B<1:0> Bit 2 Bit 1 Bit 0 CCP2M<3:0> Register on Page 238 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 93 PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 95 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 97 PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — INTCON
PIC16(L)F1946/47 23.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle.
PIC16(L)F1946/47 23.1 Capture Mode 23.1.2 The Capture mode function described in this section is available and identical for CCP modules ECCP1, ECCP2, ECCP3, CCP4 and CCP5. Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively.
PIC16(L)F1946/47 23.1.5 CAPTURE DURING SLEEP 23.1.6 Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON.
PIC16(L)F1946/47 23.2 Compare Mode 23.2.2 The Compare mode function described in this section is available and identical for CCP modules ECCP1, ECCP2, ECCP3, CCP4 and CCP5. Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair.
PIC16(L)F1946/47 23.2.5 COMPARE DURING SLEEP 23.2.6 The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. TABLE 23-4: Name CCPxCON ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON.
PIC16(L)F1946/47 23.3 PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps.
PIC16(L)F1946/47 23.3.2 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. 5. 6. 7. Disable the CCPx pin output driver by setting the associated TRIS bit. Timer2/4/6 resource selection: • Select the Timer2/4/6 resource to be used for PWM generation by setting the CxTSEL<1:0> bits in the CCPTMRSx register. Load the PRx register with the PWM period value.
PIC16(L)F1946/47 23.3.6 PWM RESOLUTION EQUATION 23-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PRx is 255. The resolution is a function of the PRx register value as shown by Equation 23-4.
PIC16(L)F1946/47 23.3.7 OPERATION IN SLEEP MODE 23.3.10 In Sleep mode, the TMRx register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMRx will continue from its previous state. 23.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON.
PIC16(L)F1946/47 23.4 PWM (Enhanced Mode) To select an Enhanced PWM Output mode, the PxM bits of the CCPxCON register must be configured appropriately. The enhanced PWM function described in this section is available for CCP modules ECCP1, ECCP2 and ECCP3, with any differences between modules noted. The PWM outputs are multiplexed with I/O pins and are designated PxA, PxB, PxC and PxD.
PIC16(L)F1946/47 TABLE 23-9: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM<1:0> CCPx/PxA PxB PxC PxD Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: PWM Steering enables outputs in Single mode.
PIC16(L)F1946/47 FIGURE 23-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) PxM<1:0> Signal PRx+1 Pulse Width 0 Period 00 (Single Output) PxA Modulated PxA Modulated 10 (Half-Bridge) Delay Delay PxB Modulated PxA Active 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCO
PIC16(L)F1946/47 23.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCPx/PxA pin, while the complementary PWM output signal is output on the PxB pin (see Figure 23-9). This mode can be used for Half-Bridge applications, as shown in Figure 23-9, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals.
PIC16(L)F1946/47 23.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure 23-10. In the Forward mode, pin CCPx/PxA is driven to its active state, pin PxD is modulated, while PxB and PxC will be driven to their inactive state as shown in Figure 23-11. In the Reverse mode, PxC is driven to its active state, pin PxB is modulated, while PxA and PxD will be driven to their inactive state as shown Figure 23-11.
PIC16(L)F1946/47 FIGURE 23-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period PxA (2) Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) Note 1: 2: (1) At this time, the TMRx register is equal to the PRx register. Output signal is shown as active-high. 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 23.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the PxM1 bit in the CCPxCON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the PxM1 bit of the CCPxCON register.
PIC16(L)F1946/47 FIGURE 23-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period PxA PxB PW PxC PxD PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: T = TOFF – TON All signals are shown as active-high. 2: TON is the turn on delay of power switch QC and its driver. 3: TOFF is the turn off delay of power switch QD and its driver. 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 23.4.3 ENHANCED PWM AUTO-SHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the CCPxAS<2:0> bits of the CCPxAS register.
PIC16(L)F1946/47 FIGURE 23-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PXRSEN = 0) Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow Missing Pulse (CCPxASE not clear) Timer Overflow Timer Overflow Timer Overflow PWM Period PWM Activity Start of PWM Period Shutdown Event CCPxASE bit Shutdown Event Occurs 23.4.4 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed.
PIC16(L)F1946/47 23.4.5 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 23-16: In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC16(L)F1946/47 23.4.6 PWM STEERING MODE In Single Output mode, PWM steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode is selected (CCPxM<3:2> = 11 and PxM<1:0> = 00 of the CCPxCON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STRx bits of the PSTRxCON register, as shown in Table 23-9.
PIC16(L)F1946/47 23.4.6.1 Steering Synchronization The STRxSYNC bit of the PSTRxCON register gives the user two selections of when the steering event will happen. When the STRxSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRxCON register. In this case, the output signal at the Px pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin.
PIC16(L)F1946/47 23.4.8 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a reset, see Section 12.1 “Alternate Pin Function” for more information.
PIC16(L)F1946/47 23.
PIC16(L)F1946/47 REGISTER 23-2: R/W-0/0 CCPTMRS0: PWM TIMER SELECTION CONTROL REGISTER 0 R/W-0/0 R/W-0/0 C4TSEL<1:0> R/W-0/0 R/W-0/0 C3TSEL<1:0> R/W-0/0 R/W-0/0 C2TSEL<1:0> R/W-0/0 C1TSEL<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 C4TSEL<1:0>: CCP4 Timer Selection 11 = Reserved 10 = CCP4 is base
PIC16(L)F1946/47 REGISTER 23-4: R/W-0/0 CCPxAS: CCPX AUTO-SHUTDOWN CONTROL REGISTER R/W-0/0 CCPxASE R/W-0/0 R/W-0/0 CCPxAS<2:0> R/W-0/0 R/W-0/0 R/W-0/0 PSSxAC<1:0> R/W-0/0 PSSxBD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCPxASE: CCPx Auto-Shutdown Event Status bit 1 = A shutdown event has occurr
PIC16(L)F1946/47 REGISTER 23-5: R/W-0/0 PWMxCON: ENHANCED PWM CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 PxRSEN R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxDC<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown
PIC16(L)F1946/47 PSTRxCON: PWM STEERING CONTROL REGISTER(1) REGISTER 23-6: U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 — — — STRxSYNC STRxD STRxC STRxB STRxA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 STRxSYNC: Steering Sync bit 1 = Output steering updat
PIC16(L)F1946/47 24.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP1 AND MSSP2) MODULE 24.1 Master SSPx (MSSPx) Module Overview The Master Synchronous Serial Port (MSSPx) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16(L)F1946/47 The I2C interface supports the following modes and features: Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDAx hold times Note 1: In devices with more than one MSSP module, it is very important to pay close attention to SSPxCONx register names.
PIC16(L)F1946/47 FIGURE 24-3: MSSPx BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSPxBUF Reg SCLx Shift Clock SSPxSR Reg SDAx MSb LSb SSPxMSK Reg Match Detect Addr Match SSPxADD Reg Start and Stop bit Detect 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 24.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a chip select known as Slave Select.
PIC16(L)F1946/47 FIGURE 24-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCKx SCKx SDOx SDIx SDIx SDOx General I/O General I/O SSx General I/O SCKx SDIx SDOx SPI Slave #1 SPI Slave #2 SSx SCKx SDIx SDOx SPI Slave #3 SSx 24.2.1 SPI MODE REGISTERS The MSSPx module has five registers for SPI mode operation.
PIC16(L)F1946/47 24.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
PIC16(L)F1946/47 24.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx line. The master determines when the slave (Processor 2, Figure 24-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input).
PIC16(L)F1946/47 24.2.4 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCKx pin. The Idle state is determined by the CKP bit of the SSPxCON1 register.
PIC16(L)F1946/47 FIGURE 24-7: SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDOx SDIx SDIx SDOx General I/O SPI Slave #1 SSx SCK SDIx SDOx SPI Slave #2 SSx SCK SDIx SDOx SPI Slave #3 SSx FIGURE 24-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPxSR and bit count are reset SSPxBUF to SSPxSR SDOx bit 7 bit 6 bit 7 SDIx bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF 2010-
PIC16(L)F1946/47 FIGURE 24-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active FIGURE 24-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3
PIC16(L)F1946/47 24.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in full power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSPx clock is much faster than the system clock. In Slave mode, when MSSPx interrupts are enabled, after the master completes sending data, an MSSPx interrupt will wake the controller from Sleep.
PIC16(L)F1946/47 24.3 I2C MODE OVERVIEW The Inter-Integrated Circuit Bus (I²C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A Slave device is controlled through addressing. VDD SCLx The I2C bus specifies two signal connections: • Serial Clock (SCLx) • Serial Data (SDAx) Figure 24-2 and Figure 24-3 show the block diagrams of the MSSPx module when operating in I2C mode.
PIC16(L)F1946/47 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCLx line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDAx line, it is called arbitration.
PIC16(L)F1946/47 24.4.4 SDAX HOLD TIME The hold time of the SDAx pin is selected by the SDAHT bit of the SSPxCON3 register. Hold time is the time SDAx is held valid after the falling edge of SCLx. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. TABLE 24-2: I2C BUS TERMS TERM Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus.
PIC16(L)F1946/47 24.4.5 START CONDITION has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. The I2C specification defines a Start condition as a transition of SDAx from a high to a low state while SCLx line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state.
PIC16(L)F1946/47 I2C SLAVE MODE OPERATION 24.4.9 ACKNOWLEDGE SEQUENCE 24.5 The 9th SCLx pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDAx line low. The transmitter must release control of the line during this time to shift in the response.
PIC16(L)F1946/47 24.5.2 SLAVE RECEPTION 24.5.2.2 7-bit Reception with AHEN and DHEN When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the 8th falling edge of SCLx.
DS41414D-page 260 SSPOV BF SSPxIF S 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 D4 5 D3 6 D2 7 D1 SSPxBUF is read Cleared by software 3 D5 Receiving Data 8 9 2 D6 First byte of data is available in SSPxBUF 1 D0 ACK D7 4 D4 5 D3 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent.
2010-2012 Microchip Technology Inc. CKP SSPOV BF SSPxIF 1 SCLx S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCLx SSPxBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPxBUF 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent.
DS41414D-page 262 P S ACKTIM CKP ACKDT BF SSPxIF S Receiving Address 1 3 5 6 7 8 ACK the received byte Slave software clears ACKDT to Address is read from SSBUF If AHEN = 1: SSPxIF is set 4 ACKTIM set by hardware on 8th falling edge of SCLx When AHEN=1: CKP is cleared by hardware and SCLx is stretched 2 A7 A6 A5 A4 A3 A2 A1 Receiving Data 9 2 3 4 5 6 7 ACKTIM cleared by hardware in 9th rising edge of SCLx When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCLx S
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PIC16(L)F1946/47 24.5.3 SLAVE TRANSMISSION 24.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave.
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PIC16(L)F1946/47 24.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure 24-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle.
2010-2012 Microchip Technology Inc. D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPxIF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCLx 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPxBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address.
PIC16(L)F1946/47 24.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION 24.5.5 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD This section describes a standard sequence of events for the MSSPx module configured as an I2C Slave in 10-bit Addressing mode. Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCLx line is held low are the same.
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DS41414D-page 270 ACKTIM CKP UA ACKDT BF 2 1 5 0 6 A9 7 A8 Set by hardware on 9th falling edge 4 1 ACKTIM is set by hardware on 8th falling edge of SCLx If when AHEN = 1; on the 8th falling edge of SCLx of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte 3 1 8 R/W = 0 9 ACK UA 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 Update to SSPxADD is not allowed until 9th falling edge of SCLx SSPxBUF can be read anytime before the next received byte Clear
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PIC16(L)F1946/47 24.5.6 CLOCK STRETCHING 24.5.6.2 10-bit Addressing Mode Clock stretching occurs when a device on the bus holds the SCLx line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching.
PIC16(L)F1946/47 24.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices.
PIC16(L)F1946/47 24.6 I2C MASTER MODE Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPxCON1 register and by setting the SSPEN bit. In Master mode, the SDAx and SCKx pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions.
PIC16(L)F1946/47 24.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting.
PIC16(L)F1946/47 24.6.4 I2C MASTER MODE START CONDITION TIMING by hardware; the Baud Rate Generator is suspended, leaving the SDAx line held low and the Start condition is complete. To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSPxCON2 register. If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count.
PIC16(L)F1946/47 24.6.5 I2C MASTER MODE REPEATED START CONDITION TIMING SSPxCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As soon as a Start condition is detected on the SDAx and SCLx pins, the S bit of the SSPxSTAT register will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out.
PIC16(L)F1946/47 24.6.6 I2C MASTER MODE TRANSMISSION 24.6.6.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted.
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PIC16(L)F1946/47 24.6.7 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN bit of the SSPxCON2 register. Note: The MSSPx module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCLx pin changes (high-to-low/low-to-high) and data is shifted into the SSPxSR.
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PIC16(L)F1946/47 24.6.8 ACKNOWLEDGE SEQUENCE TIMING 24.6.9 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPxCON2 register. At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC16(L)F1946/47 FIGURE 24-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG after SDAx sampled high. P bit (SSPxSTAT<4>) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set Falling edge of 9th clock TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 24.6.
PIC16(L)F1946/47 FIGURE 24-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCLx = 0 SDAx line pulled low by another source SDAx released by master Sample SDAx. While SCLx is high, data does not match what is driven by the master. Bus collision has occurred. SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF DS41414D-page 284 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 24.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx are sampled low at the beginning of the Start condition (Figure 24-32). SCLx is sampled low before SDAx is asserted low (Figure 24-33). During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 24-34).
PIC16(L)F1946/47 FIGURE 24-34: BUS COLLISION DURING START CONDITION (SCLX = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF.
PIC16(L)F1946/47 24.6.13.2 Bus Collision During a Repeated Start Condition If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 24-35). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time.
PIC16(L)F1946/47 24.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 24-37).
PIC16(L)F1946/47 TABLE 24-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 93 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE C3IE CCP2IE(1) 94 SSP2IE 96 97 Name INTCON (1) PIE4 — — RC2IE TX2IE — — BCL2IE PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF PIR2 OSFIF C2IF C1IF
PIC16(L)F1946/47 24.7 BAUD RATE GENERATOR The MSSPx module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 24-6). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. module clock line.
PIC16(L)F1946/47 24.
PIC16(L)F1946/47 REGISTER 24-2: SSPxCON1: SSPx CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode:
PIC16(L)F1946/47 REGISTER 24-2: bit 3-0 SSPxCON1: SSPx CONTROL REGISTER 1 (CONTINUED) SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled 0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C
PIC16(L)F1946/47 REGISTER 24-3: SSPxCON2: SSPx CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit
PIC16(L)F1946/47 REGISTER 24-4: SSPxCON3: SSPx CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is
PIC16(L)F1946/47 REGISTER 24-5: R/W-1/1 SSPxMSK: SSPx MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPxADD to detect I2C address match 0 = The received address
PIC16(L)F1946/47 25.0 Note: ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device.
PIC16(L)F1946/47 FIGURE 25-2: EUSART RECEIVE BLOCK DIAGRAM CREN RXx/DTx pin Baud Rate Generator Data Recovery FOSC BRG16 +1 SPxBRGH SPxBRGL RSR Register MSb Pin Buffer and Control Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop RCIDL OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCxREG Register 8 FIFO Data Bus RCxIF RCxIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXxSTA) •
PIC16(L)F1946/47 25.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC16(L)F1946/47 25.1.1.5 TSR Status 25.1.1.7 The TRMT bit of the TXxSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXxREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user needs to poll this bit to determine the TSR status. Note: 25.1.1.
PIC16(L)F1946/47 FIGURE 25-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXxREG Word 1 BRG Output (Shift Clock) TXx/CKx pin Word 2 Start bit bit 0 bit 1 Word 1 1 TCY TXxIF bit (Interrupt Reg. Flag) bit 7/8 Stop bit Start bit Word 2 bit 0 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Transmit Shift Reg Word 2 Transmit Shift Reg This timing diagram shows two consecutive transmissions.
PIC16(L)F1946/47 25.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode would typically be used in RS-232 systems. The receiver block diagram is shown in Figure 25-2. The data is received on the RXx/DTx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC16(L)F1946/47 25.1.2.4 Receive Interrupts The RCxIF interrupt flag bit of the PIR1/PIR3 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCxIF interrupt flag bit is read-only, it cannot be set or cleared by software.
PIC16(L)F1946/47 25.1.2.9 Asynchronous Reception Set-up: 1. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 25.4 “EUSART Baud Rate Generator (BRG)”). 2. Set the RXx/DTx and TXx/CKx TRIS controls to ‘1’. 3. Enable the serial port by setting the SPEN bit and the RXx/DTx pin TRIS bit. The SYNC bit must be clear for asynchronous operation. 4.
PIC16(L)F1946/47 FIGURE 25-5: ASYNCHRONOUS RECEPTION Start bit bit 0 RXx/DTx pin bit 1 bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg Start bit bit 7/8 Stop bit bit 0 bit 7/8 Stop bit Word 2 RCxREG Word 1 RCxREG RCIDL Start bit Read Rcv Buffer Reg RCxREG RCxIF (Interrupt Flag) OERR bit CREN This timing diagram shows three words appearing on the RXx/DTx input. The RCxREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
PIC16(L)F1946/47 25.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (HFINTOSC). However, the HFINTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the HFINTOSC output.
PIC16(L)F1946/47 25.
PIC16(L)F1946/47 REGISTER 25-2: RCxSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port disabled (held in Reset) bi
PIC16(L)F1946/47 REGISTER 25-3: BAUDxCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto
PIC16(L)F1946/47 25.4 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDxCON register selects 16-bit mode. The SPxBRGH:SPxBRGL register pair determines the period of the free running baud rate timer.
PIC16(L)F1946/47 TABLE 25-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 309 BAUD2CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 309 RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 308 RC2STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 308 SP1BRGL EUSART1 Baud Rate Generator, Low Byte 310* SP1BRGH EUSART1 Baud Rate Generator, High Byte 310*
PIC16(L)F1946/47 TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error FOSC = 18.432 MHz SPxBRGL value (decimal) Actual Rate % Error FOSC = 16.000 MHz SPxBRGL value (decimal) Actual Rate % Error FOSC = 11.
PIC16(L)F1946/47 TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate FOSC = 4.000 MHz % Error SPxBRGH: SPxBRGL (decimal) Actual Rate % Error FOSC = 3.6864 MHz SPxBRGH: SPxBRGL (decimal) Actual Rate % Error FOSC = 1.000 MHz SPxBRGH: SPxBRGL (decimal) Actual Rate % Error SPxBRGH: SPxBRGL (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.
PIC16(L)F1946/47 25.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RXx signal, the RXx signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge.
PIC16(L)F1946/47 25.4.2 AUTO-BAUD OVERFLOW During the course of automatic baud detection, the ABDOVF bit of the BAUDxCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPxBRGH:SPxBRGL register pair. After the ABDOVF bit has been set, the counter continues to count until the fifth rising edge is detected on the RXx/DTx pin.
PIC16(L)F1946/47 FIGURE 25-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RXx/DTx Line RCxIF Note 1: Cleared due to User Read of RCxREG The EUSART remains in Idle while the WUE bit is set.
PIC16(L)F1946/47 25.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXxSTA register. The Break character transmission is then initiated by a write to the TXxREG. The value of data written to TXxREG will be ignored and all ‘0’s will be transmitted.
PIC16(L)F1946/47 25.5 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC16(L)F1946/47 25.5.1.5 1. 2. 3. Synchronous Master Transmission Set-up: 4. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 25.4 “EUSART Baud Rate Generator (BRG)”). Set the RXx/DTx and TXx/CKx TRIS controls to ‘1’. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Set the TRIS bits corresponding to the RXx/DTx and TXx/CKx I/O pins. 5. 6. 7. FIGURE 25-10: 8. 9.
PIC16(L)F1946/47 TABLE 25-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 309 BAUD2CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 309 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92 93 INTCON PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE PIE4 — — RC2IE TX2IE — — BCL2IE SSP2IE 96 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1
PIC16(L)F1946/47 25.5.1.6 Synchronous Master Reception Data is received at the RXx/DTx pin. The RXx/DTx pin output driver must be disabled by setting the corresponding TRIS bits when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCxSTA register) or the Continuous Receive Enable bit (CREN of the RCxSTA register).
PIC16(L)F1946/47 FIGURE 25-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RXx/DTx pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TXx/CKx pin (SCKP = 0) TXx/CKx pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCxIF bit (Interrupt) Read RCxREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PIC16(L)F1946/47 25.5.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Setting the SYNC bit of the TXxSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXxSTA register configures the device as a slave.
PIC16(L)F1946/47 TABLE 25-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 309 BAUD2CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 309 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92 93 INTCON PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE PIE4 — — RC2IE TX2IE — — BCL2IE SSP2IE 96 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1I
PIC16(L)F1946/47 25.5.2.3 EUSART Synchronous Slave Reception 25.5.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 25.5.1.6 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode 1. Set the SYNC and SPEN bits and clear the CSRC bit. Set the RXx/DTx and TXx/CKx TRIS controls to ‘1’.
PIC16(L)F1946/47 NOTES: DS41414D-page 326 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 26.0 CAPACITIVE SENSING (CPS) MODULE The Capacitive Sensing (CPS) module allows for an interaction with an end user without a mechanical interface. In a typical application, the CPS module is attached to a pad on a Printed Circuit Board (PCB), which is electrically isolated from the end user. When the end user places their finger over the PCB pad, a capacitive load is added, causing a frequency shift in the CPS module.
PIC16(L)F1946/47 FIGURE 26-2: CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM Oscillator Module VDD (1) + (2) - S CPSx (1) Analog Pin - (2) Q CPSCLK R + Internal References Ref- 0 0 1 Ref+ DAC 1 FVR CPSRM Note 1: 2: Module Enable and Power mode selections are not shown. Comparators remain active in Noise Detection mode. DS41414D-page 328 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 26.1 Analog MUX 26.2.1 VOLTAGE REFERENCE MODES The CPS module can monitor up to 16 inputs. The capacitive sensing inputs are defined as CPS<15:0>. To determine if a frequency change has occurred the user must: The capacitive sensing oscillator uses voltage references to provide two voltage thresholds for oscillation. The upper voltage threshold is referred to as Ref+ and the lower voltage threshold is referred to as Ref-.
PIC16(L)F1946/47 26.2.2 CURRENT RANGES The remaining mode is a Noise Detection mode that resides within the high range. The Noise Detection mode is unique in that it disables the sinking and sourcing of current on the analog pin but leaves the rest of the oscillator circuitry active. This reduces the oscillation frequency on the analog pin to zero and also greatly reduces the current consumed by the oscillator module. The capacitive sensing oscillator can operate in one of seven different power modes.
PIC16(L)F1946/47 26.2.4.2 Timer1 26.2.5.2 To select Timer1 as the timer resource for the CPS module, set the TMR1CS<1:0> of the T1CON register to ‘11’. When Timer1 is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for Timer1. Because the Timer1 module has a gate control, developing a time base for the frequency measurement can be simplified by using the Timer0 overflow flag.
PIC16(L)F1946/47 26.3 Operation during Sleep The capacitive sensing oscillator will continue to run as long as the module is enabled, independent of the part being in Sleep. In order for the software to determine if a frequency change has occurred, the part must be awake. However, the part does not have to be awake when the timer resource is acquiring counts. Note: Timer0 does not operate when in Sleep, and therefore cannot be used for capacitive sense measurements in Sleep.
PIC16(L)F1946/47 26.
PIC16(L)F1946/47 REGISTER 26-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1 U-0 U-0 U-0 — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CPSCH<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 CPSCH<4:0>: Capacitive Sensing Channel Select bits If CPSON = 0: These b
PIC16(L)F1946/47 27.0 LIQUID CRYSTAL DISPLAY (LCD) DRIVER MODULE The Liquid Crystal Display (LCD) driver module generates the timing control to drive a static or multiplexed LCD panel. In the PIC16(L)F1946/47 device, the module drives the panels of up to four commons and up to 46 segments. The LCD module also provides control of the LCD pixel data.
PIC16(L)F1946/47 TABLE 27-1: LCD SEGMENT AND DATA REGISTERS # of LCD Registers Device PIC16(L)F1946/47 Segment Enable Data 6 24 The LCDCON register (Register 27-1) controls the operation of the LCD driver module. The LCDPS register (Register 27-2) configures the LCD clock source prescaler and the type of waveform; Type-A or Type-B. The LCDSEn registers (Register 27-5) configure the functions of the port pins.
PIC16(L)F1946/47 27.
PIC16(L)F1946/47 REGISTER 27-2: LCDPS: LCD PHASE REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 WFT BIASMD LCDA WA R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 LP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit bit 7 WFT: Waveform Type bit 1 = Type-B phase changes on each frame boundary 0 = Type-A phase c
PIC16(L)F1946/47 REGISTER 27-3: LCDREF: LCD REFERENCE VOLTAGE CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 LCDIRE LCDIRS LCDIRI — VLCD3PE VLCD2PE VLCD1PE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit bit 7 LCDIRE: LCD Internal Reference Enable bit 1 = I
PIC16(L)F1946/47 REGISTER 27-4: LCDCST: LCD CONTRAST CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0/0 R/W-0/0 R/W-0/0 LCDCST<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 LCDCST<2:0>: LCD Contrast Control bits Selects the resista
PIC16(L)F1946/47 REGISTER 27-5: LCDSEn: LCD SEGMENT ENABLE REGISTERS R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SEn SEn SEn SEn SEn SEn SEn SEn bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SEn: Segment Enable bits 1 = Segment function of the pin is enabled 0 = I/O function of
PIC16(L)F1946/47 27.3 LCD Clock Source Selection Using bits CS<1:0> of the LCDCON register can select any of these clock sources. The LCD module has 3 possible clock sources: 27.3.1 • FOSC/256 • T1OSC • LFINTOSC The first clock source is the system clock divided by 256 (FOSC/256). This divider ratio is chosen to provide about 1 kHz output when the system clock is 8 MHz. The divider is not programmable.
PIC16(L)F1946/47 27.
PIC16(L)F1946/47 27.5 LCD Bias Internal Reference Ladder The internal reference ladder can be used to divide the LCD bias voltage two or three equally spaced voltages that will be supplied to the LCD segment pins. To create this, the reference ladder consists of three matched resistors. Refer to Figure 27-3. 27.5.2 POWER MODES The internal reference ladder may be operated in one of three power modes. This allows the user to trade off LCD contrast for power in the specific application.
PIC16(L)F1946/47 27.5.3 AUTOMATIC POWER MODE SWITCHING The LCDRL register allows switching between two power modes, designated ‘A’ and ‘B’. ‘A’ Power mode is active for a programmable time, beginning at the time when the LCD segments transition. ‘B’ Power mode is the remaining time before the segments or commons change again. The LRLAT<2:0> bits select how long, if any, that the ‘A’ Power mode is active. Refer to Figure 27-4.
LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE A WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE) Single Segment Time Single Segment Time 32 kHz Clock Ladder Power Control ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F Segment Clock Segment Data Power Mode Power Mode A LRLAT<2:0> = 011 Power Mode B Power Mode A Power Mode B LRLAT<2:0> = 011 V2 V1 COM0-SEG0 V0 -V1 -V2 PIC16(L)F1946/47 DS41414D-page 346 FIGURE 27-5: 2010-2012 Micro
2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 27.
PIC16(L)F1946/47 27.6.1 CONTRAST CONTROL The LCD contrast control circuit consists of a seven-tap resistor ladder, controlled by the LCDCST bits. Refer to Figure 27-7. FIGURE 27-7: The contrast control circuit is used to decrease the output voltage of the signal source by a total of approximately 10%, when LCDCST = 111. Whenever the LCD module is inactive (LCDA = 0), the contrast control ladder will be turned off (open).
PIC16(L)F1946/47 27.7 LCD Multiplex Types 27.9 Pixel Control The LCD driver module can be configured into one of four multiplex types: The LCDDATAx registers contain bits which define the state of each pixel. Each bit defines one unique pixel. • • • • Register 27-6 shows the correlation of each bit in the LCDDATAx registers to the respective common and segment signals.
PIC16(L)F1946/47 TABLE 27-7: LCD Function LCD SEGMENT MAPPING WORKSHEET COM0 LCDDATAx Address COM1 LCD Segment LCDDATAx Address COM2 LCD Segment LCDDATAx Address COM3 LCD Segment LCDDATAx Address SEG0 LCDDATA0, 0 LCDDATA3, 0 LCDDATA6, 0 LCDDATA9, 0 SEG1 LCDDATA0, 1 LCDDATA3, 1 LCDDATA6, 1 LCDDATA9, 1 SEG2 LCDDATA0, 2 LCDDATA3, 2 LCDDATA6, 2 LCDDATA9, 2 SEG3 LCDDATA0, 3 LCDDATA3, 3 LCDDATA6, 3 LCDDATA9, 3 SEG4 LCDDATA0, 4 LCDDATA3, 4 LCDDATA6, 4 LCDDATA9, 4 SEG5 LCDDATA0, 5
PIC16(L)F1946/47 27.11 LCD Waveform Generation LCD waveforms are generated so that the net AC voltage across the dark pixel should be maximized and the net AC voltage across the clear pixel should be minimized. The net DC voltage across any pixel should be zero. The COM signal represents the time slice for each common, while the SEG contains the pixel data. The pixel signal (COM-SEG) will have no DC component and it can take only one of the two RMS values.
PIC16(L)F1946/47 FIGURE 27-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 COM0 pin COM1 V1 V0 V2 COM1 pin COM0 V1 V0 V2 V1 SEG0 pin V0 V2 V1 SEG1 pin SEG1 V2 SEG0 SEG2 SEG3 V0 V1 V0 COM0-SEG0 segment voltage (active) -V1 -V2 V2 V1 V0 COM0-SEG1 segment voltage (inactive) -V1 1 Frame -V2 1 Segment Time Note: 1 Frame = 2 single segment times. 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 27-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 COM1 V1 COM0 pin V0 COM0 V2 COM1 pin V1 V0 V2 SEG0 pin V1 SEG1 SEG0 SEG3 SEG2 V0 V2 SEG1 pin V1 V0 V2 V1 V0 COM0-SEG0 segment voltage (active) -V1 -V2 V2 V1 V0 COM0-SEG1 segment voltage (inactive) -V1 2 Frames -V2 1 Segment Time Note: 1 Frame = 2 single segment times. DS41414D-page 354 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 27-11: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 COM1 V2 COM0 pin V1 V0 V3 COM0 V2 COM1 pin V1 V0 V3 V2 SEG0 pin V1 V0 SEG1 SEG0 SEG2 SEG3 V3 V2 SEG1 pin V1 V0 V3 V2 V1 V0 COM0-SEG0 segment voltage (active) -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 segment voltage (inactive) -V1 1 Frame -V2 -V3 1 Segment Time Note: 1 Frame = 2 single segment times. 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 27-12: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 COM1 V2 COM0 pin V1 V0 V3 COM0 V2 COM1 pin V1 V0 V3 V2 SEG0 pin V1 V0 SEG1 SEG0 SEG2 SEG3 V3 V2 SEG1 pin V1 V0 V3 V2 V1 V0 COM0-SEG0 segment voltage (active) -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 segment voltage (inactive) -V1 2 Frames -V2 -V3 1 Segment Time Note: 1 Frame = 2 single segment times. DS41414D-page 356 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 27-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V2 COM0 pin V1 V0 V2 COM2 COM1 pin V1 V0 COM1 V2 COM0 COM2 pin V1 V0 V2 SEG0 and SEG2 pins V1 V0 V2 V1 V0 SEG0 SEG1 SEG2 SEG1 pin V2 V1 V0 COM0-SEG0 segment voltage (inactive) -V1 -V2 V2 V1 V0 COM0-SEG1 segment voltage (active) -V1 -V2 1 Frame 1 Segment Time Note: 1 Frame = 2 single segment times. 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 27-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V2 COM0 pin V1 V0 COM2 V2 COM1 pin V1 COM1 V0 COM0 V2 COM2 pin V1 V0 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 pin V2 SEG1 pin V1 V0 V2 V1 V0 COM0-SEG0 segment voltage (inactive) -V1 -V2 V2 V1 V0 COM0-SEG1 segment voltage (active) -V1 -V2 2 Frames 1 Segment Time Note: DS41414D-page 358 1 Frame = 2 single segment times. 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 27-15: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 V2 COM0 pin V1 V0 V3 COM2 V2 COM1 pin V1 COM1 V0 COM0 V3 V2 COM2 pin V1 V0 V3 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 and SEG2 pins V3 V2 SEG1 pin V1 V0 V3 V2 V1 V0 COM0-SEG0 segment voltage (inactive) -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 segment voltage (active) -V1 -V2 -V3 1 Frame 1 Segment Time Note: 1 Frame = 2 single segment times. 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 27-16: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 V2 COM0 pin V1 V0 V3 COM2 V2 COM1 pin V1 COM1 V0 COM0 V3 V2 COM2 pin V1 V0 V3 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 pin V3 V2 SEG1 pin V1 V0 V3 V2 V1 V0 COM0-SEG0 segment voltage (inactive) -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 segment voltage (active) -V1 -V2 -V3 2 Frames 1 Segment Time Note: DS41414D-page 360 1 Frame = 2 single segment times. 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 27-17: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 pin V3 V2 V1 V0 COM1 pin V3 V2 V1 V0 COM2 pin V3 V2 V1 V0 COM3 pin V3 V2 V1 V0 SEG0 pin V3 V2 V1 V0 SEG1 pin V3 V2 V1 V0 SEG0 SEG1 COM0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG0 segment voltage (active) COM0-SEG1 segment voltage (inactive) 1 Frame V3 V2 V1 V0 -V1 -V2 -V3 1 Segment Time Note: 1 Frame = 2 single segment times. 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 27-18: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM0 pin V3 V2 V1 V0 COM1 pin V3 V2 V1 V0 COM2 pin V3 V2 V1 V0 COM3 pin V3 V2 V1 V0 SEG0 pin V3 V2 V1 V0 SEG1 pin V3 V2 V1 V0 COM2 COM1 SEG0 SEG1 COM0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG0 segment voltage (active) COM0-SEG1 segment voltage (inactive) V3 V2 V1 V0 -V1 -V2 -V3 2 Frames 1 Segment Time Note: DS41414D-page 362 1 Frame = 2 single segment times. 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 27.12 LCD Interrupts The LCD module provides an interrupt in two cases. An interrupt when the LCD controller goes from active to inactive controller. An interrupt also provides unframe boundaries for Type B waveform. The LCD timing generation provides an interrupt that defines the LCD frame timing. 27.12.1 LCD INTERRUPT ON MODULE SHUTDOWN An LCD interrupt is generated when the module completes shutting down (LCDA goes from ‘1’ to ‘0’). 27.12.
PIC16(L)F1946/47 FIGURE 27-19: WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE (EXAMPLE – TYPE-B, NON-STATIC) LCD Interrupt Occurs Controller Accesses Next Frame Data COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 V3 V2 V1 V0 COM3 2 Frames TFINT Frame Boundary Frame Boundary TFWR Frame Boundary TFWR = TFRAME/2*(LMUX<1:0> + 1) + TCY/2 TFINT = (TFWR/2 – (2 TCY + 40 ns)) minimum = 1.5(TFRAME/4) – (2 TCY + 40 ns) (TFWR/2 – (1 TCY + 40 ns)) maximum = 1.
PIC16(L)F1946/47 27.13 Operation During Sleep The LCD module can operate during Sleep. The selection is controlled by bit SLPEN of the LCDCON register. Setting the SLPEN bit allows the LCD module to go to Sleep. Clearing the SLPEN bit allows the module to continue to operate during Sleep. If a SLEEP instruction is executed and SLPEN = 1, the LCD module will cease all functions and go into a very low-current Consumption mode.
PIC16(L)F1946/47 FIGURE 27-20: SLEEP ENTRY/EXIT WHEN SLPEN = 1 V3 V2 V1 COM0 V0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 SEG0 2 Frames SLEEP Instruction Execution DS41414D-page 366 Wake-up 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 27.14 Configuring the LCD Module 27.16 LCD Current Consumption The following is the sequence of steps to configure the LCD module. When using the LCD module the current consumption consists of the following three factors: 1. • Oscillator Selection • LCD Bias Source • Capacitance of the LCD segments 2. 3. 4. 5. 6. 7. Select the frame clock prescale using bits LP<3:0> of the LCDPS register. Configure the appropriate pins to function as segment drivers using the LCDSEn registers.
PIC16(L)F1946/47 TABLE 27-9: SUMMARY OF REGISTERS ASSOCIATED WITH LCD OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92 LCDCON LCDEN SLPEN WERR — Name LCDCST CS<1:0> LMUX<1:0> — — — — — LCDDATA0 SEG7 COM0 SEG6 COM0 SEG5 COM0 SEG4 COM0 SEG3 COM0 SEG2 COM0 SEG1 COM0 SEG0 COM0 341 LCDDATA1 SEG15 COM0 SEG14 COM0 SEG13 COM0 SEG12 COM0 SEG11 COM0 SEG10 COM0 SEG9 COM0 SEG8 COM0 341
PIC16(L)F1946/47 TABLE 27-9: Name SUMMARY OF REGISTERS ASSOCIATED WITH LCD OPERATION (CONTINUED) Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCDDATA22 SEG39 COM3 SEG38 COM3 SEG37 COM3 SEG36 COM3 SEG35 COM3 SEG34 COM3 SEG33 COM3 SEG32 COM3 341 LCDDATA23 — — SEG45 COM3 SEG44 COM3 SEG43 COM3 SEG42 COM3 SEG41 COM3 SEG40 COM3 341 WFT BIASMD LCDA WA LCDIRE LCDIRS LCDIRI — VLCD3PE VLCD2PE — 339 LCDPS LCDREF LCDRL LRLAP<1:0> LP<3:0> LRLBP<1:0> — LC
PIC16(L)F1946/47 NOTES: DS41414D-page 370 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 28.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications.
PIC16(L)F1946/47 28.2 Low-Voltage Programming Entry Mode FIGURE 28-2: The Low-Voltage Programming Entry mode allows the PIC® Flash MCUs to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Words is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. VDD Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2.
PIC16(L)F1946/47 For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 28-4 for more information.
PIC16(L)F1946/47 NOTES: DS41414D-page 374 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 29.0 INSTRUCTION SET SUMMARY 29.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.
PIC16(L)F1946/47 FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal)
PIC16(L)F1946/47 TABLE 29-3: PIC16(L)F1946/47 INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f
PIC16(L)F1946/47 TABLE 29-3: PIC16(L)F1946/47 ENHANCED INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation Load OPTION
PIC16(L)F1946/47 29.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: (W) .AND. (k) (W) Operation: FSR(n) + k FSR(n) Status Affected: Z Status Affected: None Description: Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair.
PIC16(L)F1946/47 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
PIC16(L)F1946/47 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<6:3>) PC<14:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>.
PIC16(L)F1946/47 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16(L)F1946/47 LSLF Logical Left Shift MOVF Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) f {,d} Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16(L)F1946/47 MOVIW Move INDFn to W MOVLP Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Syntax: [ label ] MOVLP k Operands: 0 k 127 Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrement
PIC16(L)F1946/47 MOVWI Move W to INDFn NOP No Operation Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Syntax: [ label ] Operands: None n [0,1] mm [00,01, 10, 11] -32 k 31 Description: No operation.
PIC16(L)F1946/47 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] Syntax: [ label ] None RETFIE RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC16(L)F1946/47 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’.
PIC16(L)F1946/47 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC16(L)F1946/47 30.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC16F1946/47 ........................................................................ -0.
PIC16(L)F1946/47 PIC16F1946/47 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C FIGURE 30-1: VDD (V) 5.5 2.5 1.8 4 0 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 30-1 for each Oscillator mode’s supported frequencies. PIC16LF1946/47 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C VDD (V) FIGURE 30-2: 3.6 2.5 1.
PIC16(L)F1946/47 FIGURE 30-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% Temperature (°C) 85 ± 3% 60 ± 2% 25 0 -20 -40 1.8 ± 5% 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 30.1 DC Characteristics: PIC16(L)F1946/47-I/E (Industrial, Extended) PIC16LF1946/47 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1946/47 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param. No. D001 Sym. VDD D001 D002* VDR D002A* D002B* VPOR* VPORR* Characteristic Min.
PIC16(L)F1946/47 FIGURE 30-4: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 30.2 DC Characteristics: PIC16(L)F1946/47-I/E (Industrial, Extended) PIC16LF1946/47 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1946/47 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max.
PIC16(L)F1946/47 30.2 DC Characteristics: PIC16(L)F1946/47-I/E (Industrial, Extended) (Continued) PIC16LF1946/47 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1946/47 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Max. Units Conditions Min. Typ† — 15 40 A 1.
PIC16(L)F1946/47 30.2 DC Characteristics: PIC16(L)F1946/47-I/E (Industrial, Extended) (Continued) PIC16LF1946/47 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1946/47 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max.
PIC16(L)F1946/47 30.3 DC Characteristics: PIC16(L)F1946/47-I/E (Power-Down) PIC16LF1946/47 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1946/47 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Power-down Base Current Min. Typ† Max. +85°C Max.
PIC16(L)F1946/47 30.3 DC Characteristics: PIC16(L)F1946/47-I/E (Power-Down) (Continued) PIC16LF1946/47 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1946/47 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Typ† Max. +85°C Max. +125°C Units — 0.1 5.0 8.0 — 0.
PIC16(L)F1946/47 30.3 DC Characteristics: PIC16(L)F1946/47-I/E (Power-Down) (Continued) PIC16LF1946/47 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1946/47 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Max. +85°C Max. +125°C Units — 80 — — A 1.
PIC16(L)F1946/47 30.4 DC Characteristics: PIC16(L)F1946/47-I/E DC CHARACTERISTICS Param No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ† Max. Units Conditions Input Low Voltage I/O PORT: D032 — — 0.8 V 4.5V VDD 5.5V — — 0.15 VDD V 1.8V VDD 4.5V with Schmitt Trigger buffer — — 0.2 VDD V 2.0V VDD 5.5V with I2C™ levels — — 0.
PIC16(L)F1946/47 30.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA D112 VPBE VDD for Bulk Erase 2.
PIC16(L)F1946/47 30.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. TH01 Sym. Characteristic Typ. Units JA Thermal Resistance Junction to Ambient 48.3 C/W 28 C/W 64-pin QFN package 26.1 C/W 64-pin TQFP package 0.
PIC16(L)F1946/47 30.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16(L)F1946/47 30.8 AC Characteristics: PIC16(L)F1946/47-I/E FIGURE 30-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 30-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. OS01 Sym.
PIC16(L)F1946/47 TABLE 30-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS08 Sym. HFOSC OS08A MFOSC Characteristic Freq. Tolerance Min. Typ† Max. Units Conditions 2% — 16.0 — MHz 0°C TA +60°C, VDD 2.5V 3% — 16.0 — MHz 60°C TA +85°C, VDD 2.5V 5% — 16.0 — MHz -40°C TA +125°C 2% — 500 — kHz 0°C TA +60°C, VDD 2.5V 3% — 500 — kHz 60°C TA +85°C, VDD 2.
PIC16(L)F1946/47 TABLE 30-4: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS11 OS12 Sym. TosH2ckL Characteristic Min. Typ† Max. Units Conditions — — 70 ns VDD = 3.3-5.0V — — 72 ns VDD = 3.3-5.
PIC16(L)F1946/47 FIGURE 30-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset (due to BOR) 33(1) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2 ms delay if PWRTE = 0 and VREGEN = 1. 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 TABLE 30-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max.
PIC16(L)F1946/47 TABLE 30-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. TT0H 40* Characteristic T0CKI High Pulse Width Min. No Prescaler TT0L T0CKI Low Pulse Width No Prescaler TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler — — ns — — ns 0.5 TCY + 20 — — ns 10 — — ns Greater of: 20 or TCY + 40 N — — ns 0.
PIC16(L)F1946/47 TABLE 30-8: PIC16(L)F1946/47 A/D CONVERTER (ADC) CHARACTERISTICS(1,2,3): Standard Operating Conditions (unless otherwise stated) Operating temperature TA 25°C Param Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 10 AD02 EIL Integral Error — — ±1.7 AD03 EDL Differential Error — — ±1 AD04 EOFF Offset Error — — ±2.5 LSb VREF = 3.0V AD05 EGN LSb VREF = 3.
PIC16(L)F1946/47 FIGURE 30-12: PIC16(L)F1946/47 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 1 TCY (TOSC/2(1)) AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO Sample DONE Sampling Stopped AD132 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
PIC16(L)F1946/47 TABLE 30-10: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). Param No. Sym. Characteristics Min. Typ. Max. Units Comments — ±7.
PIC16(L)F1946/47 TABLE 30-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Symbol Characteristic Min. Max. Units — 80 ns US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid 3.0-5.5V 1.8-5.5V — 100 ns US121 TCKRF Clock out rise time and fall time (Master mode) 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns US122 TDTRF Data-out rise time and fall time 3.0-5.
PIC16(L)F1946/47 FIGURE 30-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP70 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 30-5 for load conditions.
PIC16(L)F1946/47 FIGURE 30-18: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 30-5 for load conditions.
PIC16(L)F1946/47 TABLE 30-14: SPI MODE REQUIREMENTS Param No. Symbol Characteristic SP70* TSSL2SCH, SS to SCK or SCK input TSSL2SCL Min. Typ† Max. Units Conditions TCY — — ns SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns 100 — — ns 100 — — ns 3.0-5.5V — 10 25 ns 1.8-5.
PIC16(L)F1946/47 TABLE 30-15: I2C™ BUS START/STOP BITS REQUIREMENTS Param No. Symbol Characteristic SP90* TSU:STA Start condition SP91* THD:STA SP92* TSU:STO SP93 THD:STO Stop condition Typ 4700 — Max. Units — Setup time 400 kHz mode 600 — — Start condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Stop condition 100 kHz mode 4700 — — Setup time Hold time * 100 kHz mode Min.
PIC16(L)F1946/47 TABLE 30-16: I2C™ BUS DATA REQUIREMENTS Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSP module SP101* TLOW Clock low time 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1.
PIC16(L)F1946/47 TABLE 30-17: CAP SENSE OSCILLATOR SPECIFICATIONS Param. No. Symbol CS01* ISRC CS02* ISNK Characteristic Current Source Current Sink Min. Typ† Max. Units High — -8 — A Medium — -1.5 — A Low — -0.3 — A High — 7.5 — A Medium — 1.5 — A — 0.25 — A — 0.8 — V — 0.
PIC16(L)F1946/47 NOTES: DS41414D-page 420 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 31.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC16(L)F1946/47 FIGURE 31-1: IDD, LP OSCILLATOR MODE, FOSC = 32 kHz, PIC16LF1946/47 ONLY 14 Max. Max: 85°C + 3 Typical: 25°C 12 IDD (µA) 10 8 Typical 6 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IDD, LP OSCILLATOR MODE, FOSC = 32 kHz, PIC16F1946/47 ONLY FIGURE 31-2: 60 Max: 85°C + 3 Typical: 25°C Max. 50 IDD (µA) 40 Typical 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS41414D-page 422 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 31-3: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16LF1946/47 ONLY 450 4 MHz XT Typical: 25°C 400 350 4 MHz EXTRC IDD (µA) 300 250 200 150 1 MHz XT 100 50 1 MHz EXTRC 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-4: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16LF1946/47 ONLY 550 Max: 85°C + 3 500 4 MHz XT 450 400 4 MHz EXTRC IDD (µA) 350 300 250 200 150 1 MHz XT 100 50 1 MHz EXTRC 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.
PIC16(L)F1946/47 FIGURE 31-5: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16F1946/47 ONLY 500 Typical: 25°C 4 MHz XT 4 MHz EXTRC 400 IDD (µA) 300 1 MHz XT 200 1 MHz EXTRC 100 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 31-6: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16F1946/47 ONLY 600 4 MHz XT Max: 85°C + 3 500 4 MHz EXTRC IDD (µA) 400 300 1 MHz XT 200 1 MHz EXTRC 100 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1946/47 FIGURE 31-7: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 32 kHz, PIC16LF1946/47 ONLY 12 Max: 85°C + 3 Typical: 25°C 10 Max. IDD (µA) 8 6 Typical 4 2 0 1.6 1.8 FIGURE 31-8: 2.0 2.2 2.4 2.6 2.8 VDD (V) 3.0 3.2 3.4 3.6 3.8 IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 32 kHz, PIC16F1946/47 ONLY 50 Max: 85°C + 3 Typical: 25°C 45 Max. 40 IDD (µA) 35 Typical 30 25 20 15 10 5 0 1.5 2.0 2.5 2010-2012 Microchip Technology Inc. 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.
PIC16(L)F1946/47 FIGURE 31-9: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz, PIC16LF1946/47 ONLY 60 Max. Max: 85°C + 3 Typical: 25°C 50 IDD (µA) 40 30 20 Typical 10 0 1.6 1.8 FIGURE 31-10: 2.0 2.2 2.4 2.6 2.8 VDD (V) 3.0 3.2 3.4 3.6 3.8 IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz, PIC16F1946/47 ONLY 90 Max. Max: 85°C + 3 Typical: 25°C 80 70 IDD (µA) 60 Typical 50 40 30 20 10 0 1.5 DS41414D-page 426 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.
PIC16(L)F1946/47 FIGURE 31-11: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16LF1946/47 ONLY 450 Typical: 25°C 400 4 MHz 350 IDD (µA) 300 250 200 150 100 1 MHz 50 0 1.6 1.8 FIGURE 31-12: 2.0 2.2 2.4 2.6 2.8 VDD (V) 3.0 3.2 3.4 3.6 3.8 IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16LF1946/47 ONLY 500 Max: 85°C + 3 450 4 MHz 400 IDD (µA) 350 300 250 200 150 1 MHz 100 50 0 1.6 1.8 2.0 2010-2012 Microchip Technology Inc. 2.2 2.4 2.6 2.8 VDD (V) 3.0 3.2 3.4 3.6 3.
PIC16(L)F1946/47 FIGURE 31-13: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16F1946/47 ONLY 450 Typical: 25°C 400 4 MHz 350 IDD (µA) 300 250 200 1 MHz 150 100 50 0 1.5 2.0 FIGURE 31-14: 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.0 IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16F1946/47 ONLY 500 Max: 85°C + 3 450 4 MHz 400 IDD (µA) 350 300 250 1 MHz 200 150 100 50 0 1.5 DS41414D-page 428 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.
PIC16(L)F1946/47 FIGURE 31-15: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC16LF1946/47 ONLY 3.5 Typical: 25°C 3.0 32 MHz (PLL) 2.5 IDD (µA) 2.0 16 MHz 1.5 1.0 8 MHz 0.5 0.0 1.6 FIGURE 31-16: 1.8 2.0 2.2 2.4 2.6 2.8 VDD (V) 3.0 3.2 3.4 3.6 3.8 IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC16LF1946/47 ONLY 4.0 Max: 85°C + 3 3.5 3.0 32 MHz (PLL) 2.5 IDD (µA) 2.0 16 MHz 1.5 1.0 8 MHz 0.5 0.0 1.6 1.8 2.0 2010-2012 Microchip Technology Inc. 2.2 2.4 2.6 2.8 VDD (V) 3.
PIC16(L)F1946/47 FIGURE 31-17: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC16F1946/47 ONLY 3.5 Typical: 25°C 3.0 32 MHz (PLL) IDD (µA) 2.5 2.0 16 MHz 1.5 8 MHz 1.0 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.0 IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC16F1946/47 ONLY FIGURE 31-18: 3.5 Max: 85°C + 3 3.0 32 MHz (PLL) IDD (µA) 2.5 2.0 16 MHz 1.5 8 MHz 1.0 0.5 0.0 1.5 DS41414D-page 430 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.
PIC16(L)F1946/47 FIGURE 31-19: IDD, LFINTOSC MODE, FOSC = 32 kHz, PIC16LF1946/47 ONLY 12 Max: 85°C + 3 Typical: 25°C 10 Max. IDD (µA) 8 6 Typical 4 2 0 1.6 1.8 FIGURE 31-20: 2.0 2.2 2.4 2.6 2.8 VDD (V) 3.0 3.2 3.4 3.6 3.8 IDD, LFINTOSC MODE, FOSC = 32 kHz, PIC16F1946/47 ONLY 50 Max: 85°C + 3 Typical: 25°C 45 Max. 40 IDD (µA) 35 Typical 30 25 20 15 10 5 0 1.5 2.0 2.5 2010-2012 Microchip Technology Inc. 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.
PIC16(L)F1946/47 FIGURE 31-21: IDD, MFINTOSC MODE, FOSC = 500 kHz, PIC16LF1946/47 ONLY 180 Max: 85°C + 3 Typical: 25°C 160 Max. 140 IDD (µA) 120 Typical 100 80 60 40 20 0 1.6 1.8 FIGURE 31-22: 2.0 2.2 2.4 2.6 2.8 VDD (V) 3.0 3.2 3.4 3.6 3.8 IDD, MFINTOSC MODE, FOSC = 500 kHz, PIC16F1946/47 ONLY 300 Max: 85°C + 3 Typical: 25°C 250 Max. Typical IDD (µA) 200 150 100 50 0 1.5 DS41414D-page 432 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.
PIC16(L)F1946/47 FIGURE 31-23: IDD TYPICAL, HFINTOSC MODE, PIC16LF1946/47 ONLY 4000 Typical: 25°C 32 MHz (PLL) 3500 IDD (µA) 3000 2500 2000 16 MHz 1500 8 MHz 1000 500 4 MHz 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-24: IDD MAXIMUM, HFINTOSC MODE, PIC16LF1946/47 ONLY 4500 Max: 85°C + 3 4000 32 MHz (PLL) 3500 IDD (µA) 3000 2500 2000 16 MHz 1500 8 MHz 1000 500 4 MHz 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC16(L)F1946/47 FIGURE 31-25: IDD TYPICAL, HFINTOSC MODE, PIC16F1946/47 ONLY 3500 Typical: 25°C 3000 32 MHz (PLL) IDD (µA) 2500 2000 16 MHz 1500 8 MHz 1000 4 MHz 500 0 1.5 2.0 FIGURE 31-26: 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.0 5.5 6.0 IDD MAXIMUM, HFINTOSC MODE, PIC16F1946/47 ONLY 4000 32 MHz (PLL) Max: 85°C + 3 3500 3000 IDD (µA) 2500 16 MHz 2000 1500 8 MHz 1000 4 MHz 500 0 1.5 DS41414D-page 434 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.
PIC16(L)F1946/47 FIGURE 31-27: IDD TYPICAL, HS OSCILLATOR, PIC16LF1946/47 ONLY 4500 Max: 85°C + 3 Typical: 25°C 4000 32 MHz (PLL) 3500 IDD (µA) 3000 2500 20 MHz 2000 1500 8 MHz 1000 500 0 1.6 1.8 FIGURE 31-28: 2.0 2.2 2.4 2.6 2.8 VDD (V) 3.0 3.2 3.4 3.6 3.8 3.6 3.8 IDD MAXIMUM, HS OSCILLATOR, PIC16LF1946/47 ONLY 5000 Max: 85°C + 3 Typical: 25°C 4500 32 MHz (PLL) 4000 3500 IDD (µA) 3000 2500 20 MHz 2000 1500 8 MHz 1000 500 0 1.6 1.8 2.
PIC16(L)F1946/47 FIGURE 31-29: IDD TYPICAL, HS OSCILLATOR, PIC16F1946/47 ONLY 3500 Typical: 25°C 3000 32 MHz (PLL) 2500 20 MHz IDD (µA) 2000 1500 8 MHz 1000 500 0 1.5 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.0 5.5 6.0 IDD MAXIMUM, HS OSCILLATOR, PIC16F1946/47 ONLY FIGURE 31-30: 3500 Max: 85°C + 3 3000 32 MHz (PLL) IDD (µA) 2500 20 MHz 2000 1500 8 MHz 1000 500 0 1.5 DS41414D-page 436 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 31-31: IPD BASE, PIC16LF1946/47 ONLY 1200 Max. Max: 85°C + 3 Typical: 25°C 1000 IPD (nA (nA) 800 600 400 200 Typical 0 1.6 FIGURE 31-32: 1.8 2.0 2.2 2.4 2.6 2.8 VDD (V) 3.0 3.2 3.4 3.6 3.8 IPD BASE, PIC16F1946/47 ONLY 45 Max. Max: 85°C + 3 Typical: 25°C 40 35 IPD (µA) µA) 30 Typical 25 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 31-33: IPD, WATCHDOG TIMER (WDT), PIC16LF1946/47 ONLY 2500 Max: 85°C + 3 Typical: 25°C IPD D (nA) 2000 1500 Max. 1000 Typical 500 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 VDD (V) 3.0 3.2 3.4 3.6 3.8 IPD, WATCHDOG TIMER (WDT), PIC16F1946/47 ONLY FIGURE 31-34: 45 Max: 85°C + 3 Typical: 25°C 40 Max. 35 IPD (µA (µA) 30 Typical 25 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS41414D-page 438 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 31-35: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16LF1946/47 ONLY 14 Max: 85°C + 3 Typical: 25°C 13 Max. 12 11 IPD (µA) 10 Typical 9 8 7 6 5 4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-36: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16F1946/47 ONLY 120 Max: 85°C + 3 Typical: 25°C 100 Max. Typical IPD (µA (µA) 80 60 40 20 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 31-37: IPD, BROWN-OUT RESET (BOR), PIC16LF1946/47 ONLY 12 Max: 85°C + 3 Typical: 25°C 11 M Max. IPD (µ (µA) 10 9 Typical 8 7 6 5 4 1.8 2.0 FIGURE 31-38: 2.2 2.4 2.6 2.8 VDD (V) 3.0 3.2 3.4 3.6 3.8 5.5 6.0 IPD, BROWN-OUT RESET (BOR), PIC16F1946/47 ONLY 50 Max: 85°C + 3 Typical: 25°C 45 Max. 40 35 Typical IPD (µA) 30 25 20 15 10 5 0 1.5 DS41414D-page 440 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 31-39: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC16LF1946/47 ONLY 14 Max: 85°C + 3 Typical: 25°C 12 10 IPD (µA (µA) Max. 8 6 4 Typical 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-40: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC16F1946/47 ONLY 60 Max: 85°C + 3 Typical: 25°C 50 Max. IPD (µA (µA) 40 Typical 30 20 10 0 1.5 2.0 2.5 2010-2012 Microchip Technology Inc. 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.
PIC16(L)F1946/47 FIGURE 31-41: IPD, CAPACITIVE SENSING (CPS) MODULE, LOW-CURRENT RANGE, CPSRM = 0, PIC16LF1946/47 ONLY 8 M Max. Max: 85°C + 3 Typical: 25°C 7 6 IPD (µA (µA) 5 4 Typical 3 2 1 0 1.6 1.8 FIGURE 31-42: 2.0 2.2 2.4 2.6 2.8 VDD (V) 3.0 3.2 3.4 3.6 3.8 IPD, CAPACITIVE SENSING (CPS) MODULE, LOW-CURRENT RANGE, CPSRM = 0, PIC16F1946/47 ONLY 45 Max: 85°C + 3 Typical: 25°C 40 Max. 35 30 IPD (µA (µA) Typical 25 20 15 10 5 0 1.5 DS41414D-page 442 2.0 2.5 3.0 3.5 4.
PIC16(L)F1946/47 FIGURE 31-43: IPD, CAPACITIVE SENSING (CPS) MODULE, MEDIUM-CURRENT RANGE, CPSRM = 0, PIC16LF1946/47 ONLY 14 Max: 85°C + 3 M 3 Typical: 25°C 12 Max. IPD (µA) 10 8 Typical 6 4 2 0 1.6 1.8 FIGURE 31-44: 2.0 2.2 2.4 2.6 2.8 VDD (V) 3.0 3.2 3.4 3.6 3.8 IPD, CAPACITIVE SENSING (CPS) MODULE, MEDIUM-CURRENT RANGE, CPSRM = 0, PIC16F1946/47 ONLY 60 Max: 85°C + 3 M 3 Typical: 25°C 50 Max. IPD (µA (µA) 40 Typical yp 30 20 10 0 1.5 2.0 2.
PIC16(L)F1946/47 FIGURE 31-45: IPD, CAPACITIVE SENSING (CPS) MODULE, HIGH-CURRENT RANGE, CPSRM = 0, PIC16LF1946/47 ONLY 70 Max: 85°C + 3 Typical: 25°C 60 Max. IPD (µA) 50 40 Typical 30 20 10 0 1.6 1.8 FIGURE 31-46: 2.0 2.2 2.4 2.6 2.8 VDD (V) 3.0 3.2 3.4 3.6 3.8 IPD, CAPACITIVE SENSING (CPS) MODULE, HIGH-CURRENT RANGE, CPSRM = 0, PIC16F1946/47 ONLY 140 Max: 85°C + 3 Typical: 25°C 120 Max. IPD (µA) 100 80 Typical 60 40 20 0 1.5 DS41414D-page 444 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.
PIC16(L)F1946/47 FIGURE 31-47: IPD, COMPARATOR, LOW-POWER MODE, PIC16LF1946/47 ONLY 30 Max: 85°C + 3 Typical: 25°C Max Max. 25 IPD (µ (µA) 20 Typical 15 10 5 0 1.6 1.8 FIGURE 31-48: 2.0 2.2 2.4 2.6 2.8 VDD (V) 3.0 3.2 3.4 3.6 3.8 IPD, COMPARATOR, LOW-POWER MODE, PIC16F1946/47 ONLY 60 Max: 85°C + 3 Typical: 25°C 50 Max. IPD (µA (µA) 40 Typical 30 20 10 0 1.5 2.0 2.5 2010-2012 Microchip Technology Inc. 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.
PIC16(L)F1946/47 FIGURE 31-49: IPD, COMPARATOR, HIGH-POWER MODE, PIC16LF1946/47 ONLY 60 Max: 85°C + 3 M 3 Typical: 25°C 50 Max. IPD (µA (µA) 40 Typical 30 20 10 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-50: IPD, COMPARATOR, HIGH-POWER MODE, PIC16F1946/47 ONLY 80 Max: 85°C + 3 Typical: 25°C 70 Max. 60 IPD (µA) 50 Typical 40 30 20 10 0 1.5 DS41414D-page 446 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.0 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 31-51: VOH VS. IOH OVER TEMPERATURE, VDD = 5.0V, PIC16F1946/47 ONLY 6 Graph represents 3 Limits 5 VOH (V) 4 -40°C 3 125°C 2 Typical 1 0 -30 FIGURE 31-52: -25 -20 -15 IOH (mA) -10 -5 0 VOL VS. IOL OVER TEMPERATURE, VDD = 5.0V, PIC16F1946/47 ONLY 5 Graph represents 3 Limits VOL (V) 4 3 -40°C Typical 2 125°C 1 0 0 10 20 30 40 50 60 70 80 IOL (mA) 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 31-53: VOH VS. IOH OVER TEMPERATURE, VDD = 3.0V 3.5 Graph represents 3 Limits 3.0 VOH (V) 2.5 2.0 1.5 125°C Typical 1.0 -40°C 0.5 0.0 -14 -12 -10 -8 -6 -4 -2 0 IOH (mA) FIGURE 31-54: VOL VS. IOL OVER TEMPERATURE, VDD = 3.0V 3.0 Graph represents 3 Limits 2.5 VOL (V) 2.0 -40°C Typical 1.5 125°C 1.0 0.5 0.0 0 DS41414D-page 448 5 10 15 IOL (mA) 20 25 30 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 31-55: VOH VS. IOH OVER TEMPERATURE, VDD = 1.8V 2.0 Graph represents 3 Limits 1.8 1.6 VOH (V) 1.4 1.2 125°C 1.0 0.8 Typical -40°C 0.6 0.4 0.2 0.0 -4.0 FIGURE 31-56: -3.5 -3.0 -2.5 -2.0 IOH (mA) -1.5 -1.0 -0.5 0.0 VOL VS. IOL OVER TEMPERATURE, VDD = 1.8V 1.8 Graph represents 3 Limits 1.6 1.4 Vol (V) 1.2 1 125°C Typical 0.8 -40°C 0.6 0.4 0.2 0 0 1 2 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 31-57: BROWN-OUT RESET VOLTAGE, BORV = 1 2.10 Max: Typical + 3 Min: Typical - 3 2.05 2.00 Voltage (V) Max. 1.95 1.90 Min. 1.85 1.80 1.75 1.70 -60 FIGURE 31-58: -40 -20 0 20 40 60 Temperature (°C) 80 100 120 140 BROWN-OUT RESET HYSTERESIS, BORV = 1 70 Max. 60 Voltage (mV) 50 Typical 40 30 Min.
PIC16(L)F1946/47 FIGURE 31-59: BROWN-OUT RESET VOLTAGE, BORV = 0 2.90 2.85 Max: Typical + 3 Min: Typical - 3 2.80 Max. Voltage (V) 2.75 2.70 2.65 Min. 2.60 2.55 2.50 2.45 2.40 -60 FIGURE 31-60: -40 -20 0 20 40 60 Temperature (°C) 80 100 120 140 BROWN-OUT RESET HYSTERESIS, BORV = 0 90 80 Max. 70 Voltage (mV) 60 50 Typical 40 30 20 Max: Typical + 3 Typical: 25°C Min: Typical - 3 Min. 10 0 -60 -40 -20 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 31-61: COMPARATOR HYSTERESIS, HIGH-POWER MODE 120 Max: Typical + 3 Typical: 25°C Min: Typical - 3 Hysteresis (mV) 100 Max. 80 Typical 60 40 Min. 20 0 1.5 FIGURE 31-62: 2 2.5 3 3.5 4 VDD (V) 4.5 5 5.5 6 COMPARATOR HYSTERESIS, LOW-POWER MODE 25 Max: Typical + 3 Typical: 25°C Min: Typical - 3 Hysteresis (mV) 20 Max. 15 Typical 10 Min. 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) DS41414D-page 452 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 FIGURE 31-63: COMPARATOR RESPONSE TIME, HIGH-POWER MODE 390 Max: Typical + 3 Typical: 25°C 340 Time (nS) 290 240 Max. 190 Typical 140 90 1.5 FIGURE 31-64: 2 2.5 3 3.5 4 VDD (V) 4.5 5 5.5 6 COMPARATOR RESPONSE TIME OVER TEMPERATURE, HIGH-POWER MODE 260 Graph represents 3 Limits 240 Time (nS) 220 200 180 125°C 160 Typical -40°C 140 1.5 2 2010-2012 Microchip Technology Inc. 2.5 3 3.5 4 VDD (V) 4.5 5 5.
PIC16(L)F1946/47 FIGURE 31-65: COMPARATOR INPUT OFFSET AT 25°C, HIGH-POWER MODE, PIC16F1946/47 ONLY 60 40 Offset Voltage (V) Max. 20 Typical 0 Min. -20 Max: Typical + 3 Typical: 25°C Min: Typical - 3 -40 -60 0 DS41414D-page 454 1 2 3 Common Mode Voltage (V) 4 5 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 32.
PIC16(L)F1946/47 32.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 32.
PIC16(L)F1946/47 32.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16(L)F1946/47 32.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 32.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC16(L)F1946/47 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 64-Lead QFN (9x9x0.9 mm) PIN 1 PIN 1 XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC16F1947 -I/MR e3 1110017 64-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC16F1947 -I/PT e3 1110017 Legend: XX...
PIC16(L)F1946/47 33.2 Package Details The following sections give the technical details of the packages. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41414D-page 460 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 E e E1 N b NOTE 1 123 NOTE 2 α A φ c A2 β A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± )RRW /HQJWK
PIC16(L)F1946/47 /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 NOTES: DS41414D-page 464 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (3/2010) APPENDIX B: MIGRATING FROM OTHER PIC® DEVICES This shows a comparison of features in the migration from the PIC16F917 device to the PIC16F1946 family of devices. Original release. Revision B (9/2010) Updated with current electrical specifications; Added Temperature Indicator Module section; Other minor corrections.
PIC16(L)F1946/47 NOTES: DS41414D-page 466 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 INDEX A A/D Specifications............................................................ 410 Absolute Maximum Ratings (PIC16F/LF1946/47) ............ 389 AC Characteristics Industrial and Extended ............................................ 404 Load Conditions ........................................................ 403 ACKSTAT ......................................................................... 278 ACKSTAT Status Flag ...................................................... 278 ADC .....
PIC16(L)F1946/47 PWM Period .............................................................. 221 PWM Setup ............................................................... 221 CCP1CON Register ...................................................... 38, 39 CCPR1H Register ......................................................... 38, 39 CCPR1L Register.......................................................... 38, 39 CCPTMRS0 Register ........................................................ 239 CCPTMRS1 Register .
PIC16(L)F1946/47 Baud Rates, Asynchronous Modes .................. 311 Formulas ........................................................... 310 High Baud Rate Select (BRGH Bit) .................. 310 Clock polarity Synchronous Mode ........................................... 318 Data Polarity Asynchronous Receive ..................................... 302 Data polarity Asynchronous Transmit .................................... 299 Synchronous Mode ...........................................
PIC16(L)F1946/47 INTOSC Specifications ..................................................... 405 IOCBF Register................................................................. 155 IOCBN Register ................................................................ 155 IOCBP Register................................................................. 155 L LATA Register................................................................... 131 LATB Register..............................................................
PIC16(L)F1946/47 PORTC Associated Registers ................................................ 138 LATC Register ............................................................ 35 Pin Functions and Output Priorities .......................... 136 PORTC Register ......................................................... 33 Specifications............................................................ 406 PORTC Register ............................................................... 137 PORTD ..........................
PIC16(L)F1946/47 PIR4 (Peripheral Interrupt Request 4) ................ 96, 100 PORTA...................................................................... 131 PORTB...................................................................... 134 PORTC ..................................................................... 137 PORTD ..................................................................... 140 PORTE...................................................................... 143 PORTF ..........................
PIC16(L)F1946/47 Asynchronous Transmission (Back to Back) ............ 301 Auto Wake-up Bit (WUE) During Normal Operation . 316 Auto Wake-up Bit (WUE) During Sleep .................... 316 Automatic Baud Rate Calculator............................... 315 Baud Rate Generator with Clock Arbitration ............. 275 BRG Reset Due to SDA Arbitration During Start Condition........................................................... 286 Brown-out Reset (BOR) ............................................
PIC16(L)F1946/47 NOTES: DS41414D-page 474 2010-2012 Microchip Technology Inc.
PIC16(L)F1946/47 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16(L)F1946/47 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16(L)F1946/47 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO.
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