Datasheet

PIC16(L)F1946/1947
DS41414D-page 46  2010-2012 Microchip Technology Inc.
Banks 16-30
x00h/
x80h
(2)
INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
x00h/
x81h
(2)
INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
x02h/
x82h
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x03h/
x83h
(2)
STATUS — — —TOPD ZDCC---1 1000 ---q quuu
x04h/
x84h
(2)
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x05h/
x85h
(2)
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x06h/
x86h
(2)
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x07h/
x87h
(2)
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x08h/
x88h
(2)
BSR — — — BSR<4:0> ---0 0000 ---0 0000
x09h/
x89h
(2)
WREG Working Register 0000 0000 uuuu uuuu
x0Ah/
x8Ah
(1),(2)
PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
x0Bh/
x8Bh
(2)
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
x0Ch/
x8Ch
—
x1Fh/
x9Fh
— Unimplemented — —
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other
Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.