Datasheet

 2010-2012 Microchip Technology Inc. DS41414D-page 277
PIC16(L)F1946/47
24.6.5 I
2
C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
of the SSPxCON2 register is programmed high and the
Master state machine is no longer active. When the
RSEN bit is set, the SCLx pin is asserted low. When the
SCLx pin is sampled low, the Baud Rate Generator is
loaded and begins counting. The SDAx pin is released
(brought high) for one Baud Rate Generator count
(T
BRG). When the Baud Rate Generator times out, if
SDAx is sampled high, the SCLx pin will be deasserted
(brought high). When SCLx is sampled high, the Baud
Rate Generator is reloaded and begins counting. SDAx
and SCLx must be sampled high for one T
BRG. This
action is then followed by assertion of the SDAx pin
(SDAx = 0) for one T
BRG while SCLx is high. SCLx is
asserted low. Following this, the RSEN bit of the
SSPxCON2 register will be automatically cleared and
the Baud Rate Generator will not be reloaded, leaving
the SDAx pin held low. As soon as a Start condition is
detected on the SDAx and SCLx pins, the S bit of the
SSPxSTAT register will be set. The SSPxIF bit will not
be set until the Baud Rate Generator has timed out.
FIGURE 24-27: REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDAx is sampled low when SCLx
goes from low-to-high.
• SCLx goes low before SDAx is
asserted low. This may indicate
that another master is attempting to
transmit a data ‘1’.
SDAx
SCLx
Repeated Start
Write to SSPxCON2
Write to SSPxBUF occurs here
At completion of Start bit,
hardware clears RSEN bit
1st bit
S bit set by hardware
TBRG
TBRG
SDAx = 1,
SDAx = 1,
SCLx (no change)
SCLx = 1
occurs here
TBRG TBRG TBRG
and sets SSPxIF
Sr