Datasheet

PIC16(L)F1946/47
DS41414D-page 82  2010-2012 Microchip Technology Inc.
6.4 MCLR
The MCLR is an optional external input that can reset
the device. The MCLR
function is controlled by the
MCLRE bit of Configuration Words and the LVP bit of
Configuration Words (Table 6-2).
6.4.1 MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR
pin is connected to
V
DD through an internal weak pull-up.
The device has a noise filter in the MCLR
Reset path.
The filter will detect and ignore small pulses.
6.4.2 MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 12.15 “PORTG
Registers” for more information.
6.5 Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 10.0
“Watchdog Timer (WDT)” for more information.
6.6 RESET Instruction
A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Ta ble 6-4
for default conditions after a RESET instruction has
occurred.
6.7 Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Words. See Section 3.5.2 “Overflow/Underflow
Reset” for more information.
6.8 Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
6.9 Power-Up Timer
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
The Power-up Timer is controlled by the PWRTE
bit of
Configuration Words.
6.10 Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1. Power-up Timer runs to completion (if enabled).
2. Oscillator start-up timer runs to completion (if
required for oscillator source).
3. MCLR
must be released (if enabled).
The total time-out will vary based on oscillator configu-
ration and Power-up Timer configuration. See
Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for more information.
The Power-up Timer and oscillator start-up timer run
independently of MCLR
Reset. If MCLR is kept low long
enough, the Power-up Timer and oscillator start-up
timer will expire. Upon bringing MCLR
high, the device
will begin execution immediately (see Figure 6-3). This
is useful for testing purposes or to synchronize more
than one device operating in parallel.
TABLE 6-2: MCLR CONFIGURATION
MCLRE LVP MCLR
00Disabled
10Enabled
x1Enabled
Note: A Reset does not drive the MCLR pin low.