Datasheet

TVP5150AM1

www.ti.com

SLES209E–NOVEMBER 2007– REVISED OCTOBER 2011

3.21.64 Interrupt Configuration Register A

Address C2h

Default 04h

7 6 5 4 3 2 1 0

Reserved YCbCr enable Interrupt A Interrupt

(VDPOE) polarity A

YCbCr enable (VDPOE)

0 = YCbCr pins are high impedance.

1 = YCbCr pins are active if other conditions are met (default) (see Table 3-13).

Interrupt A (read only)

0 = Interrupt A is not active on the external pin (default).

1 = Interrupt A is active on the external pin.

Interrupt polarity A must be the same as interrupt polarity B of Interrupt Configuration Register B at

Address 1Eh.

Interrupt polarity A

0 = Interrupt A is active low (default).

1 = Interrupt A is active high.

Interrupt configuration register A is used to configure the polarity of the external interrupt terminal. When

interrupt A is configured as active low, the terminal is driven low when active and high impedance when

inactive (open drain). Conversely, when the terminal is configured as active high, it is driven high when

active and driven low when inactive.

Note: An external pullup resistor (4.7kΩ to 10kΩ) is required when the polarity of the external interrupt

terminal (pin 27) is configured as active low.

3.21.65 VDP Configuration RAM Register

Address C3h C4h C5h

Default DCh 0Fh 00h

Address 7 6 5 4 3 2 1 0

C3h Configuration data

C4h RAM address (7:0)

C5h Reserved RAM

address 8

The configuration RAM data is provided to initialize the VDP with initial constants. The configuration RAM

is 512 bytes organized as 32 different configurations of 16 bytes each. The first 12 configurations are

defined for the current VBI standards. An additional two configurations can be used as a custom

programmed mode for unique standards such as Gemstar.

Address C3h is used to read or write to the RAM. The RAM internal address counter is automatically

incremented with each transaction. Addresses C5h and C4h make up a 9-bit address to load the internal

address counter with a specific start address. This can be used to write a subset of the RAM for only

those standards of interest.

NOTE

Registers D0h–FBh must all be programmed with FFh before writing or reading the

configuration RAM. Full field mode (CFh) must be disabled as well.

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