User guide

ManualsBrandsRockwell Automation ManualsEquipment1747-PT1, D1747NP002 Hand-Held Terminal

ALLEN–BRADLEY

Hand–Held Terminal

(Catalog Number 1747–PT1)

User Manual

Summary of content (486 pages)

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ALLEN–BRADLEY Hand–Held Terminal (Catalog Number 1747–PT1) User Manual
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Important User Information Solid state equipment has operational characteristics differing from those of electromechanical equipment. “Safety Guidelines for the Application, Installation and Maintenance of Solid State Controls” (Publication SGI-1.1) describes some important differences between solid state equipment and hard–wired electromechanical devices.
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Summary of Changes Summary of Changes The information below summarizes the changes to this manual since the last printing as 1747–809 in July 1989, which included the supplement 40063–079–01(A) from October 1990. New Information The table below lists sections that document new features and additional information about existing features, and shows where to find this new information.
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Table of Contents Hand–Held Terminal User Manual Preface Who Should Use this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Purpose of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Common Techniques Used in this Manual . . . . . . . . .
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Table of Contents Hand–Held Terminal User Manual Understanding File Organization Chapter 3 Data File Organization and Addressing Chapter 4 ii Program, Program Files, and Data Files . . . . . . . . . . . . . . . . . . . . . . . . . . . Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Files . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents Hand–Held Terminal User Manual Transferring Data Between Processor Files and M0 or M1 Files . . . . . . . . . Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimizing the Scan Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capturing M0–M1 File Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specialty I/O Modules with Retentive Memory . . . . . . . . . . . . . . . . . . . . .
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Table of Contents Hand–Held Terminal User Manual Creating and Editing Program Files iv Chapter 7 Creating and Deleting Program Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Subroutine Program File using the Next Consecutive File Number Creating a Subroutine Program File using a Non–Consecutive File Number Deleting a Subroutine Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Editing a Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents Hand–Held Terminal User Manual Saving and Compiling a Program Chapter 8 Configuring Online Communication Chapter 9 Downloading/Uploading a Program Chapter 10 Processor Modes Chapter 11 Saving and Compiling Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving a Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Available Compiler Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents Hand–Held Terminal User Manual Monitoring Controller Operation Chapter 12 The Force Function Chapter 13 Monitoring a Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . True/False Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitoring Data Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents Hand–Held Terminal User Manual Instruction Set Overview Chapter 15 Instruction Classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Instructions – Chapter 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer and Counter Instructions – Chapter 17 . . . . . . . . . . . . . . . . . . . . I/O Message and Communications Instructions – Chapter 18 . . . . . . . . Comparison Instructions – Chapter 19 . . . . . . . . . . . . . . . . .
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Table of Contents Hand–Held Terminal User Manual I/O Message and Communication Instructions Chapter 18 Comparison Instructions Chapter 19 Message Instruction (MSG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Status File Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Available Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents Hand–Held Terminal User Manual Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–9 True/False Status of the Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–10 Math Instructions Chapter 20 Math Instructions Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Arithmetic Status Bits .
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Table of Contents Hand–Held Terminal User Manual Decode 4 to 1 of 16 (DCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Arithmetic Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Square Root (SQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Arithmetic Status Bits . . . . . . . . . . . . . . . . . .
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Table of Contents Hand–Held Terminal User Manual Bit Shift, FIFO, and LIFO Instructions Chapter 23 Sequencer Instructions Chapter 24 Bit Shift, FIFO, and LIFO Instructions Overview . . . . . . . . . . . . . . . . . . . . . . Effect on Index Register in SLC 5/02 Processors . . . . . . . . . . . . . . . . . . . Bit Shift Left (BSL), Bit Shift Right (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents Hand–Held Terminal User Manual Nesting Subroutine Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subroutine (SBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Return from Subroutine (RET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Control Reset (MCR) . . . . . . . . . . . . . . . . . . . .
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Table of Contents Hand–Held Terminal User Manual Troubleshooting Faults Chapter 28 Troubleshooting Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Fault Routine Not in Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Fault Routine in Effect – SLC 5/02 Processors Only . . . . . . . . . . . . . Status File Fault Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents Hand–Held Terminal User Manual Understanding I/O Interrupts – SLC 5/02 Processor Only Chapter 31 HHT Messages and Error Definitions Number Systems, Hex Mask Appendix A I/O Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Programming Procedure for the I/O Interrupt Function . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Preface A–B P Preface Read this preface to familiarize yourself with the rest of the manual. This preface covers the following topics: • who should use this manual • the purpose of this manual • conventions used in this manual • Allen–Bradley support Who Should Use this Manual Use this manual if you are responsible for designing, installing, programming, or troubleshooting control systems that use Allen–Bradley small logic controllers. You should have a basic understanding of SLC 500 products.
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Preface Contents of this Manual Title Chapter P–2 Contents Preface Describes the purpose, background, and scope of this manual. Also specifies the audience for whom this manual is intended. 1 Features, Installation, Powerup Introduces you to the Hand–Held Terminal (HHT). 2 The Menu Tree Guides you through the HHT display menu tree. 3 Understanding File Organization Defines programs, program files, and data files, explaining how programs are created, stored, and modified.
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Preface Chapter Title Contents 19 Comparison Instructions Provides detailed information about these instructions. 20 Math Instructions Provides detailed information about these instructions. 21 Move and Logical Instructions Provides detailed information about these instructions. 22 File Copy and File Fill Instructions Provides detailed information about these instructions. 23 Bit Shift, FIFO, and LIFO Instructions Provides detailed information about these instructions.
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Preface Related Documentation The following documents contain additional information concerning Allen–Bradley SLC and PLC products. To obtain a copy, contact your local Allen–Bradley office or distributor. For Read this Document Document Number An overview of the SLC 500 family of products SLC 500 System Overview 1747–2.
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Preface Allen–Bradley Support Allen–Bradley offers support services worldwide, with over 75 Sales/Support Offices, 512 authorized Distributors and 260 authorized Systems Integrators located throughout the United States alone, plus Allen–Bradley representatives in every major country in the world.
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Chapter 1 Features, Installation, Powerup This chapter introduces you to the Hand–Held Terminal (HHT) hardware.
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Chapter 1 Features, Installation, Powerup The HHT is menu–driven. The display area accommodates 8 lines by 40 characters. You can display up to five rungs of a user program. When monitoring a program ONLINE, in the Run mode, instructions in a ladder diagram are intensified to indicate “true” status. A zoom feature is included to give immediate access to instruction parameters. Display Area SLC 500 PROGRAMMING SOFTWARE Rel. 2.
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Chapter 1 Features, Installation, Powerup Installing the Memory Pak, Battery, and Communication Cable The HHT (with communication cable), memory pak, and battery are supplied separately. Install each as follows: 1. Install the memory pak first. The English version is catalog number 1747–PTA1E. ! ATTENTION: The memory pak contains CMOS devices. Wear a grounding strap and use proper grounding procedures to guard against damage to the memory pak from electrostatic discharge. a.
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Chapter 1 Features, Installation, Powerup b. Insert the memory pak in its compartment as indicated in the following figure: After the memory pak is in the compartment, press down on handle to secure connector in socket. .. . .. .. .. .. .. .. .. .. .. .. ..
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Chapter 1 Features, Installation, Powerup 2. Install the battery, catalog number 1747–BA. The battery compartment is next to the memory pak compartment. ! ATTENTION: The letter B appears flashing on the prompt line of the HHT display if the battery is not installed correctly or the battery power is low; in addition, each time you power up, the self–diagnostic is interrupted, and the prompt BATTERY TEST FAILED appears.
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Chapter 1 Features, Installation, Powerup 3. Locate the communication port on the SLC 500 controller, or peripheral port on the 1747–AIC Link Coupler. The figure below shows where it is located on the different devices: Processor Module (Modular Controller) SLC 500 Fixed Controller Isolated Link Coupler (Peripheral Port) (Cover Open) (Communication Port) The connectors are keyed. Connect one end of the 1747–C10 communication cable to the top of the HHT.
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Chapter 1 Features, Installation, Powerup HHT Powerup After you install the memory pak and battery, and plug in the cable, you can test the operation of the HHT by applying power to the SLC 500 controller or plugging in the external power supply such as the 1747–NP1 or –NP2. When the HHT is energized, it performs a series of diagnostic tests. When the selftest is successfully completed, the following display appears: SLC 500 PROGRAMMING SOFTWARE Rel. 2.
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Chapter 1 Features, Installation, Powerup HHT Display Format The HHT display format consists of the following: • display area • prompt/data entry/error message area • menu tree functions The figure below indicates what appears in these areas. To access this particular screen, press [F3], PROGMAINT. Display Area Prompt/Data Entry/Error Area Menu tree functions are directly accessible. File Name: 101 File Name 0 1 2 101 1–8 Indicates that the HHT is offline.
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Chapter 1 Features, Installation, Powerup The Keyboard F1 N F3 F2 S I O U PRE/LEN ACC/POS F4 SPACE F5 This section is intended only as a brief preview of keyboard operation. Starting in chapter 6, you will become familiar with the keyboard as you are guided through various programming procedures. ESC A 7 B 8 C 9 Menu Function Keys (F1, F2, F3, F4, F5) D 4 E 5 F 6 T 1 R 2 M 3 RUNG # 0 – . SHIFT The top row of purple keys, F1 through F5, are menu function keys.
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Chapter 1 Features, Installation, Powerup Cursor Keys , , , Use the four arrow keys to: • change or modify instruction addresses • locate and correct data entry errors (either type over or use the [SPACE] key) • move the cursor left, right, up, and down in a ladder program (rungs not shown on the HHT display automatically scroll into view as you move the cursor up [or down] in the program) • scroll through controller and I/O configuration selections • scroll through program file directories • scroll thro
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Chapter 1 Features, Installation, Powerup The keys scroll through the I/O module choices in this display. Similarly, these keys scroll through rack and CPU choices in the appropriate displays. Rack Rack Rack Slot 1 2 3 0 = = = = 1746–A4 NONE NONE 1747–L511 Slot 1 = 1746–IA4 Slot 1 = 1746–IA4 F1 The keys scroll through user program files.
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Chapter 1 Features, Installation, Powerup ZOOM and RUNG Keys The [ZOOM] key brings up a display that shows the parameters of an instruction. The [RUNG] key moves the cursor to a particular rung. Using this key saves time when you have a long ladder diagram. When you press [RUNG], you are prompted for the rung number that you want to edit or monitor. Enter the rung number and press [ENTER], the cursor moves to the selected rung and the rung appears at the top of the display.
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Chapter 2 The Menu Tree This chapter guides you through the HHT display menu tree. It is intended as an overview. For a more detailed introduction to ladder programming, refer to The Getting Started Guide for HHT, catalog number 1747–NM009. The abbreviated function and instruction mnemonic keys you encounter in this manual and on the HHT displays are explained at the end of this chapter.
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Chapter 2 The Menu Tree The ENTER Key 1. Because the > symbol appears in the lower right hand corner of the display, press [ENTER] to display additional menu functions. File Name: 101 File Name 0 1 2 101 Prog Name: 1492 Type Size(Instr) System 217 Reserved 0 Ladder 465 OFL EDT_DAT SEL_PRO EDT_I/O CLR_MEM F1 F2 F3 F4 > F5 2. Press [F4], CLR_MEM to clear the HHT memory.
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Chapter 2 The Menu Tree The Main Menu After going through diagnostic tests at startup/powerup, the HHT displays the Main menu. It consists of the following function keys: • Selftest • Terminal • Program Maintenance • Utility The display appears as follows: SLC 500 PROGRAMMING SOFTWARE Rel. 2.
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Chapter 2 The Menu Tree UTILITY, [F5] Allows you to: • attach online to a processor – upload and download programs between the processor and HHT – change processor mode – transfer processor memory between RAM and EEPROM – force inputs and outputs • access network diagnostic functions • create or delete processor passwords • clear processor memory • monitor the ladder diagram while the processor is in Run mode The Menu Tree The figures that follow, graphically guide you through the HHT menus and sub–menus
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Chapter 2 The Menu Tree Main Menu – Program Maintenance [F3] F3 PROGMAINT F1 CHG_NAM F2 PROGRAM F2 CRT_FIL F4 FILE F3 EDT_FIL F1 INS_RNG_ F2 MOD_RNG F3 SEARCH F1 CUR–INS F4 DEL_RNG F2 CUR–OPD F5 UND_RNG F1 INS_INST F2 BRANCH F3 NEW–INS F4 UP F3 MOD_INST F5 FORCE F5 ACP_RNG See next page.
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Chapter 2 The Menu Tree Program Maintenance [F3] – Ladder Editing See previous page.
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Chapter 2 The Menu Tree Main Menu – Utility [F5], Default Program in Processor (First Time) F5 UTILITY F1 ONLINE F1 F3 F4 F5 F2 WHO F3 PASSWRD F5 DIAGNSTC * ATTACH NODE_CFG OWNER F1 ENT F2 REM F3 ENT_MAS F4 REM_MAS F1 NODE F5 NETWORK F1 OFFLINE F2 DWNLOAD F3 CLR_PRC F4 MEM_PRC F1 CHG_ADR F2 MAX_ADR F3 F1 F5 F5 RESET BAUD F1 19200 SET_OWNR F2 9600 CLR_OWNR F3 2400 F4 1200 CLR_MEM Main Menu – Utility [F5], Default Program in Processor (If Previously At
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Chapter 2 The Menu Tree Main Menu – Utility [F5], Processor Program Does Not Equal HHT Program (First Time) F5 UTILITY F1 ONLINE F1 F3 F4 F5 F2 WHO F3 PASSWRD F5 DIAGNSTC * ATTACH NODE_CFG OWNER F1 ENT F2 REM F3 ENT_MAS F4 REM_MAS F1 NODE F5 NETWORK F1 OFFLINE F2 UPLOAD F3 DWNLOAD F4 F5 F5 RESET MODE F1 RUN CLR_PRC F3 TEST F2 CONT F1 CHG_ADR F5 PROGRAM F4 SINGLE F2 MAX_ADR F3 BAUD F1 SET_OWNR F5 CLR_OWNR F1 19200 F2 9600 F3 2400 F4 1200 CLR
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Chapter 2 The Menu Tree Main Menu – Utility [F5], Processor Program Equals HHT Program (First Time) Legend F5 UTILITY F1 ONLINE F1 F3 DIAGNSTC ATTACH Modular controllers only F1 NODE F5 NETWORK F1 OFFLINE F2 UPLOAD F3 DWNLOAD F4 MODE F1 RUN F5 CLR_PROC F3 TEST F2 CONT F5 PROGRAM F4 SINGLE F1 ENT F2 REM F3 ENT_MAS F4 REM_MAS F2 MEM_PRC F4 PRC_MEM F1 ADDRESS F2 NEXT_FL F3 PREV_FL F4 NEXT_PG F5 PREV_PG F1 MODE F1 RUN F3 TEST F2 CONT F5 PROGRAM F
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Chapter 2 The Menu Tree Main Menu – Utility [F5], Processor Program Equals the HHT Program (If Previously Attached to that Processor) F5 UTILITY F1 ONLINE F1 OFFLINE F2 UPLOAD F3 DWNLOAD F4 MODE F1 RUN F5 CLR_PROC F3 TEST F2 CONT F5 PROGRAM F4 SINGLE F1 ENT F2 REM F3 ENT_MAS F4 REM_MAS Modular controllers only F2 MEM_PRC SLC 5/02 only F4 PRC_MEM F1 ADDRESS F2 NEXT_FL F3 PREV_FL F4 NEXT_PG F5 PREV_PG F1 MODE ENTER F1 PASSWRD F3 XFERMEM F4 EDT_DAT F5 M
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Chapter 2 The Menu Tree HHT Function Keys and Instruction Mnemonics The following table provides a listing of the abbreviated function keys and their meanings. The next table provides a list of instruction mnemonics.
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Chapter 2 The Menu Tree Abbreviation 2–12 Meaning EDT_DAT edit data EDT_FIL edit file EDT_I/O edit I/O ENT enter ENT_MAS enter master EXEC_FILE executable files EXT_DWN extend down EXT_UP extend up F force FILEPRT file protection FLT fault FUTACC future access HEX/BCD hexadecimal/binary coded decimal number INDXCHK index across files INS_BR insert branch INS_INST insert instruction INS_RNG insert rung INT_SBR interrupt subroutine I/O_MSG I/O message MAX_ADR maximum
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Chapter 2 The Menu Tree Abbreviation Meaning PASSWRD password PRC_MEM processor to memory module PREV_FL previous file PREV_PG previous page PRG program PRG_SIZE program size PROGMAINT program maintenance RLY relay REM remove REM_ALL remove all REM_MAS remove master SAVE_CT save and continue SAVE_EX save and exit SEL_PRO select processor SET_OWNR set ownership SFT/SEQ shift/sequencer SNK sink SRC source SSN single scan TERM terminal TMR/CNT timer/counter TRANS t
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Chapter 2 The Menu Tree Instruction Mnemonics Mnemonic 2–14 Instruction ADD add AND and BSL bit shift left BSR bit shift right CLR clear COP copy file CTD count down CTU count up DCD decode 4 to 1 of 16 DDV double divide DIV divide EQU equal FFL FIFO load FFU FIFO unload FLL file fill FRD convert from BCD GEQ greater than or equal to GRT greater than HSC high–speed counter IID I/O interrupt disable IIE I/O interrupt enable IIM immediate input with mask INT in
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Chapter 2 The Menu Tree Mnemonic Instruction NEG negate NEQ not equal NOT not OR or OSR one–shot rising OTE output energize OTL output latch OTU output unlatch PID proportional integral derivative REF I/O refresh RES reset RET return from subroutine RPI reset pending I/O interrupt RTO retentive on–delay timer SBR subroutine SCL scale data SQC sequencer compare SQL sequencer load SQO sequencer output SQR square root STD STI disable STE STI enable STS STI start
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Chapter 3 Understanding File Organization This chapter: • defines program, program files, and data files • indicates how programs are stored and transferred • covers the use of EEPROMs and UVPROMs for program backup Program, Program Files, and Data Files As explained in the following sections, the program can reside in: • the Hand–Held Terminal • an SLC 500 processor • a memory module • the APS terminal Notes on terminology: The term program used in Hand-Held Terminal (HHT) displays is equivalent to the
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Chapter 3 Understanding File Organization Program A program is the collective program files and data files of a particular user program. It contains all the instructions, data, and configuration information pertaining to that user program. The HHT allows only numbers and certain letters available on the keyboard to be entered for a program name. The program is a transferable unit.
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Chapter 3 Understanding File Organization Data Files Data files contain the data associated with the program files. Each program can contain up to 256 data files. These files are organized by the type of data they contain. Each piece of data in each of these files has an address associated with it that identifies it for use in the program file. For example, an input point has an address that represents its location in the input data file.
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Chapter 3 Understanding File Organization Uploading Programs When you need to modify a program, it may be necessary to upload the program from an SLC 500 processor to the HHT. If the original HHT program is not current or the HHT has been attached to a different processor, uploading is necessary. Use the upload function to do this. When you are uploading, you can leave the processor in the Run mode.
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Chapter 4 Data File Organization and Addressing This chapter discusses the following topics: • data file organization and addressing • indexed addressing (SLC 5/02 processors) • file instructions (using the file indicator #) • creating and deleting data • program constants • M0-M1 files, G files (SLC 5/02 processors with specialty I/O modules) Data File Organization Data files contain the status information associated with external I/O and all other instructions you use in your main and subroutine ladde
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Chapter 4 Data File Organization and Addressing Data File Types For the purposes of addressing, each data file type is identified by a letter (identifier) and a file number. File numbers 0 through 7 are the default files, created for you. If you need additional storage, you can create files by specifying the appropriate identifier and a file number from 9 to 255. This applies to Bit, Timer, Counter, Control, and Integer files only.
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Chapter 4 Data File Organization and Addressing Typical element, word, and bit addresses are shown below: File Type File Number Element File Number File Type N7:15 Element File Type Word T4:7.ACC Element Delimiter An element address Element Bit B3:64/15 Word Delimiter Element Delimiter File Number Element Delimiter A word address Bit Delimiter A bit address The address format varies, depending on the file type.
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Chapter 4 Data File Organization and Addressing Data Files 0 and 1 – Outputs and Inputs Bits in file 0 are used to represent external outputs. Bits in file 1 are used to represent external inputs. In most cases, a single 16-bit word in these files will correspond to a slot location in your controller, with bit numbers corresponding to input or output terminal numbers. Unused bits of the word are not available for use.
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Chapter 4 Data File Organization and Addressing Assign I/O addresses to fixed I/O controllers as shown in the table below: Format Explanation O Output I Input : Element delimiter Slot number (decimal) e fixed I/O controller: 0 left slot of expansion rack: 1 right slot of expansion rack: 2 O:e.s/b . Word delimiter. Required only if a word number is necessary as noted below. s Word number / Bit delimiter b Terminal number I:e.
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Chapter 4 Data File Organization and Addressing I/O Addressing for a Modular Controller: With modular controllers, slot number 0 is reserved for the processor module (CPU). Slot 0 is invalid as an I/O slot. The figure below shows a modular controller configuration consisting of a 7-slot rack interconnected with a 10-slot rack. Slot 0 contains the CPU. Slots 1 through 10 contain I/O modules. The remaining slots are saved for future I/O expansion.
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Chapter 4 Data File Organization and Addressing The table below explains the addressing format for outputs and inputs. Note that the format specifies e as the slot number and s as the word number. When you are dealing with file instructions, refer to the element as e.s (slot and word), taken together. Format Explanation O Output I Input : Element delimiter O:e.s/b e Slot number (decimal) I:e.s/b . Word delimiter. Required only if a word number is necessary as noted below.
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Chapter 4 Data File Organization and Addressing Data File 3 – Bit File 3 is the bit file, used primarily for bit (relay logic) instructions, shift registers, and sequencers. The maximum size of the file is 256 1-word elements, a total of 4096 bits. You can address bits by specifying the element number (0 to 255) and the bit number (0 to 15) within the element. You can also address bits by numbering them in sequence, 0 to 4095. You can also address elements of this file.
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Chapter 4 Data File Organization and Addressing Data File 4 – Timers Timers are 3-word elements. Word 0 is the control word, word 1 stores the preset value, and word 2 stores the accumulated value.
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Chapter 4 Data File Organization and Addressing Data File 5 – Counters Counters are 3-word elements. Word 0 is the control word, word 1 stores the preset value, and word 2 stores the accumulated value.
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Chapter 4 Data File Organization and Addressing Data File 6 – Control These are 3-word elements, used with Bit Shift, FIFO, LIFO, and Sequencer instructions. Word 0 is the status word, word 1 indicates the length of stored data, and word 2 indicates position.
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Chapter 4 Data File Organization and Addressing Data File 7 – Integer These are 1-word elements, addressable at the element and bit level. Address Data N7:0 N7:1 N7:2 N7:3 Element 1 has a decimal value of 495. 0 495 0 66 Element 3 has a decimal value of 66. Assign integer addresses as follows: Format Nf:e/b Explanation N Integer file f File number. Number 7 is the default file. A file number between 10 – 255 can be used if additional storage is required.
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Chapter 4 Data File Organization and Addressing Indexed Addressing SLC 5/02 Processors Only An indexed address is offset from its indicated address in the data table. Indexing of addresses applies to word addresses in bit and integer data files, preset and accumulator words of timers and counters, and to the length and position words of control elements. You can also index I/O addresses. The indexed address symbol is #.
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Chapter 4 Data File Organization and Addressing Creating Data for Indexed Addresses Data tables are not expanded automatically to accommodate indexed addresses. You must create this data with the memory map function as described in chapter 6. In the example on the previous page, data words N7:3 through N7:12 and N11:6 through N11:15 must be allocated. Important: Failure to allocate these data file elements will result in an unintended overwrite condition or a major fault.
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Chapter 4 Data File Organization and Addressing Monitoring Indexed Addresses The offset address value is not displayed when you monitor an indexed address. For example, the value at N7:2 appears when you monitor indexed address #N7:2. Example If your application requires you to monitor indexed data, we recommend that you use a MOV instruction to store the value. MOV B3 ] [ 1 MOVE Source #N7:2 Dest N10:2 ADD ADD Source A #N7:2 Source B T4:0.ACC Dest T4:1.
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Chapter 4 Data File Organization and Addressing File Instructions – Using the File Indicator # File instructions employ user-created files. These files are addressed with the # sign. They store an offset value in word S:24, just as with indexed addressing discussed in the last section.
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Chapter 4 Data File Organization and Addressing Sequencer Instructions The figure below shows a user-defined file within bit data file 3. For this particular user-defined file, enter the following parameters when programming the instruction: • #B3:4 The address of the file. This defines the starting element as element 4, bit file 3. • 6 This is the specified length of the file, 6 elements beyond the starting address (totals 7 elements).
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Chapter 4 Data File Organization and Addressing File Copy and File Fill Instructions These instructions manipulate user-defined files. The files are used as source or destination parameters in File Copy or File Fill instructions. Files can be Output, Input, Status, Bit, Timer, Counter, Control, or Integer files. Two examples are shown below. Note that the file length is the specified number of elements of the destination file; this differs from the file length specification for sequencer instructions.
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Chapter 4 Data File Organization and Addressing Creating Data The SLC 500 controller provides the flexibility of a user-configured memory. Data is created, in the Offline mode, in two ways: • Assign addresses to instructions in your program – When you assign an address to an instruction in your ladder program, you are allocating memory space in a data file. Data files are expanded for instructions that use File Addresses.
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Chapter 4 Data File Organization and Addressing Deleting Data Deleting data is accomplished only in the Offline mode. There are two ways to delete the contents of data files: • Clear memory – This deletes your entire program, including all files except the system program file (0) and the status data file (2). • Use the memory map function – The memory map function allows you to delete data in individual files or portions of files.
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Chapter 4 Data File Organization and Addressing M0 and M1 Data Files – Specialty I/O Modules M0 and M1 files are data files that reside in specialty I/O modules only. There is no image for these files in the processor memory. The application of these files depends on the function of the particular specialty I/O module. For some modules, the M0 file is regarded as a module output file and the M1 file is regarded as a module input file.
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Chapter 4 Data File Organization and Addressing Monitoring Bit Instructions Having M0 or M1 Addresses When you monitor a ladder program in the Run or Test mode, the following bit instructions, addressed to an M0 or M1 file, are indicated as false regardless of their actual true/false logical state. Mf:e.s ] [ b Mf:e.s ]/[ b Mf:e.s ( ) b Mf:e.s (L) b Mf:e.
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Chapter 4 Data File Organization and Addressing Transferring Data Between Processor Files and M0 or M1 Files As pointed out earlier, the processor does not contain an image of the M0 or M1 file. As a result, you must edit and monitor M0 and M1 file data via instructions in your ladder program. For example, you can copy a block of data from a processor data file to an M0 or M1 data file or vice versa using the COP instruction in your ladder program.
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Chapter 4 Data File Organization and Addressing Access Time During the program scan, the processor must access the specialty I/O card to read/write M0 or M1 data. This access time must be added to the execution time of each instruction referencing M0 or M1 data. The following table shows approximate access times per instruction or word of data for the SLC 5/02 processors. Access Time per Bit Instruction or Word of Data Access Time per Multi–Word Instruction SLC 5/02 Series B 1.93 ms 1.58 ms plus 0.
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Chapter 4 Data File Organization and Addressing Minimizing the Scan Time You can keep the processor scan time to a minimum by economizing on the use of instructions addressing the M0 or M1 files. For example, XIC instruction M0:2.1/1 is used in rungs 1 and 2 of figure 1 below, adding approximately 2 ms to the scan time if you are using a Series B processor. In the equivalent rungs of figure 2, XIC instruction M0:2.1/1 is used only in rung 1, reducing the scan time by approximately 1 ms. 1 M0:2.
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Chapter 4 Data File Organization and Addressing Capturing M0–M1 File Data The first and second figures in the last section illustrate a technique allowing you to capture and use M0 or M1 data as it exists at a particular time. In the first figure, bit M0:2.1/1 could change state between rungs 1 and 2. This could interfere with the logic applied in rung 2. The second figure avoids the problem.
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Chapter 4 Data File Organization and Addressing G Data Files – Specialty I/O Modules Some specialty I/O modules use G (confiGuration) files (indicated in the specialty I/O module user’s manual). These files can be thought of as the software equivalent of DIP switches. The content of G files is accessed and edited offline under the I/O Configuration function. You cannot access G files under the Monitor File function.
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Chapter 4 Data File Organization and Addressing Editing G File Data Data in the G file must be edited according to your application and the requirements of the specialty I/O module. You edit the data offline under the I/O configuration function only.
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Chapter 5 Ladder Program Basics This chapter discusses the basic operation of ladder programs. For a more simplified introduction to ladder programming, refer to The Getting Started Guide for HHT, catalog number 1747–NM009. This guide is intended for the first time user. Ladder Programming The ladder program you enter into the controller’s memory contains bit (relay logic) instructions representing external input and output devices.
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Chapter 5 Ladder Program Basics A 1–Rung Ladder Program A ladder program consists of individual rungs, each containing at least one output instruction and one or more input instructions. Variations of this simple rung construction are discussed in later chapters. This ladder rung has two input instructions and an output instruction. An output instruction always appears at the right, next to the right power rail. Input instructions always appear to the left of the output instruction.
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Chapter 5 Ladder Program Basics Logical Continuity During controller operation, the processor determines the on/off state of the bits in the data files, evaluates the rung logic, and changes the state of the outputs according to the logical continuity of rungs. More specifically, input instructions set up the conditions under which the processor will make an output instruction true or false.
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Chapter 5 Ladder Program Basics Series Logic In the previous section on logical continuity, you have seen examples of series (And) logic. This means that when all input conditions in the path are true, energize the output. Example – Series Inputs B A C In the above example, if A and B are true, energize C. Parallel Logic Another form of logical continuity is Parallel (OR) logic. This means that when one or another path of logic is true, energize the output.
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Chapter 5 Ladder Program Basics Input Branching Use an input branch in your application program to allow more than one combination of input conditions to form parallel branches (OR–logic conditions.) If at least one of these parallel branches forms a true logic path, the rung logic is enabled. If none of the parallel branches forms a true logic path, rung logic is not enabled and the output instruction logic will not be true. (Output is not energized.
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Chapter 5 Ladder Program Basics With the SLC 5/02 processor, additional input logic instructions (conditions) can be programmed in the output branches to further condition control of the outputs. When there is a true logic path, including extra input conditions on an output branch, that branch becomes true.
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Chapter 5 Ladder Program Basics Nested branches can be converted into non–nested branches by repeating instructions to make parallel equivalents.
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Chapter 5 Ladder Program Basics A 4–Rung Ladder Program The following 4-rung ladder program uses the same 3 bit addresses as our simple 1-rung diagram. It also uses an external input bit address and an external output bit address. Note that individual bits are addressed repeatedly. For example, B3/11 is addressed with an XIC instruction in rungs 1 and 4, and it is addressed with both an XIC and an OTE instruction in rung 2.
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Chapter 5 Ladder Program Basics Application Example Use the following program to achieve the maintained contact action of an On–Off toggle switch using a momentary contact push button. (Press for On; press again for Off.) The first time you press the push button (represented by address I:0/1), instruction B3/11 is latched, energizing output O:0/2. The second time you press the push button, instruction B3/12 unlatches instruction B3/11, de–energizing output O:0/2.
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Chapter 5 Ladder Program Basics When the state of a bit changes during the scan, the effects this may have in earlier rungs of the program are not accounted for until the next scan. To point this out, we have shown successive scans (1000 and 1001, 2000 and 2001, etc.). XIC I:0/1 1 I:0.0 B3 B3 ] [ ]/[ ] [ 1 10 11 B3 ( ) 12 2 I:0.
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Chapter 5 Ladder Program Basics Operating Cycle (Simplified) The diagram below shows a simplified operating cycle, consisting of the program scan, discussed in the last section, and the I/O scan. I/O SCAN PROGRAM SCAN In the I/O scan, data associated with external outputs is transferred from the output data file to the output terminals. (This data was updated during the preceding program scan.
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Chapter 5 Ladder Program Basics The following figures indicate how the operating cycle works for the 4-rung ladder program discussed on pages 5–7 through 5–10. When the Input Goes True Scan before input goes true (scan 999). Input Scan 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 Input Data File 0 0 0 0 0 0 0 0 0 0 I:0 Input Bit De–energized I:0.0 Program Scan Ladder Program Instructions are normal intensity. O:0.
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Chapter 5 Ladder Program Basics When the Input Goes False Scan before input goes false (scan 1999). Input Scan 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 Input Data File 0 0 0 0 0 0 0 0 1 0 I:0 Input Bit Energized I:0.0 Ladder Program Instructions intensified O:0.
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Chapter 6 Creating a Program In this chapter you create a ladder program. The tasks you will perform are: • configure your SLC 500 controller • name your program Creating a Program Offline with the HHT A program is always created offline using the HHT. In creating the program, you: 1. Clear the memory of the HHT. 2. Configure the processor. 3. Configure the I/O. 4. Name the ladder program and main program file.
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Chapter 6 Creating a Program 2. Press [F3], PROGMAINT. Then press [ENTER] to view the additional menu functions (as indicated by the > symbol in the lower right corner). The following display appears: File Name: File Name 0 1 2 Prog Name:2345 Type Size(Instr) System * Reserved * Ladder * OFL EDT_DAT SEL_PRO EDT_I/O CLR_MEM F1 F2 F3 F4 > F5 3. Press [F4], CLR_MEM.
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Chapter 6 Creating a Program 2. Use the cursor keys [ ↑ ] or [ ↓ ] then press [ENTER] to select the correct processor type. For this example, select the 1747–L511 processor. Since this is the default selection on the display, press [ENTER]. Processor module 1747–L511 is entered into memory. The previous display appears. 3.
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Chapter 6 Creating a Program 3. Assign the input module found in slot 1 by scrolling with the [ ↓ ] key. For this example, press the [ ↓ ] key once to assign the 1746–IA4 module. (The [F3], OTHER key is for configuring I/O modules not found in the list of catalog numbers. See your specialty I/O user manual or instruction sheet for the proper code). 4. Press [ENTER]. The 1746–IA4 AC input is entered for slot 1.
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Chapter 6 Creating a Program Configuring Specialty I/O Modules – (SLC 5/02 Specific) When you use a specialty I/O module, you must indicate the type of module to the HHT. The configuration menu provides a list of available modules to select from. Each module is pre–configured, so after selecting the module from the list you have the option of viewing its configuration by pressing [F5], ADV_SET, advanced setup. Alteration of the fields is not recommended since these fields are pre–configured.
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Chapter 6 Creating a Program 4. Press [F3], OTHER. For the RIO Scanner Module, enter the module ID code. Type 13608, then press [ENTER]. (For some module ID codes, the HHT may request additional information). The next display appears: Rack Rack Rack Slot 1 2 3 0 = = = = 1746–A7 NONE NONE 1747–L524 7–SLOT RACK CPU–4K USER MEMORY Slot 6 = OTHER 13608 MOD_RCK MOD_SLT DEL_SLT UND_SLT ADV_SET F1 F2 F3 F4 F5 5.
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Chapter 6 Creating a Program 9. Press [ESC]. The following display appears: –––––– Advanced I/O Configuration –––––– Current Subroutine File: 0 Current Configuration File: G6 OFL INT_SBR MOD_SET CFG_SIZ ADV_SIZ F1 F2 F3 F4 F5 10.Set the G file (configuration file) size to 3. Press [F3], CFG_SIZ. The following display appears: –––––– Advanced I/O Configuration –––––– Current Subroutine File: 0 Current Configuration File: G6 ENTER CONFIG. F1 FILE SIZE: F2 F3 0 F4 OFL F5 11.
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Chapter 6 Creating a Program 13.From this display you may choose the data format you prefer to use to configure the module for your application: BINary, DECimal, HEXadecimal/Binary Coded Decimal. Refer to Remote I/O Scanner User Manual, catalog number 1747–NM005, for a detailed description of the configuration specifications. 14.
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Chapter 6 Creating a Program 2. Press [F1], CHG_NAM. The following display appears: ––––––– Change Program/File Name ––––––– File Name: Program Name: DEFAULT OFL PROGRAM F1 F2 FILE F3 F4 F5 3. Press [F2], PROGRAM. The following display appears: ––––––– Change Program/File Name ––––––– File Name: Program Name: DEFAULT ENTER NAME: DEFAULT F1 F2 OFL F3 F4 F5 4. Name your program 1000. Type 1000, then press [SPACE], then [ENTER].
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Chapter 6 Creating a Program 1. Continuing from the change name display, press [F4], FILE. This display appears: ––––––– Change Program/File Name ––––––– File Name: Program Name: 1000 ENTER NAME: F1 OFL F2 F3 F4 F5 2. Name the main program file 222. Type 222, then press [ENTER]. The main program file name is entered and you are returned to the previous menu. The same restrictions apply to the characters for the main program file name as to ladder program names.
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Chapter 6 Creating a Program You can use passwords in the following combinations: You must enter the password to gain access to the program file. Only Password Designated Only Master Password Designated Password and Master Password Designated You do not have to enter the master password to gain access to the program file. A master password is used by itself to allow access if a regular password is accidentally entered.
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Chapter 6 Creating a Program 3. Press [F1], ENT. The display prompts you for the password: File Name: 222 File Name 0 1 2 222 Prog Name:1000 Type Size(Instr) System * Reserved * Ladder * ENTER NEW PASSWORD: F1 F2 OFL F3 F4 F5 4. Type 123. Notice that as you enter the characters, X’s are displayed for security reasons: File Name: 222 File Name 0 1 2 222 Prog Name:1000 Type Size(Instr) System * Reserved * Ladder * ENTER NEW PASSWORD: XXX F1 F2 F3 OFL F4 F5 5. Press [ENTER].
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Chapter 6 Creating a Program Removing and Changing Passwords To remove a password or master password, do one of the following: Removing Passwords Removing Master Passwords 1. Press [F3], PASSWRD. 1. Press [F3], PASSWRD. 2. Press [F2], REM 2. Press [F4], REM_MAS. 3. Type existing password and press [ENTER]. 3. Type the existing master password and press [ENTER]. To change a password or master password, do one of the following: Changing Passwords Changing Master Passwords 1. Press [F3], PASSWRD.
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Chapter 7 Creating and Editing Program Files In this chapter you create a ladder program. The topics include: • creating and deleting program files • editing program files • using the search function • creating and deleting data files Creating and Deleting Program Files As described in chapter 2, a program must contain the main program file (file 2) for user–programmed instructions defining how the controller is to operate.
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Chapter 7 Creating and Editing a Program File 3. To create subroutine program file 3, press [3] then [ENTER]. File 3 is created and the following display appears showing subroutine file 3 as a ladder file. File Name: 222 File Name 0 1 2 222 3 Prog Name:1000 Type Size(Instr) System * Reserved * Ladder * Ladder * OFL CHG_NAM CRT_FIL EDT_FIL DEL_FIL MEM_MAP > F1 F2 F3 F4 F5 You may not name any of the subroutine program files using the HHT. Subroutine program files may be named on an APS terminal.
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Chapter 7 Creating and Editing a Program File Deleting a Subroutine Program File All created program files (file numbers 3 – 255) can be deleted. You cannot delete files 0 and 1. Deleting file 2 deletes all ladder rungs in the main program file. Attempting to delete file 0, file 1, or an undefined subroutine file displays the FILE CANNOT BE DELETED! prompt. In the case of a subroutine file, the error message indicates that a subroutine program file of a higher number exists.
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Chapter 7 Creating and Editing a Program File Editing a Program File This section describes the following editing techniques: • entering a rung • adding a rung with branching • modifying rungs • modifying instructions • modifying branches • deleting branches • deleting and copying instructions • deleting and copying rungs Important: In the following examples, there may be multiple ways to enter certain instructions. The examples are chosen to show the simplest methods of programming and editing.
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Chapter 7 Creating and Editing a Program File Entering a Rung To enter a rung, do the following: 1. Press [F3], EDT_FIL from the program maintenance display. The following display appears: File Name: 222 File Name 0 1 2 222 3 ENTER FILE NUMBER: F1 F2 Prog Name:1000 Type Size(Instr) System * Reserved * Ladder * Ladder * OFL F3 F4 F5 2. Edit file number 2, the main program file. Press [2], then [ENTER]. The display shows the END of program statement. No other rungs exist at this time. The numbers 2.0.0.
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Chapter 7 Creating and Editing a Program File Entering an Examine if Closed Instruction 1. Press [F1], INS_INST. The following display appears: 2.0.0.0.* I I BIT OFL TMR/CNT I/O_MSG COMPARE CPT/MTH > F1 F2 F3 F4 F5 2. Press [F1], BIT. The following display appears: 2.0.0.0.* I I ] [ ]/[ ( ) (L) OFL (U) F2 F3 F4 F5 F1 > 3. Press [F1], —] [— , for the examine if closed instruction. The following zoom display appears: ] [ ZOOM on XIC NAME: BIT ADDR: 2.0.0.0.
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Chapter 7 Creating and Editing a Program File This zoom display, once again gives you a chance to verify that all the information entered is accurate. Notice that the address displayed is shown in its full format: 2.0.0.0.* ] [ ZOOM on XIC NAME: EXAMINE IF CLOSED BIT ADDR: I1:1.0/0 ENTER BIT ADDR: EDT_DAT F1 I1:1.0/0 F2 F3 F4 ACCEPT F5 6. Press [F5], ACCEPT. This inserts the instruction and address into the rung. The following rung display appears: 2.0.0.0.
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Chapter 7 Creating and Editing a Program File 3. Press [F5], ACCEPT, then press [ESC] twice to move up through the menu displays. Now press [F5], ACP_RUNG. The following display appears: 2.1.0.0.* ( ) ] [ Notice the I symbol in the power rails has changed to a solid line, indicating the rung is accepted into the program. OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG > F1 F2 F3 F4 F5 Important: Saving and compiling your ladder program is explained in detail, in the next chapter.
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Chapter 7 Creating and Editing a Program File Adding a Rung to a Program 1. From the previous display, press [ENTER] for the additional menu functions. The following display appears: 2.0.0.0.* ( ) ] [ OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG > F1 F2 F3 F4 F5 2. Press the [ ↓ ] key once to place the cursor on the END of program statement. 3. Press [F1], INS_RNG. The insert rung function always places the new rung above the rung on which the cursor is positioned.
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Chapter 7 Creating and Editing a Program File 5. Enter the address for the first examine if closed instruction. Type the address I:1/0, then press [ENTER], then [F5], ACCEPT. The following display appears with the cursor positioned on the right power rail: 2.1.0.0.* I ( ) ] [ ] [ I OFL ] [ ]/[ ( ) (L) F1 F2 F3 F4 (U) > F5 6. Enter the output energize instruction. Press [F3], —( )— . The following zoom display appears: ( ) ZOOM on OTE NAME: BIT ADDR: 2.0.0.0.
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Chapter 7 Creating and Editing a Program File Entering a Parallel Branch The five branching instructions available on the HHT are listed below. Function Key Description [F1], Extend Up Adds a parallel branch above the cursored branch. [F2], Extend Down Adds a parallel branch below the cursored branch. Places the starting point of a branch to the right of the cursored instruction or at the cursor. Places the starting point of the branch to the left of the cursored instruction or at the cursor.
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Chapter 7 Creating and Editing a Program File 3. With the cursor still on the output energize instruction, press [F4], INS_BR. The display changes as follows: 2.1.0.0.* I ( ) ( ) I ] [ ] [ SELECT BRANCH TARGET, PRESS ENTER OFL F1 F2 F3 F4 F5 The insert branch instruction places the start of the branch to the left of the cursor position. (You choose the direction of the branch target by using the [←] or [→] keys.) 4.
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Chapter 7 Creating and Editing a Program File 2. Press [F1], INS_INST, then [F1], BIT, then [F1], —] [— . The zoom display prompts you for the bit address: ] [ ZOOM on XIC NAME: BIT ADDR: 2.1.0.0.* EXAMINE IF CLOSED ENTER BIT ADDR: F1 F2 F3 F4 F5 3. Type the address I:1/1, then press [ENTER], then [F5], ACCEPT. The display appears as follows: 2.1.1.1.* I I ( ) ( ) I I ] [ ] [ ] [ OFL ] [ ]/[ ( ) (L) F1 F2 F3 F4 (U) > F5 4.
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Chapter 7 Creating and Editing a Program File Modifying Rungs In the previous two examples you created rungs by inserting them into the program. After rungs are part of a ladder program, you can modify those rungs offline, at any time. Adding an Instruction to a Rung In this example, add an examine if closed instruction to the first rung (rung 0) of your program. The modified rung should appear as follows. I:1.0 ] [ 0 O:3.0 ( ) 0 I:1.0 ] [ 2 Add this instruction to the rung.
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Chapter 7 Creating and Editing a Program File 4. Press [F1], —] [— for the new examine if closed instruction. The following zoom display appears: ] [ ZOOM on XIC NAME: BIT ADDR: 2.0.0.0.2 EXAMINE IF CLOSED ENTER BIT ADDR: F1 F2 F3 F4 F5 5. At the ENTER BIT ADDR: prompt, type the address I:1/2, then press [ENTER]. 6. Press [F5], ACCEPT. This inserts the instruction and address into the rung. The following display appears: OTE:O0:3.0/0 I ] [ ] [ ] [ ] [ F1 NO FORCE 2.0.0.0.
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Chapter 7 Creating and Editing a Program File Modifying Instructions In the previous example you modified a rung by adding an instruction to the rung. Another function available in the HHT is the ability to modify instructions. Instructions may be edited by changing the address and/or changing the type of instruction. The following examples show you how to do both.
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Chapter 7 Creating and Editing a Program File 4. Press [F3], MOD_INST, then [ZOOM]. The following display appears with the cursor on the first character of the instruction address, on the prompt line: 2.0.0.0.2 ] [ ZOOM on XIC NAME: EXAMINE IF CLOSED BIT ADDR:I1:1.0/2 ENTER BIT ADDR: EDT_DAT F1 F2 I1:1.0/2 F3 F4 ACCEPT F5 5.
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Chapter 7 Creating and Editing a Program File Changing an Instruction Type Change the second examine if closed instruction, in the first rung of the program, to an examine if open instruction. Keep the same address for the new instruction. The new rung should appear as follows: O:3.0 ( ) 0 I:1.0 I:1.0 ] [ ]/[ 0 1 Change this instruction type. 1. From the previous save and continue display, press [ENTER]. The following display appears: 2.0.0.0.
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Chapter 7 Creating and Editing a Program File 4. Since all the information is correct, press [F5], ACCEPT. The new instruction is inserted into the rung. NO FORCE XIC:I1:1.0/1 I 2.0.0.0.2 ( ) I ( ) ]/[ ] [ ] [ ] [ OFL ] [ F1 ]/[ ( ) (L) (U) F2 F3 F4 F5 > 5. To accept the new instruction, press [ESC] twice to display the proper menu, then press [F5], ACP_RNG. 6. Save the changes.
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Chapter 7 Creating and Editing a Program File 2. Because the cursor is positioned on the left power rail of rung 0, move the cursor to a position within nest level 1, branch level 1 of rung 1; by pressing the [↓] key, then the [→] key, then the [↓] key. The display changes to the following: 2.1.1.1.* ] [ ] [ ] [ ]/[ ( ) ( ) Cursor Location OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG > F1 F2 F3 F4 F5 3. Press [F2], MOD_RNG, then [F2], BRANCH. The following menu display appears: 2.1.1.1.
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Chapter 7 Creating and Editing a Program File 6. First insert the examine if closed instruction with address B3/1, by pressing [F1], INS_INST, then [F1], BIT, then [F1], —] [— . 7. In the zoom display type the address B3/1, then press [ENTER], then, [F5], ACCEPT. The display appears as follows: 2.1.1.1.* I I I ] ] ] ] [ [ [ [ ]/[ ( ) ( ) I I I OFL ] [ ]/[ ( ) (L) (U) F1 F2 F3 F4 F5 > 8. Now insert the examine if closed instruction with address B3/2.
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Chapter 7 Creating and Editing a Program File Extending a Branch Down Use the extend branch down command to create a new branch level on an existing branch, below your cursor location. The new branch shares the same start and target locations as the branch on which the cursor is located. In this example, modify rung 1 of your program to appear as follows: O:3.0 ( ) 1 I:1.0 ] [ 0 B3 ] [ B3 ] [ 1 2 I:1.0 ] [ 1 Add this branch level to the rung. B3 ] [ 3 1.
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Chapter 7 Creating and Editing a Program File 3. Press [F2], MOD_RNG, then [F2], BRANCH. The following menu display appears: 2.1.1.2.* I I I ] ] ] ] [ [ [ [ ( ) ( ) I I I ]/[ ] [ EXT_UP F1 EXT_DWN APP_BR F2 F3 INS_BR F4 OFL DEL_BR F5 4. Press [F2], EXT_DWN. The display changes as follows: 2.1.1.3.* I I I I ] ] ] ] [ [ [ [ EXT_UP F1 ( ) ( ) I I I OFL I ]/[ ] [ EXT_DWN APP_BR F2 F3 INS_BR F4 DEL_BR F5 5. Press [ESC]. The proper menu is displayed: 2.1.1.3.
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Chapter 7 Creating and Editing a Program File Appending a Branch Use the append branch command to place the start of a branch to the right of the cursor location. In this example, you use the append branch command to create a parallel output branch. Modify rung 1 of your program to appear as follows: O:3.0 ( ) 1 I:1.0 ] [ 0 B3 ] [ O:3.0 ( ) 2 B3 ] [ 1 2 Add this branch to the rung. I:1.0 ] [ 1 B3 ] [ 3 1.
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Chapter 7 Creating and Editing a Program File 4. Press [F3], APP_BR. The following display appears: 2.1.1.0.* I I I I ] ] ] ] ] [ [ [ [ [ ( ) ( ) I I I I ]/[ ] [ SELECT BRANCH TARGET, PRESS ENTER F1 F2 F3 F4 OFL F5 5. Press the [→] key once to place the cursor to the right of the output. 2.1.1.0.6 I I I I ] ] ] ] ] [ [ [ [ [ ( ) ( ) I I I I ]/[ ] [ SELECT BRANCH TARGET, PRESS ENTER F1 F2 F3 F4 OFL F5 6. Press [ENTER]. The branch is placed around the output: 2.1.1.1.
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Chapter 7 Creating and Editing a Program File 8. To enter the output energize instruction, press [F1], INS_INST, then [F1], BIT, then [F3], —( )— . 9. In the zoom display, type the address O:3/2, then [ENTER], and [ACCEPT]. The display appears as follows: 2.1.1.1.7 I I I I ] [ ] [ ] [ ] [ ] [ ] [ ]/[ ]/[ ( ) (L) F1 F2 F3 F4 ] [ ( ) ( ) I ( ) I I OFL I (U) > F5 10. Press [ESC] twice to return to the proper menu. Then press [F5], ACP_RNG. 11. Save the changes.
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Chapter 7 Creating and Editing a Program File 1. From the previous save and continue display, press [ENTER] for the main editing display menu: 2.0.0.0.* ] ] ] ] ] [ [ [ [ [ ( ) ( ) ( ) ]/[ ] [ OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG > F1 F2 F3 F4 F5 2. Press the [↓] key to position the cursor on rung 1, then press [F2], MOD_RNG. The following display appears with the cursor positioned on the left power rail of rung 1: 2.1.0.0.
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Chapter 7 Creating and Editing a Program File 5. Press [F5], DEL_BR. The following display cautions you that address references on this branch remain in their last state (either energized or de–energized) when you delete the instructions. 2.1.1.1.
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Chapter 7 Creating and Editing a Program File Deleting an Instruction Modify your program to appear as follows: I:1.0 I:1.0 ] [ ] [ 1 0 I:1.0 ] [ 0 I:1.0 ] [ 1 O:3.0 ( ) 0 O:3.0 ( ) 1 O:3.0 ( ) 2 1. From the previous save and continue display, press [ENTER] for the main editing display menu: 2.0.0.0.* ] [ ] [ ] [ ]/[ ( ) ( ) ( ) OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG > F1 F2 F3 F4 F5 2. Press the [→] key twice to place the cursor on the instruction to be deleted. Then press [F2], MOD_RNG.
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Chapter 7 Creating and Editing a Program File Copying an Instruction from One Location to Another Use the delete instruction command in conjunction with the undelete instruction command to copy an instruction from one location to another, within the same rung or to a different rung. 1. To copy the examine if closed instruction with address I:1.
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Chapter 7 Creating and Editing a Program File 6. Press [F4], UND_INST, then [ENTER], then [F5], ACP_RNG. The examine if closed instruction is now pasted into rung 0. 2.1.0.0.* ] [ ] [ ] [ ( ) ( ) ( ) ] [ OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG > F1 F2 F3 F4 F5 7. To confirm this, press the [↑] key, then the [→] key twice. The display shows you that the examine if closed instruction with address I:1.0/1 is now the second instruction in rung 0. XIC:I1:1.0/1 ] [ ] [ ] [ NO FORCE 2.0.0.0.
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Chapter 7 Creating and Editing a Program File 2. Confirm the deletion by pressing [F2], YES. 3. Rung 0 is now placed in the delete buffer. Re–insert the rung by pressing [F5], UND_RNG. 4. Copy the rung before the END statement. Position the cursor on the END statement by pressing the [↓] key twice. The undelete rung command functions the same as the insert rung command, the new rung is inserted above the rung that the cursor is positioned on. 5. Press [F5], UND_RNG.
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Chapter 7 Creating and Editing a Program File 8. Press [F2], MOD_RNG, then [F3], MOD_INST, then [ZOOM]. The zoom display for that instruction appears: 2.2.0.0.1 ] [ ZOOM on XIC NAME: EXAMINE IF CLOSED BIT ADDR:I1:1.0/0 ENTER BIT ADDR: EDT_DAT F1 F2 I1:1.0/0 F3 F4 ACCEPT F5 9. To change the address to I:1.0/3, press the [→] key seven times to position the cursor on the bit element. 10. Press [3], then [ENTER], then [F5], ACCEPT. The new address is assigned to the instruction. NO FORCE XIC:I1:1.
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Chapter 7 Creating and Editing a Program File 12. Since you are assigning an input address from a different slot, press the [→] key three times, then press [2]. Press the [→] key three more times, then press [0], then [ENTER]. Verify that the new address is correct, then press [F5], ACCEPT. 13. Press the [→] key, then [ZOOM] to change the output address. The zoom display for the output energize instruction appears: ( ) ZOOM on OTE NAME: OUTPUT ENERGIZE BIT ADDR: O0:3.0/0 ENTER BIT ADDR: EDT_DAT F1 F2 2.
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Chapter 7 Creating and Editing a Program File The Search Function The search function allows you to quickly locate instructions and addresses in ladder program files. This section shows you how to search for: • instruction types, such as XIC • addresses, such as I:1/2 • combined instruction/address, such as OTE + O:3/4 • forced I/O instructions • a specific rung The HHT search function is done only within the existing program file.
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Chapter 7 Creating and Editing a Program File The following is a list of the search commands available on the HHT: Function Key [F1], CURSOR–INSTRUCTION [F2], CURSOR–OPERAND [F3], NEW–INSTRUCTION [F4], UP/DOWN [F5], FORCE Description Searches for all instructions that are the same type as the instruction that the cursor is positioned on. Searches for every instruction that contains the address associated with the instruction that the cursor is positioned on.
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Chapter 7 Creating and Editing a Program File Searching for an Instruction In this example, search for every examine if closed instruction (XIC) in the program, regardless of address. A search can be initiated with the cursor located anywhere in the program. In this example, the cursor is located on the left power rail of rung 0. 1. Start at the offline edit file display: 2.0.0.0.* ] ] ] ] ] [ [ [ [ [ ( ( ( ( ( ] [ ] [ ] [ ) ) ) ) ) OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG > F1 F2 F3 F4 F5 2.
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Chapter 7 Creating and Editing a Program File 4. To find the next occurrence of the same instruction, press [ENTER]. The following display appears with the cursor positioned on the second examine if closed instruction in rung 0. Once again, notice that the display shows the instruction mnemonic and address in the upper left corner, and the cursor location in the upper right corner. Instruction Mnemonic and Address XIC:I1:1.0/1 ] ] ] ] ] [ [ [ [ [ NO FORCE 2.0.0.0.
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Chapter 7 Creating and Editing a Program File 2. Press [F3], SEARCH. The search display appears: 2.0.0.0.* ] ] ] ] ] [ [ [ [ [ ( ( ( ( ( ] [ ] [ ] [ + CUR–INS CUR–OPD NEW–INS F1 F2 F3 UP F4 ) ) ) ) ) OFL FORCE F5 3. To search for the specific address, press [SHIFT], then type the abbreviated form of the address, I:1/1. Then press [ENTER] to place the address into the search buffer: 2.0.0.0.* The address is displayed in the search buffer.
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Chapter 7 Creating and Editing a Program File 6. Press [ENTER] again. The cursor wraps around to the beginning of the program and locates the cursor on the previous occurrence of the address, in rung 0: XIC:I1:1.0/1 ] ] ] ] ] [ [ [ [ [ NO FORCE 2.0.0.0.2 ( ( ( ( ( ] [ ] [ ] [ + I:1/1 CUR–INS CUR–OPD NEW–INS F1 F2 F3 UP F4 ) ) ) ) ) OFL FORCE F5 7. Exit the search. Press [ESC].
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Chapter 7 Creating and Editing a Program File 3. Press [F3], NEW–INS, then [F1], BIT, then [F3], —( )— , then [ENTER]. The following display appears, with the instruction mnemonic displayed in the search buffer: 2.0.0.3.* Instruction Mnemonic for the Output Energize Instruction ] ] ] ] ] [ [ [ [ [ ( ( ( ( ( ] [ ] [ ] [ OTE + CUR–INS CUR–OPD NEW–INS F1 F2 F3 UP F4 ) ) ) ) ) OFL FORCE F5 4. To enter the address, press [SHIFT], then type the abbreviated address O:3/4.
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Chapter 7 Creating and Editing a Program File To change the search direction, press [F4], UP. The display changes as follows: 2.0.0.0.* ] ] ] ] ] [ [ [ [ [ ( ( ( ( ( ] [ ] [ ] [ + CUR–INS CUR–OPD NEW–INS F1 F2 F3 DOWN F4 ) ) ) ) ) OFL FORCE F5 With DOWN displayed, the search starts at the cursor location, in this case at the start of the program, wraps around to the end of the program and continues toward the start of the program.
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Chapter 7 Creating and Editing a Program File In this example, a force has been inserted into the ladder program on input I1:1.0/0. Start from the offline edit file display with the cursor positioned on the left power rail of rung 0: 2.0.0.0.* ] ] ] ] ] [ [ [ [ [ ( ( ( ( ( ] [ ] [ ] [ ) ) ) ) ) OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG > F1 F2 F3 F4 F5 1. To search for any forces, press [F3], SEARCH. The search display appears: 2.0.0.0.
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Chapter 7 Creating and Editing a Program File Searching for Rungs You can search for a specific rung number by using the rung key located at the lower right corner of the keypad: F1 N F3 F2 S I O U PRE/LEN ACC/POS F4 SPACE ESC ZOOM A 7 B 8 C 9 D 4 E 5 F 6 T 1 R 2 M 3 RUNG # 0 – . SHIFT : / F5 Press [RUNG], type the desired rung number, and then press [ENTER].
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Chapter 7 Creating and Editing a Program File 3. Type 3, then press [ENTER]. The cursor is now positioned on the left power rail of rung 3. 2.3.0.0.* ] [ ( ) ] [ OFL INS_RNG MOD_RNG SEARCH DEL_RNG UND_RNG > F1 F2 F3 F4 F5 4. To search for additional rungs, repeat steps 1 through 3. Creating and Deleting Program Files The memory map function also allows you to create and delete data elements and files.
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Chapter 7 Creating and Editing a Program File 2. To create elements N7:0 through N7:12, press [F1], CRT_DAT, type N7:12 and press [ENTER]. The following display appears: File 7 8 0 1 2 Type LastAddr Elements N integer N7:12 13 Reserved – – O output O0:3.0 1 I input I1:2.0 2 S status S2:15 16 CRT DT F1 DEL DT NEXT PG F2 F3 Words 13 – 1 2 16 OFL PREV PG PRG SIZE F4 F5 The memory map indicates that the integer (N) file 7 size is 13 elements (equivalent to 13 words) and the last address is N7:12.
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Chapter 8 Saving and Compiling a Program This chapter discusses the procedures used to save and compile ladder programs. Topics include: • save and continue editing • save and exit offline editing • view memory layout Saving and Compiling Overview When you are entering a new program or editing an existing program, the ladder program is stored in the work area of the HHT. After completing your editing session, you must save your program to the HHT RAM memory.
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Chapter 8 Compiling and Saving a Program 2. To save this program and continue editing, press [F4], SAVE_CT. To save this program and exit offline editing, press [F5], SAVE_EX.
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Chapter 8 Compiling and Saving a Program If you selected SAVE_CT, you are returned to the editing display when the compile and save is complete.
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Chapter 8 Compiling and Saving a Program [F2] Test Single Rung (SLC 5/02 Specific) This option allows you to execute your program one rung at a time or a section at a time. Use this function for debugging purposes. Enable: When selected the size of your program increases by 0.375 instruction words per rung. Disable: Test Single Rung is not available. This is the default selection. Important: The HHT can save the program enabling Test Single Rung; however, the Test Single/Rung mode is available with APS.
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Chapter 8 Compiling and Saving a Program Viewing Program Memory Layout The memory map function allows you to view your program memory layout. It shows you the type and size of the data files used. It also gives you a summary of the number of the program files created and the number of instructions used in them. Lastly, it shows you how much user memory is left.
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Chapter 8 Compiling and Saving a Program ––––––––––––– MEMORY LAYOUT ––––––––––––– 1 output 20 data words used 2 input 16 status 1 bit 90 instruction words (ladder program and overhead) 20 4 = 5 instruction words (data) + 90 instruction words (ladder) 95 instruction words 1024–95 = 929 words left If you had not saved your program after adding or deleting program files, or modifying data files, the following display appears with asterisks (*) indicating that the program has not been compiled.
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Chapter 9 Configuring Online Communication This chapter describes online communication between the HHT and SLC 500 processors. Topics include: • online configuration • the Who function Online Configuration As described in chapter 1, the HHT may be connected directly to a port located on an SLC 500 processor or it may be connected to any fixed, SLC 5/01, or SLC 5/02 processor that is active on a DH–485 network. Important: The HHT is not compatible with the SLC 5/03 processor.
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Chapter 9 Configuring Online Communication To configure your HHT for online communication, begin at the main menu display of the HHT. SLC 500 PROGRAMMING SOFTWARE Rel. 2.03 1747 – PTA1E Allen–Bradley Company Copyright 1990 All Rights Reserved PRESS A FUNCTION KEY SELFTEST TERM PROGMAINT F1 F2 F3 OFL UTILITY F4 F5 Press [F5], UTILITY.
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Chapter 9 Configuring Online Communication Because the program files match, there are 2 menu screens and 10 function keys. The greater than sign (>), in the lower right corner of the display, indicates that a second function key menu is available. The following functions are available to you: Function Key Description [F1], OFFLINE Returns you to the utility menu display. [F2], UPLOAD Reads the program from the processor RAM and copies it to the HHT RAM.
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Chapter 9 Configuring Online Communication Another exception is when the processor contains the default program.
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Chapter 9 Configuring Online Communication The following functions are available from the Who display: Function Key [F1], DIAGNSTC [F3], ATTACH Description Allows you to monitor the status of the network or the selected node. Initiates communication with the selected node for uploading/downloading a program, changing the processor operating mode, clearing processor memory, changing processor password/master password, monitoring a program, viewing or modifying data files, or clearing the processor memory.
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Chapter 9 Configuring Online Communication Diagnostics 1. To monitor the diagnostics of the network or the selected node, press [F1], DIAGNSTC from the Who display. The following display appears: Node Addr. 2 3 4 0 Node Addr: 2 NODE F1 Device Max Addr./Owner 5/02 (31) 500–20 (31) 5/01 (31) APS (31) Baud Rate: 19200 OFL NETWORK F2 F3 F4 F5 2. To monitor the diagnostic display of the selected node press [F1], NODE.
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Chapter 9 Configuring Online Communication Attach The Attach function initiates communication between the HHT and a processor.
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Chapter 9 Configuring Online Communication Because the program files match, there are 2 menu displays and 10 function keys. The greater than sign (>), in the lower right corner of the display, indicates that a second function key menu is available. At this point, all the functions listed on page 9–3 are available to you. Return to the utility display by pressing [F1], OFFLINE or press [ESC], then [F2], YES. Exception The function keys and menus vary depending on how the HHT and processor programs relate.
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Chapter 9 Configuring Online Communication Begin at the WHO display. Press[F4], NODE_CFG. Node Addr. 2 3 4 0 Node Addr: Device Max Addr./Owner 5/02 (31) 500–20 (31) 5/01 (31) APS (31) 2 Baud Rate: 19200 OFL CHG_ADDR MAX_ADDR BAUD F1 F2 F3 F4 F5 The following functions are available from this menu: Function Key Description [F1], CHG_ADDR Allows you to change the node address of your HHT or the node address of any active processor on the DH–485 network.
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Chapter 9 Configuring Online Communication Entering a Maximum Node Address You may change the maximum node address for your HHT and any active processors on the DH–485 network. However, you cannot alter the value on another programming device. For the most efficient network operation, it is best to set the maximum node addresses of all devices on the DH–485 network to the lowest available value. The default maximum node address for all SLC 500 family processors and programming devices is 31.
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Chapter 9 Configuring Online Communication When the owner exits the network or goes offline, another terminal can clear the ownership of the inactive node and gain access to an owned processor file. In this example, the SLC 5/02 processor with node address 5 is owned by the APS terminal with address 0, which is no longer online. Clear node 0’s ownership of the processor and set the HHT, node 1, as owner of node 5. 1. Begin at the Who display.
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Chapter 9 Configuring Online Communication Recommendations When Using DH–485 Devices The following summarizes the recommendations for a DH–485 network. • Use node 0 (default) and the lowest node numbers for the programming device(s). • Number the processor nodes consecutively, beginning at the lowest possible number. • When establishing a multi–node network, keep in mind that the default node address for a processor is 1.
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Chapter 10 Downloading/Uploading a Program This chapter discusses how to: • download a program from the HHT to a processor • upload a program from a processor to the HHT➀ Downloading a Program When you have finished creating your program offline, you must download it from the HHT to a processor. In this example you will download program 1000, that you created in the previous chapters. 1. Start at the main menu: SLC 500 PROGRAMMING SOFTWARE Rel. 2.
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Chapter 10 Downloading/Uploading a Program In this example assume that the HHT has not been previously attached to a processor. 3. Press [F2], WHO. 4. Use the [↑] and [↓] keys to display node 4 as the current node. The display should appear as follows: Node Addr. 4 5 1 3 Node Addr: DIAGNSTC F1 Device 5/01 5/02 TERMINAL 500–20 4 Max Addr./Owner (5) (5) (5) (5) Indicates that node 4 is the current node. Baud Rate: 19200 OFL ATTACH NODE_CFG OWNER F2 F3 F4 F5 5. Press [F3], ATTACH.
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Chapter 10 Downloading/Uploading a Program 6. Press [F3], DWNLOAD. The following display appears: Program Directory Programmer Processor Prog: 1000 Prog: 1952 File: 222 File: Exec Files: 4 Exec Files: Data Files: 9 Data Files: DOWNLOAD TO PROCESSOR? PRG YES NO F1 F2 F3 F4 3 9 F5 7. Press [F2], YES to confirm. If necessary, the HHT requests you to compile the program.
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Chapter 10 Downloading/Uploading a Program In this example you will upload program 03CLOCK stored in processor node 3. The processor can be in any mode to upload a program. 1. Start at the main menu display: SLC 500 PROGRAMMING SOFTWARE Rel. 2.03 1747 – PTA1E Allen–Bradley Company Copyright 1990 All Rights Reserved PRESS A FUNCTION KEY SELFTEST TERM PROGMAINT F1 F2 F3 OFL UTILITY F4 F5 2. Press [F5], UTILITY. The following display appears if a password is required: SLC 500 PROGRAMMING SOFTWARE Rel. 2.
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Chapter 10 Downloading/Uploading a Program 4. Press [F3], ATTACH.
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Chapter 11 Processor Modes This chapter describes the different operating modes a processor can be placed in while using the HHT. Available processor modes include: • Run • Program • Test The Test mode has the following options: – continuous scan – single scan Processor Modes Run Mode While in the Run mode, the processor scans or executes the ladder program and monitors input devices. It also energizes output devices and acts on enabled I/O forces.
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Chapter 11 Processor Modes Test Mode The Test mode allows you to: • Monitor the current ladder program as it is being executed. • Use the search function. • Force I/O. • Monitor and edit data. While you are in the Test mode, the processor scans or executes the ladder program, monitors input devices, and updates the output data files without energizing output circuits or devices.
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Chapter 11 Processor Modes 2. Press [F4], MODE. The following display appears: File Name: 222 File Name 0 1 2 222 3 RUN F1 F2 Prog Name:1000 Type Size(Instr) System 77 Reserved 0 Ladder 13 Ladder 1 PRG TEST PROGRAM F3 F4 F5 3. Change the processor to the Run mode by pressing [F1], RUN. The display requests you to confirm your selection: File Name: 222 File Name 0 1 2 222 3 ARE YOU SURE? YES F1 F2 Prog Name:1000 Type Size(Instr) System 77 Reserved 0 Ladder 13 Ladder 1 PRG NO F3 F4 F5 4.
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Chapter 12 Monitoring Controller Operation This chapter briefly describes monitoring controller operation. Topics include: • monitoring a program file • monitoring data files • monitoring data file displays • online data changes Monitoring a Program File The following demonstrates how to monitor a program file while online: 1.
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Chapter 12 Monitoring Controller Operations True/False Indication Once the processor is operating in the Run or Test mode, the ladder program indicates the logical state of the instructions, either true or false.
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Chapter 12 Monitoring Controller Operations Accessing Data Files There are four ways to access the data table: Option 1 While offline, press [F3], PROGMAINT, from the menu display, then [ENTER], and [F1], EDT_DAT. Option 2 While monitoring a program offline, press [ENTER] and [F1], EDT_DAT. Option 3 While online, press [ENTER] from the main online display, then [F4], EDT_DAT. Option 4 While monitoring a program online, press [F3], EDT_DAT.
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Chapter 12 Monitoring Controller Operations The following HHT display shows the ladder program being monitored in the online mode. The cursor is located on the XIC instruction C5:0/DN on rung 2. XIC:C5:0/13 ] ] ] ] ] 2.2.0.0.
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Chapter 12 Monitoring Controller Operations Data File Displays The following section provides you with an example of what each data table display appears as. The radix (or number system) that the file elements are displayed in is fixed: binary for Input, Output, and Bit files; decimal for Integer files; and formatted display for Status, Timer, Counter, and Control files. To access the data table, place the cursor on the left power rail in the online monitor display and press [F3], EDT_DAT.
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Chapter 12 Monitoring Controller Operations To display the next consecutive data file – the status data file, press [F2], NEXT_FL. Status Data File (S2) The status data file contains information about processor operation, diagnostics, memory module loading, fault codes, etc. The displays below show the 16–word status file for a fixed controller or a SLC 5/01 processor. To move between displays, press [F3], NEXT_PG.
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Chapter 12 Monitoring Controller Operations The displays below show the 33–word status file for a SLC 5/02 processor. To move between displays, press [F3], NEXT_PG. To display the next consecutive data file – the bit data file, press [F2], NEXT_FL.
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Chapter 12 Monitoring Controller Operations Bit Data File (B3) The display below shows the bit data file. Two elements are shown; B3:0 and B3:1. The cursor is located on bit B3/0. All bits are reset to zero. Address B3:0 B3:1 15 data 0 0000 0000 0000 0000 0000 0000 0000 0000 B3/0 = 0 RUN ADDRESS NEXT FL PREV FL NEXT PG PREV PG F1 F2 F3 F4 F5 To display the next consecutive data file – the timer data file, press [F2], NEXT_FL. Timer Data File (T4) The display below shows the timer data file.
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Chapter 12 Monitoring Controller Operations Control Data File (R6) The display below show the control data file. The cursor is on the enable bit EN (bit 15) of control element R6:0. The control word bits EN, EU, DN, EM, ER, UL, IN, and FD (bits 15, 14, 13, 12, 11, 10, 9, and 8 respectively) are all reset. The length is 25 and the position is 0.
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Chapter 12 Monitoring Controller Operations To change online data, begin by monitoring the program online while the processor is in either the Run or Test Continuous Scan (CSN) mode. XIC:I1:1.0/0 ] ] ] ] ] NO FORCE 2.0.0.0.1 (CTU) [ [ [ [ [ MODE F1 ( ) ( ) ( ) FORCE F2 EDT_DAT F3 SEARCH F4 (RES) RUN F5 Observe the following: • XIC instruction C5:0/15 (count–up bit) and rung 1 are true whenever rung 0 is true, and false whenever rung 0 is false.
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Chapter 12 Monitoring Controller Operations 3. Increment the counter by turning on I:1/0. The accumulator value equals the preset value, the done bit DN (bit 13) is set, and rung 2 is true. 4. Increment the counter again. The is in an overflow condition, setting the overflow bit OV (bit 12). Rung 3 in the ladder program is true.
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Chapter 13 The Force Function This chapter briefly describes the force function. Topics include: • forcing I/O • forcing an external input • searching for forced I/O • forcing an external output • forces carried offline Forcing I/O The force function allows you to override the actual status of external input circuits by forcing external input data file bits On or Off. You can also override the processor logic and status of output data file bits by forcing output circuits On or Off.
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Chapter 13 The Force Function Forcing an External Input Installing forces on input data file bits only affects the input force table. However, enabling the installed forces affects the input force table, input data file, and, thus, the program logic. The effects on the program logic of installed and enabled forces can be seen in both the Run and Test modes. In the following example, the HHT is online, monitoring the program in the Run mode. The cursor is located on external input I:0/1.
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Chapter 13 The Force Function Function Key Description [F1], ON Enters a 1 in the input force table for the cursored external input bit address. This installs a force. If the Enable function is in effect and the processor is in the Run or Test mode, the force is applied. The data file bit remains forced until: 1) the disable function is in effect, or 2) the force is removed. [F2], OFF Enters a 0 in the input force table for the cursored external input bit address. This installs a force.
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Chapter 13 The Force Function 4. To verify enabling of forces, press [F2]. The force is enabled. The letter F on the prompt line is now on continuously. Also, the FORCED I/O LED of the processor is on continuously. XIC: I1:0.0/1 ] [ ]/[ ]/[ ] [ ] [ ] [ ] [ ON F1 FORCE ON ] [ ]/[ OFF REM F2 F3 2.0.0.0.1 ( ) ( ) REM_ALL F4 ( ) ( ) F RUN DISABLE F5 Rungs 1, 2, and 3 have gone true, as indicated by highlighted (bold) instructions in the display. Note that the output 0 LED of the controller is on.
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Chapter 13 The Force Function 3. Press [F2], OFF. All rungs are false. Program operation is back to the starting point. The display shows FORCE OFF, but the force is still enabled. XIC: I1:0.0/1 ] [ ]/[ ]/[ ] [ ] [ ] [ ] [ ON F1 FORCE OFF ] [ ]/[ OFF REM F2 F3 2.0.0.0.1 ( ) ( ) REM_ALL F4 ( ) ( ) F RUN DISABLE F5 To disable and/or remove forces, you can select DISABLE, REM, or REM ALL. 4. Remove the force by pressing [F3], REM. NO FORCE indicates the force is removed and disabled.
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Chapter 13 The Force Function Searching for Forced I/O To search for forced I/O, you can have the cursor located anywhere in the program at the beginning of the search. In the following display, the cursor is located in rung 0, on a forced instruction. The force is enabled. 1. Set up these initial conditions (a repeat of what was done on page 13–2). XIC: I1:0.0/1 ] [ ]/[ ]/[ ] [ ] [ ] [ ] [ FORCE ON ] [ ]/[ 2.0.0.0.1 ( ) ( ) ( ) ( ) F RUN MODE FORCE EDT DAT SEARCH F1 F2 F3 F4 F5 2.
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Chapter 13 The Force Function 4. Press [ENTER]. As the display shows, the next occurrence of a forced instruction is found in rung 1. XIC: I1:0.0/1 ] [ ]/[ ] [ ] [ ] [ FORCE ON ] [ 2.0.0.0.1 ( ) ( ) ( ) ENTER TO FIND FORCE F1 F2 F F3 UP F4 RUN F5 5. Press [ENTER]. The display indicates the next occurrence of a forced instruction, in rung 2. XIC: I1:0.0/1 FORCE ON 2.0.0.0.1 ] [ ] [ ( ) ( ) ENTER TO FIND FORCE F1 F2 F F3 UP F4 RUN F5 6. Press [ENTER].
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Chapter 13 The Force Function Forcing an External Output A forced external output circuit is independent of the internal logic of the ladder program and the output data file. Installing forces on output circuits only affects the output force table. Enabling installed forces does not affect the output data file or the program logic. However, it does affect the output circuit. The effects of installed and enabled forces can only be seen in the Run mode. The Test mode does not energize output circuits.
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Chapter 13 The Force Function The following display shows output O:0/0 forced on. The controller output LED is on, yet the rung and output data file show the output to be logically false. OTE: O0:0.0/1 ] [ ]/[ ] [ ] [ ] [ FORCE ON ]/[ 2.3.0.0.
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Chapter 14 Using EEPROMs and UVPROMs This chapter describes: • using an EEPROM memory module • EEPROM burning options • using a UVPROM memory module Using an EEPROM Memory Module You can transfer a program from the processor to an EEPROM and vice versa. The procedures are similar. • Make sure the EEPROM is installed in the processor. Disconnect controller power and insert the EEPROM in the processor.
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Chapter 14 Using EEPROMs and UVPROMs 5. Press [ENTER] to view the remaining menu selections: File Name: 222 File Name 0 1 2 222 3 PASSWRD F1 F2 Prog Name:1000 Type Size(Instr) System 77 Reserved 0 Ladder 13 Ladder 1 PRG XFERMEM EDT_DAT MONITOR> F3 F4 F5 6. Press [F3], XFERMEM. File Name: 222 File Name 0 1 2 222 3 MEM_PRC F1 F2 Prog Name:1000 Type Size(Instr) System 77 Reserved 0 Ladder 13 Ladder 1 PRG PRC_MEM F3 F4 F5 Choices are memory to processor (MEM_PRC) and processor to memory (PRC_MEM). 7.
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Chapter 14 Using EEPROMs and UVPROMs Transferring a Program from an EEPROM Memory Module 1. Establish online communication with the processor. Refer to chapter 9. 2. Change the processor mode to Program. Refer to chapter 11. 3. If the DEFAULT file is in the processor, continue to step 4. If the processor and HHT programs do not match, upload or download to make the programs match. (Refer to chapter 10.) Proceed to step 7. 4.
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Chapter 14 Using EEPROMs and UVPROMs 7. To transfer a program from an EEPROM with matching programs in the HHT and the processor, begin at the following display: File Name: 222 File Name 0 1 2 222 3 OFFLINE F1 Prog Name:1000 Type Size(Instr) System 77 Reserved 0 Ladder 13 Ladder 1 PRG UPLOAD DWNLOAD MODE CLR_PRC> F2 F3 F4 F5 To view the remaining menu selections, press [ENTER].
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Chapter 14 Using EEPROMs and UVPROMs 10.Press [F2]. The prompt line indicates XFERRING MEMORY MODULE TO PROC momentarily, then returns to this display: Program Directory Programmer Processor Prog: 1000 Prog: 1066 File: 222 File: Exec Files: 4 Exec Files: 3 Data Files: 9 Data Files: 9 PROGRAM FILES DIFFER PRG OFFLINE UPLOAD DWNLOAD MODE CLR_PRC F1 F2 F3 F4 F5 A copy of the EEPROM program has been transferred to the processor.
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Chapter 14 Using EEPROMs and UVPROMs Burning EEPROMS for SLC Configurations If you have a SLC 5/02 processor or SLC 5/01 4k processor, you can burn EEPROMs for any fixed, SLC 5/01, or SLC 5/02 program. UVPROM Memory Modules You may choose to use UVPROM modules. These modules are protected against electrical erasure. You can transfer a program from the UVPROM to the processor, but you cannot transfer a program to the UVPROM.
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Chapter A–B 15 Instruction Set Overview This chapter: • takes a brief look at the instruction set • lists the name, mnemonic, and function of each instruction • points out the instructions that can be used only with SLC 5/02 processors Important: To avoid misapplication, do not apply any of the instructions until you have read the detailed descriptions in chapters 16 through 26. On page 15–9 you will find an Instruction Locator.
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Chapter 15 Instruction Set Overview Timer and Counter Instructions – Chapter 17 5/02 Only Instruction Name and Mnemonic 15–2 • Function – Output Instructions Timer On-Delay TON Counts time intervals when conditions preceding it in the rung are true. Produces an output when accumulated value (count) reaches preset value. Resets when rung is false (non–retentive). Timer Off-Delay TOF Counts time intervals when conditions preceding it in the rung are false.
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Chapter 15 Instruction Set Overview I/O Message and Communications Instructions – Chapter 18 5/02 Only Instruction Name and Mnemonic • Function – Output Instructions Immediate Input with Mask IIM When conditions preceding it in the rung are true, the IIM instruction is enabled and interrupts the program scan to read the status of a word of external inputs and transfer it through a mask to the input data file.
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Chapter 15 Instruction Set Overview Comparison Instructions – Chapter 19 5/02 Only Instruction Name and Mnemonic 15–4 • Function – Conditional Input Instructions Equal EQU Instruction is true when source A = source B. Not Equal NEQ Instruction is true when source A 0source B. Less Than LES Instruction is true when source A < source B. Less Than or Equal LEQ Instruction is true when source A < source B. Greater Than GRT Instruction is true when source A > source B.
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Chapter 15 Instruction Set Overview Math Instructions – Chapter 20 5/02 Only Instruction Name and Mnemonic • Function – Output Instructions Add ADD When rung conditions are true, the ADD instruction adds source A to source B and stores the result in the destination. Subtract SUB When rung conditions are true, the SUB instruction subtracts source B from source A and stores the result in the destination.
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Chapter 15 Instruction Set Overview Move and Logical Instructions – Chapter 21 5/02 Only Instruction Name and Mnemonic • Function – Output Instructions Move MOV When rung conditions are true, the MOV instruction moves a copy of the source to the destination. Masked Move MVM When rung conditions are true, the MVM instruction moves a copy of the source through a mask to the destination.
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Chapter 15 Instruction Set Overview Bit Shift, FIFO, and LIFO Instructions – Chapter 23 5/02 Only Instruction Name and Mnemonic Bit Shift Left Bit Shift Right Function – Output Instructions • BSL BSR On each false–to–true transition, these instructions load a bit of data into a bit array, shift the pattern of data through the array, and unload the end bit of data. The BSL shifts data to the left and the BSR shifts data to the right.
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Chapter 15 Instruction Set Overview Control Instructions – Chapter 25 5/02 Only Instruction Name and Mnemonic Jump to Label JMP Output instruction. When rung conditions are true, the JMP instruction causes the program scan to jump forward or backward to the corresponding LBL instruction. Label LBL Conditional instruction. This is the target of the correspondingly numbered JMP instruction. Jump to Subroutine JSR Output instruction.
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Chapter 15 Instruction Set Overview Proportional Integral Derivative Instruction – Chapter 26 5/02 Only Instruction Name and Mnemonic Proportional Integral Derivative Instruction Locator Function – Output Instruction • PID • This instruction is used to control physical properties such as temperature, pressure, liquid level, or flow rate of process loops. The table below lists instructions by mnemonic, in alphabetical order. Page references are included.
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Chapter A–B 16 Bit Instructions This chapter covers the bit instructions with fixed, SLC 5/01, and SLC 5/02 processors: • Examine if Closed (XIC) • Examine if Open (XIO) • Output Energize (OTE) • Output Latch (OTL) • Output Unlatch (OTU) • One–Shot Rising (OSR) Bit Instructions Overview Bit instructions operate on a single bit of data. During operation, the processor may set or reset the bit, based on logical continuity of ladder rungs. You can address a bit as many times as your program requires.
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Chapter 16 Bit Instructions Examine if Closed (XIC) Examine if Closed XIC HHT Ladder Display: HHT Zoom Display: (online monitor mode) Input Instruction ] [ ZOOM on XIC –] [– 2.0.0.0.1 NAME: EXAMINE IF CLOSED BIT ADDR: I1:1.0/0 ***************0 EDT_DAT F1 Ladder Diagrams and APS Displays: Logic States: F2 F3 F4 F5 I:1.
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Chapter 16 Bit Instructions Examine if Open (XIO) Examine if Open XIO HHT Ladder Display: HHT Zoom Display: (online monitor mode) Input Instruction ]/[ ZOOM on XIO –]/[– 2.3.0.0.1 NAME: EXAMINE IF OPEN BIT ADDR: I1:1.0/0 ***************0 EDT_DAT F1 F2 F4 F5 I:1.
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Chapter 16 Bit Instructions Output Energize (OTE) Output Energize HHT Ladder Display: HHT Zoom Display: (online monitor mode) OTE Output Instruction ( ) ZOOM on OTE –( )– 2.3.0.0.2 NAME: OUTPUT ENERGIZE BIT ADDR: O0:2.0/7 ********0******* EDT_DAT F1 Ladder Diagrams and APS Displays: F2 F3 F4 F5 O:2.0 ( ) 7 Specific operation of an OTE instruction having an input data file address: The status of an output terminal is reflected in the output data file at a particular bit address.
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Chapter 16 Bit Instructions Output Latch (OTL), Output Unlatch (OTU) Output Latch, Output Unlatch HHT Ladder Display: HHT Zoom Display: (online monitor mode) (L) OTL, OTU Output Instruction (U) ZOOM on OTL –(L)– NAME: OUTPUT LATCH BIT ADDR: B3/6 2.3.0.0.2 *********0****** EDT_DAT F1 F2 F3 F4 F5 ZOOM on OTU –(U)– 2.4.0.0.
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Chapter 16 Bit Instructions When the processor changes from the Run to the Program mode or when power is lost (provided there is battery backup or the capacitor retains memory), the last true output latch or output unlatch instruction in the ladder program continues to control the bit in memory. The latched output device is energized even though the rung conditions controlling the output latch instruction may have gone false. ! ATTENTION: Physical outputs are turned off under processor fault conditions.
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Chapter 16 Bit Instructions One-Shot Rising (OSR) One–Shot Rising HHT Ladder Display: HHT Zoom Display: (online monitor mode) OSR Input Instruction OSR ZOOM on OSR –|OSR|– 2.3.0.0.2 NAME: ONE SHOT RISING BIT ADDR: B3/0 ***************0 EDT_DAT F1 Ladder Diagrams and APS Displays: F2 F3 F4 F5 B3 [OSR] 0 The OSR instruction is a retentive input instruction that triggers an event to occur one time.
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Chapter 16 Bit Instructions Fixed, SLC 5/01, SLC 5/02 Processors O:3.0 I:1.0 B3 ( ) ] [ [OSR] 0 0 0 When the input instruction goes from false–to–true, the OSR instruction conditions the rung so that the output goes true for one program scan. The output goes false and remains false for successive scans until the input makes another false–to–true transition. I:1.0 ] [ 0 TOD B3 [OSR] 0 TO BCD Source Dest T4:0.
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Chapter A–B 17 Timer and Counter Instructions This chapter covers the following timer and counter instructions for use with all processors except where noted: • Timer On-Delay (TON) • Timer Off-Delay (TOF) • Retentive Timer On-Delay (RTO) • Count Up (CTU) • Count Down (CTD) • High–Speed Counter (HSC) – fixed controller only • Counter or Timer Reset (RES) Timer and Counter Instructions Overview Timers and counters are output instructions. They include: • Timer On-Delay (TON).
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Chapter 17 Timer and Counter Instructions Preset and accumulated values for timers range from 0 to +32,767. If a timer preset or accumulated value is a negative number, a runtime error occurs and places the processor in a fault condition. Preset and accumulated values for counters range from –32,768 to +32,767. Indexed Word Addresses With SLC 5/02 processors, you have the option of referencing timer and counter preset and accumulated values in other areas of your program with indexed addressing.
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Chapter 17 Timer and Counter Instructions Timer On-Delay (TON) Timer On–Delay HHT Ladder Display: HHT Zoom Display: (online monitor mode) TON Output Instruction (TON) ZOOM on TON –(TON)– 2.0.0.0.2 NAME: TIMER ON DELAY TIMER: T4:0 TIME BASE .01 SEC PRESET: 120 ACCUM: 0 EN TT DN 0 0 0 EDT_DAT F1 Ladder Diagrams and APS Displays: F2 F3 F4 F5 TON TIMER ON DELAY Timer T4:0 Time Base 0.
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Chapter 17 Timer and Counter Instructions Timer Off-Delay (TOF) Timer Off–Delay HHT Ladder Display: HHT Zoom Display: (online monitor mode) TOF Output Instruction (TOF) ZOOM on TOF –(TOF)– 2.0.0.0.2 NAME: TIMER OFF DELAY TIMER: T4:1 TIME BASE .01 SEC PRESET: 120 ACCUM: 0 EN TT DN 0 0 0 EDT_DAT F1 Ladder Diagrams and APS Displays: F2 F3 F4 F5 TOF TIMER OFF DELAY Timer T4:1 Time Base 0.
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Chapter 17 Timer and Counter Instructions When you go back to the Run or Test mode, the following can happen: • If the rung is true, the accumulated value is reset, the timing bit is reset, the enable bit is set, and the done bit remains set. • If the rung is false, the accumulated value is set equal to the preset value and the control bits are reset. The counter/timer RES instruction cannot be used with the TOF instruction.
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Chapter 17 Timer and Counter Instructions Status Bits • The done bit (DN) is set when the accumulated value is equal to the preset value. However, it is not reset when rung conditions become false; it is reset only when the appropriate RES instruction is enabled. • The timing bit (TT) is set when rung conditions are true and the accumulated value is less than the preset value. It is reset when the rung conditions go false or when the done bit is set.
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Chapter 17 Timer and Counter Instructions Count Up (CTU) and Count Down (CTD) Count Up, Count Down HHT Ladder Displays: HHT Zoom Displays: (online monitor mode) CTU, CTD (CTU) Output Instructions (CTD) ZOOM on CTU –(CTU)– NAME: COUNT UP COUNTER: C5:0 PRESET: 120 ACCUM: 0 CU CD DN OV UN 0 0 0 0 0 EDT_DAT F1 F2 F3 2.3.0.0.2 F4 ZOOM on CTD –(CTD)– NAME: COUNT DOWN COUNTER: C5:1 PRESET: 120 ACCUM: 0 CU CD DN OV UN 0 0 0 0 0 EDT_DAT F1 F2 F3 F5 2.4.0.0.
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Chapter 17 Timer and Counter Instructions Status Bits The control word for counter instructions includes six status bits, indicated in the figure below. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 CU CD DN OV UN UA Not Used Preset Value Accumulated Value CU CD DN OV UN UA = = = = = = Counter up enable bit Counter down enable bit Done bit Overflow bit Underflow bit Update accumulator (HSC only) Counter preset and accumulated values are stored as signed integers.
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Chapter 17 Timer and Counter Instructions CTD instructions also count false-to-true rung transitions. The counter accumulated value is decremented one count for each false-to-true transition. When a sufficient number of counts has occurred and the accumulated value becomes less than the preset value, the counter done bit (bit 13) is reset. Bit 14 of the counter control word is the count down enable (CD) bit. It is set when rung conditions of the CTD instruction are true.
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Chapter 17 Timer and Counter Instructions Important: This instruction provides high–speed counting on fixed controllers with 24 VDC inputs. One HSC instruction allowed per controller. To use the instruction, you must clip a jumper as described in the installation manual, catalog number 1747–NI002. Input I:0/0 then operates in the high–speed mode. The address of the high–speed counter enable bit is C5:0/CU. When rung conditions are true, C5:0/CU is set and transitions occurring at input I:0/0 are counted.
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Chapter 17 Timer and Counter Instructions The HSC’s status bits and accumulator are non-retentive. At power-up or Run mode entry, the HSC instruction will clear the status bits, clear the accumulator, and load the preset value. Instruction Parameters Address C5:0 is the HSC counter 3-word element.
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Chapter 17 Timer and Counter Instructions Program File 2 – Poll for DN Bit in Main Program File Rung ] [ 6 31 JSR JUMP TO SUBROUTINE SBR file number 3 ]/[ JSR JUMP TO SUBROUTINE SBR file number 3 ]/[ ( ) ] [ JSR C5:0 ] [ DN ] [ ( ) ] [ C5:0 ] [ DN ] [ ( ) ] [ C5:0 ] [ DN ] [ 16 ]/[ JUMP TO SUBROUTINE SBR file number 3 ]/[ ( ) ] [ Program File 3 – Execute HSC Logic Rung 0 1 SBR SUBROUTINE ] [ ]/[ ] [ ( ) HSC Application Logic ( ) ] [ Unlatch DN Bit C5:0 (U) DN 20 RET 21
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Chapter 17 Timer and Counter Instructions Reset (RES) Reset RES HHT Ladder Displays: (RES) HHT Zoom Displays: (online monitor mode) ZOOM on RES –(RES)– NAME: RESET COUNTER: C5:0 Output Instruction 2.3.0.0.2 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: C5:0 (RES) You use a reset instruction to reset timing and counting instructions.
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Chapter A–B 18 I/O Message and Communication Instructions This chapter discusses the following output instructions.
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Chapter 18 I/O Message and Communication Instructions This is an output instruction that allows you to transfer data from one node to another on the DH–485 network. The instruction can be programmed as a write message or read message. The target device can be another SLC 500 processor on the network, or a non-SLC 500 device, using the common interface file (data file 9 in SLC 500 processors).
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Chapter 18 I/O Message and Communication Instructions Available Configuration Options The following configuration options are available with a SLC 5/02 processor: • Peer–to–Peer Write on a local network to another SLC 500 processor • Peer–to–Peer Read on a local network to another SLC 500 processor • Peer–to–Peer Write on a local network to a 485CIF (PLC2 emulation) • Peer–to–Peer Read on a local network to a 485CIF (PLC2 emulation) Entering Parameters After you select the MSG instruction on the HHT, the d
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Chapter 18 I/O Message and Communication Instructions After you make a selection [F2] or [F4], the display changes to the following: 3. Enter Control Block – ZOOM on MSG –(MSG)– 2.0.0.0.* NAME: MESSAGE READ/WRITE MSG TYPE: WRITE LD/LS ADDR: TARGET: 500 CPU TARG NODE: 0 CTRL BLK: TARG OS/AD: CTRL BLK 7 WORDS MSG LEN: 0 ENTER CONTROL BLK: F1 F2 F3 F4 F5 This is an integer file address that you select.
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Chapter 18 I/O Message and Communication Instructions After you enter an address, the display changes to the following. 5. Target Node – ZOOM on MSG –(MSG)– 2.0.0.0.* NAME: MESSAGE READ/WRITE MSG TYPE: WRITE LD/LS ADDR:N7:40 TARGET: 500 CPU TARG NODE: 0 CTRL BLK: N7:0 TARG OS/AD: CTRL BLK 7 WORDS MSG LEN: 0 TARGET NODE:0 F1 F2 F3 F4 F5 This is the node number of the device that the local processor is reading or writing to. After you enter a node number, the display changes to the following. 6.
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Chapter 18 I/O Message and Communication Instructions After you enter an address, the display changes to the following. 7. Enter Message Length – ZOOM on MSG –(MSG)– 2.0.0.0.* NAME: MESSAGE READ/WRITE MSG TYPE: WRITE LD/LS ADDR:N7:40 TARGET: 500 CPU TARG NODE: 5 CTRL BLK: N7:0 TARG OS/AD:N7:6 CTRL BLK 7 WORDS MSG LEN: 0 ENTER MESSAGE LENGTH:0 F1 F2 F3 F4 F5 This is the length of the message in elements. The 1–word elements are limited to a maximum length of 41.
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Chapter 18 I/O Message and Communication Instructions Control Block Layout The control block layout if you select 500 CPU as the target device: Control Block Layout – 500 CPU 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 EN ST DN ER EW NR TO Error Code Target Device Node Number Word 0 1 Reserved for message length in words 2 Target Address File Number 3 Target File Type (S, B, T, C, R, N) Code 4 Target Address Element Number 5 Reserved 6 The control block layout if you select 485 CIF as th
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Chapter 18 I/O Message and Communication Instructions When you are online, you can locate the cursor on the MSG instruction, press the Zoom key, and observe the current status of some of these bits: ZOOM on MSG –(MSG)– 2.0.0.0.2 NAME: MESSAGE READ/WRITE MSG TYPE: WRITE LD/LS ADDR:N7:40 TARGET: 500 CPU TARG NODE: 5 CTRL BLK: N7:0 TARG OS/AD:N7:6 EN ST DN ER NR TO MSG LEN: 2 0 0 0 0 0 0 EDT_DAT F1 F2 F3 F4 F5 Successful MSG Instruction Timing Diagram Target node Rung goes True. receives packet.
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Chapter 18 I/O Message and Communication Instructions MSG Instruction Error Codes When an error condition occurs, the error bit ER is set. The lower byte of the first word in the control block indicates the type of error: Error Code (decimal) Error Code (binary) Error Code (hex) 2 0000 0010 02H Target node is busy. The MSG instruction will automatically reload. If other messages are waiting, the message is placed at the bottom of the stack.
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Chapter 18 I/O Message and Communication Instructions To view a MSG instruction error code when troubleshooting, add a MVM instruction to the program as shown in the example below. This example assumes the control block is an integer file. MVM Source Dest Mask N7:0 0OFF B3:0 Application Examples 1. Application example 1 is shown below. It indicates how you can implement continuous operation of a message instruction. 2. Application example 2 begins on page 18–11 through 18–12.
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Chapter 18 I/O Message and Communication Instructions Example 2 – Program File 2 of SLC 5/02 Processor Temperature–sensing Input Device 0 I:1.0 ] [ 5 N7:0 ( ) 1 1 S:1 ] [ 15 T4:0 (RES) N7:0 (L) 0 First Pass Bit Bit 1 of the message word. Used for fan control. Bit 0 of the message word. This is the interlock bit. B3 (U) 0 TON TIMER ON DELAY Timer T4:0 Time Base 0.
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Chapter 18 I/O Message and Communication Instructions Example 2 – Program File 2 of SLC 5/01 Processor at Node 3 0 N7:0 (U) 0 S:1 ] [ 15 First Pass Bit Bit 0 of the message word. This is the interlock bit. T4:0 (RES) TON TIMER ON DELAY Timer T4:0 Time Base 0.01 Preset 400 Accum 0 1 Bit 1 of the message word. Used for fan control.
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Chapter 18 I/O Message and Communication Instructions Example 3 0 1 [LBL] B3 ] [ 1 1 B3 ] [ 1 T4:0 ]/[ DN 2 T4:0 ] [ DN B3/1 is latched to initiate the message instruction. 3 MSG READ/WRITE MESSAGE Read/write WRITE Target Device 500CPU Control Block N7:0 Control Block Length 7 (EN) (DN) (ER) TON TIMER ON DELAY Timer T4:0 Time Base 0.01 Preset 200 Accum 0 (EN) (DN) 2–second timer. Each attempt at transmission has a 2–second duration. (CU) Counter allows 5 attempts.
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Chapter 18 I/O Message and Communication Instructions Service Communications (SVC) SLC 5/02 Processors Only Service Communications HHT Ladder Display: HHT Zoom Display: (monitor mode) SVC Output Instruction (SVC) ZOOM on SVC –(SVC)– 2.0.0.0.1 NAME: SERVICE COMMUNICATIONS EDT_DAT F1 F2 Ladder Diagrams and APS Displays: F3 F4 F5 (SVC) The SVC instruction has no programming parameters.
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Chapter 18 I/O Message and Communication Instructions This example assumes that the Comms Servicing Selection bit S:2/15 is clear and that this is the only active MSG instruction. Important: You may program the SVC instruction unconditionally. Immediate Input with Mask (IIM) Immediate Input with Mask IIM Output Instruction HHT Ladder Display: (IIM) HHT Zoom Display: (online monitor mode) ZOOM on IIM –(IIM)– 2.0.0.0.1 NAME: IMMEDIATE INPUT w/ MASK SLOT: I1:4.
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Chapter 18 I/O Message and Communication Instructions MASK: Specify a Hex constant or register address. Refer to appendix B for information regarding masks and hexadecimal numbering. Immediate Output with Mask (IOM) Immediate Output with Mask IOM Output Instruction HHT Ladder Display: (IOM) HHT Zoom Display: (online monitor mode) ZOOM on IOM –(IOM)– 2.0.0.0.1 NAME: IMMEDIATE OUTPUT w/ MASK SLOT: O0:3.
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Chapter 18 I/O Message and Communication Instructions MASK: Specify a Hex constant or register address. Refer to appendix B for information regarding masks and hexadecimal numbering. I/O Event-Driven Interrupts SLC 5/02 Processors Only I/O Interrupt Disable I/O Interrupt Enable Reset Pending I/O Interrupt HHT Ladder Display: IID IIE RPI Output Instruction Output Instruction Output Instruction (IID) HHT Zoom Display: (monitor mode) (IIE) (RPI) ZOOM on IID –(IID)– 2.4.0.0.
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Chapter 18 I/O Message and Communication Instructions The I/O Event-Driven Interrupt function is used with specialty I/O modules capable of generating an interrupt. You specify a subroutine to be executed upon receipt of such an interrupt. Important: Refer to chapter 31, Understanding I/O Interrupts – SLC 5/02 Processor Only, before you use these instructions in your program. Programming an I/O event interrupt is done through locations in the status file.
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Chapter 18 I/O Message and Communication Instructions I/O Refresh (REF) SLC 5/02 Processors Only I/O Refresh HHT Ladder Display: HHT Zoom Display: (monitor mode) REF Output Instruction (REF) ZOOM on REF –(REF)– NAME: REFRESH I/O 2.0.0.0.1 EDT_DAT F1 Ladder Diagrams and APS Displays: F2 F3 F4 F5 (REF) The REF instruction has no programming parameters.
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Chapter A–B 19 Comparison Instructions This chapter covers input instructions that allow you to compare values of data.
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Chapter 19 Comparison Instructions Equal (EQU) Equal HHT Ladder Display: HHT Zoom Display: (online monitor mode) EQU Input Instruction EQU ZOOM on EQU –|EQU|– NAME: EQUAL SOURCE A: N7:1 SOURCE B: 612 2.3.0.0.1 0 612 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: EQU EQUAL Source A Source B N7:1 0 612 When the values at source A and source B are equal, the instruction is logically true. If these values are not equal, the instruction is logically false.
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Chapter 19 Comparison Instructions Not Equal (NEQ) Not Equal HHT Ladder Display: HHT Zoom Display: (online monitor mode) NEQ Input Instruction NEQ ZOOM on NEQ –|NEQ|– NAME: NOT EQUAL SOURCE A: N7:1 SOURCE B: 612 2.3.0.0.1 0 612 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: NEQ NOT EQUAL Source A Source B N7:1 0 612 When the values at source A and source B are not equal, the instruction is logically true. If the two values are equal, this instruction is logically false.
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Chapter 19 Comparison Instructions Less Than (LES) Less Than HHT Ladder Display: HHT Zoom Display: (online monitor mode) LES Input Instruction LES ZOOM on LES –|LES|– NAME: LESS THAN SOURCE A: N7:1 SOURCE B: 612 2.3.0.0.1 0 612 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: LES LESS THAN Source A Source B N7:1 0 612 When the value at source A is less than the value at source B, this instruction is logically true.
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Chapter 19 Comparison Instructions Less Than or Equal (LEQ) Less Than or Equal HHT Ladder Display: HHT Zoom Display: (online monitor mode) LEQ Input Instruction LEQ ZOOM on LEQ –|LEQ|– NAME: LESS THAN OR EQUAL SOURCE A: N7:1 0 SOURCE B: 612 612 2.3.0.0.1 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: LEQ LESS THAN OR EQUAL Source A N7:1 0 Source B 612 When the value at source A is less than or equal to the value at source B, this instruction is logically true.
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Chapter 19 Comparison Instructions Greater Than (GRT) Greater Than HHT Ladder Display: HHT Zoom Display: (online monitor mode) GRT Input Instruction GRT ZOOM on GRT –|GRT|– NAME: GREATER THAN SOURCE A: N7:1 0 SOURCE B: 612 612 2.3.0.0.1 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: GRT GREATER THAN Source A Source B N7:1 0 612 When the value at source A is greater than the value at source B, this instruction is logically true.
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Chapter 19 Comparison Instructions Greater Than or Equal (GEQ) Greater Than or Equal HHT Ladder Display: HHT Zoom Display: (online monitor mode) GEQ Input Instruction GEQ ZOOM on GEQ –|GEQ|– 2.3.0.0.1 NAME: GREATER THAN OR EQUAL SOURCE A: N7:1 0 SOURCE B: 612 612 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: GEQ GRTR THAN OR EQUAL Source A N7:1 0 Source B 612 When the value at source A is greater than or equal to the value at source B, this instruction is logically true.
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Chapter 19 Comparison Instructions Masked Comparison for Equal (MEQ) Masked Comparison for Equal HHT Ladder Display: HHT Zoom Display: (online monitor mode) MEQ Input Instruction MEQ ZOOM on MEQ –|MEQ|– 2.3.0.0.
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Chapter 19 Comparison Instructions Limit Test (LIM) SLC 5/02 Processors Only Limit Test HHT Ladder Display: HHT Zoom Display: (online monitor mode) LIM Input Instruction LIM ZOOM on LIM –|LIM|– NAME: LIMIT TEST LOW LIM: N7:0 14 TEST: 50 50 HIGH LIM: N7:1 70 2.3.0.0.1 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: LIM LIMIT TEST Low Lim Test High Lim N7:0 14 50 N7:1 70 This input instruction tests for values within or outside a specified range, depending on how you set the limits.
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Chapter 19 Comparison Instructions True/False Status of the Instruction If the Low Limit has a value equal to or less than the High Limit, the instruction is true when the Test value is between the limits or is equal to either limit. If the Test value is outside the limits, the instruction is false. This is illustrated in the figure below.
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Chapter A–B 20 Math Instructions This chapter covers output instructions that allow you to perform computation and math operations on individual words.
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Chapter 20 Math Instructions Using Arithmetic Status Bits After an instruction is executed, the arithmetic status bits in the status file are updated: • Carry (C), S:0/0 – Set if a carry is generated; otherwise cleared. • Overflow (V), S:0/1 – Indicates that the actual result of a math instruction does not fit in the designated destination. • Zero (Z), S:0/2 – Indicates a 0 value after a math, move, or logic instruction.
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Chapter 20 Math Instructions Add (ADD) Add ADD Output Instruction HHT Ladder Display: (ADD) HHT Zoom Display: (online monitor mode) ZOOM on ADD –(ADD)– NAME: ADD SOURCE A: N7:0 SOURCE B: N7:1 DEST: N7:2 2.3.0.0.2 879 2150 3029 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: ADD ADD Source A Source B Dest N7:0 879 N7:1 2150 N7:2 3029 The value at source A is added to the value at source B and then stored in the destination.
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Chapter 20 Math Instructions Subtract (SUB) Subtract SUB Output Instruction HHT Ladder Display: (SUB) HHT Zoom Display: (online monitor mode) ZOOM on SUB –(SUB)– NAME: SUBTRACT SOURCE A: N7:0 879 SOURCE B: N7:1 2150 DEST: N7:2 –1271 2.3.0.0.2 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: SUB SUBTRACT Source A Source B Dest N7:0 879 N7:1 2150 N7:2 –1271 The value at source B is subtracted from the value at source A and then stored in the destination.
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Chapter 20 Math Instructions 32-Bit Addition and Subtraction–Series C and Later SLC 5/02 Processors With the Series C SLC 5/02 processor, you have the option of performing 16-bit signed integer addition and subtraction (same as Series B SLC 5/02 processors) or 32-bit signed integer addition and subtraction. This is facilitated by status file bit S:2/14, the Math Overflow Selection Bit. Bit S:2/14 Math Overflow Selection Set this bit when you intend to use 32-bit addition and subtraction.
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Chapter 20 Math Instructions Add 16–bit value B3:1 to 32–bit value B3:3 B3:2 Add operation Binary Decimal➀ Hex Addend B3:3 B3:2 Addend B3:1 0000 0000 0000 0011 0001 1001 0100 0000 0003 1940 55A8 0101 0101 1010 1000 203,072 21,928 Sum B3:3 B3:2 0000 0000 0000 0011 0110 1110 1110 1000 0003 6EE8 225,000 ➀ The programming device displays 16–bit decimal values only. The decimal value of a 32–bit integer is derived from the displayed binary or hex value.
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Chapter 20 Math Instructions Multiply (MUL) Multiply MUL Output Instruction HHT Ladder Display: (MUL) HHT Zoom Display: (online monitor mode) ZOOM on MUL –(MUL)– NAME: MULTIPLY SOURCE A: N7:0 SOURCE B: N7:1 DEST: N7:2 2.3.0.0.2 8 2150 17200 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: MUL MULTIPLY Source A Source B Dest N7:0 8 N7:1 2150 N7:2 17200 The value at source A is multiplied by the value at source B and then stored in the destination.
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Chapter 20 Math Instructions Divide (DIV) Divide DIV Output Instruction HHT Ladder Display: (DIV) HHT Zoom Display: (online monitor mode) ZOOM on DIV –(DIV)– NAME: DIVIDE SOURCE A: N7:0 SOURCE B: N7:1 DEST: N7:2 2.3.0.0.2 6214 19 327 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: DIV DIVIDE Source A Source B Dest N7:0 6214 N7:1 19 N7:2 327 The value at source A is divided by the value at source B with the rounded quotient being stored in the destination. If the remainder is 0.
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Chapter 20 Math Instructions Double Divide (DDV) Double Divide DDV Output Instruction HHT Ladder Display: (DDV) HHT Zoom Display: (online monitor mode) ZOOM on DDV –(DDV)– NAME: DOUBLE DIVIDE SOURCE: N7:0 9 DEST: N7:1 5000 2.3.0.0.2 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: DDV DOUBLE DIVIDE Source N7:0 9 Dest N7:1 5000 The contents of the math register are divided by the source value. The rounded quotient is placed in the destination. If the remainder is 0.
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Chapter 20 Math Instructions Negate (NEG) Negate NEG Output Instruction HHT Ladder Display: (NEG) HHT Zoom Display: (online monitor mode) ZOOM on NEG –(NEG)– NAME: NEGATE SOURCE: N7:0 DEST: N7:1 2.3.0.0.2 98 –98 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: NEG NEGATE Source Dest N7:0 98 N7:1 –98 The source value is subtracted from 0 and then stored in the destination. (The destination contains the 2’s complement of the source.
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Chapter 20 Math Instructions Clear (CLR) Clear CLR HHT Ladder Display: (CLR) HHT Zoom Display: (online monitor mode) ZOOM on CLR –(CLR)– NAME: CLEAR DEST: N7:1 Output Instruction 2.3.0.0.2 0 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: CLR CLEAR Dest N7:1 0 The destination value is cleared to zero. Using Arithmetic Status Bits C V Z S always reset always reset always set always reset Math Register Unchanged.
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Chapter 20 Math Instructions Convert to BCD (TOD) Convert to BCD TOD HHT Ladder Display: (TOD) HHT Zoom Display: (online monitor mode) ZOOM on TOD –(TOD)– NAME: TO BCD SOURCE: N7:0 DEST: S:13 Output Instruction 2.3.0.0.2 557 1367 (decimal) EDT_DAT F1 F2 F3 F4 F5 Fixed, SLC 5/01 Processors ZOOM on TOD –(TOD)– NAME: TO BCD SOURCE: N7:0 DEST: N7:1 2.3.0.0.
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Chapter 20 Math Instructions Using Arithmetic Status Bits C always reset V set if the BCD result is larger than 9999. Overflow results in a minor error. Z set if the destination value is zero S set if the source word is negative; otherwise reset Math Register (When Used) Contains the 5–digit BCD result of the conversion. This result is valid at overflow. Example 1 (SLC 5/02 Processors Only) The integer value 9760 stored at N7:3 is converted to BCD and the BCD equivalent is stored in N10:0.
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Chapter 20 Math Instructions Example 2 (Fixed, SLC 5/01, and SLC 5/02 Processors) In the following example, the integer value 32760 stored at N7:3 is converted to BCD. The 5-digit BCD value is stored in the math register. The lower 4 digits of the BCD value is moved to output word O:2 and the remaining digit is moved thru a mask to output word O:3. When using the math register as the destination parameter in the TOD instruction, the maximum BCD value possible is 32767.
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Chapter 20 Math Instructions Convert from BCD (FRD) Convert from BCD FRD Output Instruction HHT Ladder Display: (FRD) HHT Zoom Display: (online monitor mode) ZOOM on FRD –(FRD)– NAME: FROM BCD DEST: N7:1 SOURCE: S:13 2.3.0.0.2 557 1367 (decimal) EDT_DAT F1 F2 F3 F4 F5 Fixed, SLC 5/01 Processors ZOOM on FRD –(FRD)– NAME: FROM BCD SOURCE: N7:0 DEST: N7:1 2.3.0.0.
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Chapter 20 Math Instructions Using Arithmetic Status Bits C always reset V set if a non-BCD value is contained at the source or the value to be converted is greater than 32,767; otherwise reset. Overflow results in a minor error. Z set when destination value is zero S always reset Math Register (When Used) Used as the source for converting the entire number range of a register.
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Chapter 20 Math Instructions Example 1 (SLC 5/02 Processors Only) The BCD value 9760 at source N7:3 is converted from BCD and stored in N10:0. The maximum source value is 9999, BCD. ZOOM on FRD –(FRD)– NAME: FROM BCD SOURCE: N7:3 DEST: N10:0 2.3.0.0.2 –26784 9760 Source is displayed as –26784, decimal (equivalent to 9760 BCD).
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Chapter 20 Math Instructions An example of clearing S:14 before executing the FRD instruction is shown below. I:1.0 ] [ 0 MOV MOVE Source Dest N7:2 4660 S:13 4660 0001 0010 0011 0100 CLR CLEAR Dest S:14 0 FRD FROM BCD Source Dest S:13 00001234 N7:0 1234 APS displays S:13 and S:14 in BCD. 0000 0100 1101 0010 When the input condition is set (1), a BCD value (from a 4-digit thumbwheel switch for example) is moved from word N7:2 into the math register.
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Chapter 20 Math Instructions Decode 4 to 1 of 16 (DCD) Decode 4 to 1 of 16 DCD Output Instruction HHT Ladder Display: (DCD) HHT Zoom Display: (online monitor mode) ZOOM on DCD –(DCD)– 2.3.0.0.
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Chapter 20 Math Instructions Entering Parameters • Source – the address that contains the bit decode information. Only the first four bits (0–3) are used by the DCD instruction. The remaining bits may be used for other application specific needs. Change the value of the first four bits of this word to select one bit of the destination word. • Destination – the address of the word to be decoded. Only one bit of this word is turned on at any one time, depending on the value of the source word.
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Chapter 20 Math Instructions Using Arithmetic Status Bits C V Z S reserved always reset set when destination value is zero always reset Math Register Contents unchanged. Scale Data (SCL) SLC 5/02 Processors Only Scale Data HHT Ladder Display: HHT Zoom Display: (online monitor mode) SCL Output Instruction (SCL) ZOOM on SCL –(SCL)– NAME: SCALE SOURCE: N7:0 RATE: 25000 OFFSET: 127 DEST: N7:1 2.3.0.0.
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Chapter 20 Math Instructions This instruction can be used to solve linear equations of the form Dest = (Rate/10000) x Source + Offset “Rate” is sometimes referred to as Slope. When the SCL instruction is true, the value at the source address is multiplied by the rate value. The rounded result is added to the offset value and placed in the destination. Example SCL SCALE Source Rate [/10000] Offset Dest N7:0 100 25000 127 N7:1 377 The source 100 is multiplied by 25000/10000 and added to 127.
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Chapter 20 Math Instructions Math Register Contents unchanged. Typical Application – Converting Degrees Celsius to Degrees Fahrenheit Convert degrees Celsius to degrees Fahrenheit. The conversion equation is F = (9/5)C + 32, or F = (1.8)C + 32. Example: 25 degrees C = 77 degrees F. F = (1.8)25 + 32 = 77. Graphically, F 100 77 32 25 100 C To implement the conversion equation F = (1.8)25 + 32 = 77 in the SCL instruction: 1. Place the degrees C value (25 in this case) in the source parameter. 2.
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Chapter A–B 21 Move and Logical Instructions This chapter covers output instructions that allow you to perform move and logical operations on individual words. Use these instructions with fixed, SLC 5/01 and SLC 5/02 processors: • Move (MOV) • Masked Move (MVM) • And (AND) • Inclusive Or (OR) • Exclusive Or (XOR) • Not (NOT) All application examples shown are in the HHT zoom display. Move and Logical Instructions Overview The following general information applies to move and logical instructions.
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Chapter 21 Move and Logical Instructions Overflow Trap Bit, S:5/0 Minor error bit set upon detection of a mathematical overflow or division by 0. If this bit is set upon execution of the END statement or a TND instruction, a major error will be declared. Math Register, S:13 and S:14 Move and logical instructions do not affect the math register.
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Chapter 21 Move and Logical Instructions Using Arithmetic Status Bits C V Z S always reset always reset set if the result is zero; otherwise reset set if the result is negative (most significant bit is set); otherwise reset Application note: If you wish to move 1 word of data without affecting the math flags, use a copy (COP) instruction with a length of 1 word instead of using the MOV instruction. The COP instruction is discussed in chapter 22.
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Chapter 21 Move and Logical Instructions Entering Parameters • Source – the address of the data you want to move. • Mask – the address of the mask word through which the instruction moves data. You can also enter a hex value (constant). Refer to appendix B for more information regarding masks and hexadecimal numbering. • Destination – the address where the instruction moves the data.
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Chapter 21 Move and Logical Instructions And (AND) And AND Output Instruction HHT Ladder Display: (AND) HHT Zoom Display: (online monitor mode) ZOOM on AND –(AND)– 2.3.0.0.
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Chapter 21 Move and Logical Instructions Or (OR) Or OR Output Instruction HHT Ladder Display: (OR) HHT Zoom Display: (online monitor mode) ZOOM on OR –(OR)– NAME: BITWISE INCLUSIVE OR SOURCE A: B3:0 0001 0101 SOURCE B: B3:1 0010 0000 DEST: B3:2 0011 0101 2.3.0.0.
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Chapter 21 Move and Logical Instructions Exclusive Or (XOR) Exclusive Or XOR Output Instruction HHT Ladder Display: (XOR) HHT Zoom Display: (online monitor mode) ZOOM on XOR –(XOR)– NAME: BITWISE EXCLUSIVE OR SOURCE A: B3:0 0001 0101 SOURCE B: B3:1 0010 0000 DEST: B3:2 0011 0101 2.3.0.0.
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Chapter 21 Move and Logical Instructions Not (NOT) Not NOT HHT Ladder Display: (NOT) HHT Zoom Display: (online monitor mode) ZOOM on NOT –(NOT)– NAME: NOT SOURCE: B3:0 DEST: B3:1 Output Instruction 2.3.0.0.2 1010 0110 1110 1100 0101 1001 0001 0011 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: NOT NOT Source B3:0 1010011011101100 Dest B3:1 0101100100010011 The source value is NOTed (inverted) bit by bit and then stored in the destination.
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Chapter 22 File Copy and File Fill Instructions This chapter covers the following instructions for use with the fixed, SLC 5/01, and SLC 5/02 processors: • File Copy (COP) • File Fill (FLL) File Copy and Fill Instructions Overview These instructions move data from a source file or element to a destination file. They are similar to a Move (MOV) instruction, but they enable you to move more than one word at a time. This is facilitated by the use of the file indicator # in the parameter addresses.
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Chapter 22 File Copy and File Fill Instructions File Copy (COP) File Copy COP Output Instruction HHT Ladder Display: (COP) HHT Zoom Display: (online monitor mode) ZOOM on COP –(COP)– NAME: FILE COPY LENGTH: 10 SOURCE: #N7:5 DEST: #N10:0 2.3.0.0.2 10 0 0 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: COP COPY FILE Source Dest Length #N7:5 #N10:0 10 This instruction copies data from one location into another. It uses no status bits.
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Chapter 22 File Copy and File Fill Instructions All elements are copied from the specified source file into the specified destination file each scan the rung is true. Elements are copied in ascending order with no transformation of data. They are copied up to the specified number (length) or until the last element of the destination file is reached, whichever occurs first. The destination file type determines the number of words that the instruction transfers.
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Chapter 22 File Copy and File Fill Instructions The FLL instruction loads either an element of data or a program constant from the source to a destination file, as illustrated below. Source: Element Destination: File Typically, the FLL instruction might be used to reset or clear several integer values all at once. Entering Parameters • Source – The program constant (decimal) or element address. (The file indicator # is not required for an element address.
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Chapter A–B 23 Bit Shift, FIFO, and LIFO Instructions This chapter covers instructions for use with fixed, SLC 5/01, and SLC 5/02 processors: • Bit Shift Left (BSL) • Bit Shift Right (BSR) These are output instructions that load data into a bit array one bit at a time. The data is shifted through the array, then unloaded one bit at a time. Bit shift instructions are useful in conveyor applications and product evaluation (pass/fail) applications.
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Chapter 23 Bit Shift, FIFO, and LIFO Instructions Bit Shift Left (BSL), Bit Shift Right (BSR) Bit Shift Left, Bit Shift Right HHT Ladder Display: HHT Zoom Display: (online monitor mode) BSL, BSR (BSL) Output Instructions (BSR) ZOOM on BSL –(BSL)– 2.3.0.0.1 NAME: BIT SHIFT LEFT FILE: #B3:1 LENGTH: 50 CONTROL: R6:0 BIT ADDR: I1:1.0/0 EN DN ER UL 0 0 0 0 EDT_DAT F1 F2 F3 F4 F5 ZOOM on BSR –(BSR)– 2.3.0.0.1 NAME: BIT SHIFT RIGHT FILE: #B3:1 LENGTH: 50 CONTROL: R6:0 BIT ADDR: I1:1.
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Chapter 23 Bit Shift, FIFO, and LIFO Instructions Entering Parameters • File – The address of the bit array you want to manipulate. You must use the file indicator # in the bit array address. The address must start on an element boundary (for example, B3:0/0, not B3:0/4). • Control – The instruction’s address and control (R data file) element that stores the status byte of the instruction, the length of the array (in number of bits), and the bit pointer (currently not used).
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Chapter 23 Bit Shift, FIFO, and LIFO Instructions Operation – Bit Shift Left When the rung goes from false–to–true, the enable bit (EN bit 15) is set and the data block is shifted to the left (to a higher bit number) one bit position. The specified bit at the Bit Address (source) is shifted into the first bit position. The last bit is shifted out of the array and stored in the unload bit (UL bit 10) in the status byte of the control element. The shift is completed in one scan.
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Chapter 23 Bit Shift, FIFO, and LIFO Instructions If you wish to shift more than one bit per scan, you must create a loop using jump (JMP) and label (LBL) instructions. FIFO Load (FFL), FIFO Unload (FFU) SLC 5/02 Processors Only FIFO Load, FIFO Unload HHT Ladder Display: HHT Zoom Display: (online monitor mode) FFL, FFU (FFL) Output Instructions (FFU) ZOOM on FFL –(FFL)– 2.3.0.0.
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Chapter 23 Bit Shift, FIFO, and LIFO Instructions Entering Parameters Enter the following parameters when programming these instructions: • Source – This word address stores the value to be entered next into the FIFO stack. The FFL instruction places this value into the next available element in the FIFO stack. SOURCE can be a word address or a program constant (–32768 to 32767). For I/O addresses, the HHT requires you to specify the slot and word number, for example I:3.0.
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Chapter 23 Bit Shift, FIFO, and LIFO Instructions Operation Instruction parameters have been programmed in the FFL – FFU instruction pair shown below. FFL FIFO LOAD Source FIFO Control Length Position (EN) N7:10 #N7:12 R6:0 34 9 (DN) N7:11 (EM) FFU FIFO UNLOAD FIFO Dest Control Length Position (EU) #N7:12 N7:11 R6:0 34 9 FFU instruction unloads data from stack #N7:12 at position 0, N7:12.
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Chapter 23 Bit Shift, FIFO, and LIFO Instructions LIFO Load (LFL), LIFO Unload (LFU) SLC 5/02 Processors Only LIFO Load, LIFO Unload HHT Ladder Display: HHT Zoom Display: (online monitor mode) (monitor mode) LFL, LFU (LFL) Output Instructions (LFU) ZOOM on LFL –(LFL)– 2.3.0.0.2 NAME: LIFO LOAD SOURCE: N7:10 LENGTH: 34 LIFO: #N7:12 POSITION:0 CONTROL: R6:0 EN EU DN EM 0 0 0 0 EDT_DAT F1 F2 F3 F4 F5 ZOOM on LFU –(LFU)– 2.4.0.0.
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Chapter 23 Bit Shift, FIFO, and LIFO Instructions Operation Instruction parameters have been programmed in the LFL – LFU instruction pair shown below. For purposes of comparison, the same parameters are used here as in the FFL – FFU example on page 23–7. LFL LIFO LOAD Source LIFO Control Length Position (EN) N7:10 #N7:12 R6:0 34 9 (DN) (EM) LFU LIFO UNLOAD LIFO Dest Control Length Position (EU) #N7:12 N7:11 R6:0 34 9 (DN) (EM) LFU instruction unloads data from stack #N7:12 at position 8.
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Chapter A–B 24 Sequencer Instructions This chapter covers sequencer instructions including Sequencer Output, Sequencer Compare, and Sequencer Load. These instructions are generally used in machine control. Instructions for use with fixed, SLC 5/01, and SLC 5/02 processors: • Sequencer Output (SQO). It transfers 16-bit data to word addresses for the control of sequential machine operations. • Sequencer Compare (SQC).
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Chapter 24 Sequencer Instructions Sequencer Output (SQO), Sequencer Compare (SQC) Sequencer Output Sequencer Compare HHT Ladder Display: HHT Zoom Display: (online monitor mode) SQO SQC (SQO) Output Instructions (SQC) ZOOM on SQO –(SQO)– 2.3.0.0.2 NAME: SEQUENCER OUTPUT FILE: #B10:1 CONTROL: R6:20 MASK: 0F0F LENGTH: 4 DEST: O0:2.0 POSITION:0 EN DN ER 0 0 0 EDT_DAT F1 F2 F3 F4 F5 ZOOM on SQC –(SQC)– 2.3.0.0.2 NAME: SEQUENCER COMPARE FILE: #B10:11 CONTROL: R6:21 MASK: FFF0 LENGTH: 4 SOURCE: I1:1.
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Chapter 24 Sequencer Instructions Entering Parameters • File (SQO, SQC) – This is the address of the sequencer file. You must use the file indicator # for this address. Sequencer file data is used as follows: Instruction SQO SQC Sequencer File Stores Data for controlling outputs Reference data for monitoring inputs • Mask (SQO, SQC) – This is a hex code or the address of the mask word or file through which the instruction moves data. Set mask bits to pass data, reset mask bits to mask data.
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Chapter 24 Sequencer Instructions Status Bits of the Control Element EN (bit 15) – The enable bit is set by a false-to-true rung transition and indicates the SQO or SQC instruction is enabled. It follows the rung condition. DN (bit 13) – The done bit is set by the SQO or SQC instruction after it has operated on the last word in the sequencer file. It is reset on the next false-to-true rung transition after the rung goes false.
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Chapter 24 Sequencer Instructions When the rung goes from false–to–true, the instruction increments to the next step (word) in the sequencer file. Data stored there is transferred through a mask to the destination address specified in the instruction. Current data is written to the corresponding destination word every scan that the rung remains true. The done bit is set when the last word of the sequencer file is transferred.
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Chapter 24 Sequencer Instructions Operation – Sequencer Compare The SQC instruction compares a word or file of input data, through a mask, to a word or file of reference data for equality. When the status of all non-masked bits in an input word match those of the corresponding reference word, the instruction sets the found bit (FD) in the respective control word. Otherwise, when the input word does not match, the found bit (FD) is cleared. Mask data by resetting bits in the mask word.
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Chapter 24 Sequencer Instructions Sequencer Load (SQL) SLC 5/02 Processors Only Sequencer Load SQL HHT Ladder Display: HHT Zoom Display: (online monitor mode) Output Instruction (SQL) ZOOM on SQL –(SQL)– 2.3.0.0.2 NAME: SEQUENCER LOAD FILE: #N7:30 LENGTH: 4 SOURCE: I1:1.0 POSITION:0 CONTROL: R6:4 EN EU DN EM 0 0 0 0 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: SQL SEQUENCER LOAD File #N7:30 Source I:1.
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Chapter 24 Sequencer Instructions Status Bits • EN (bit 15) – The enable bit. This bit is set on a false-to-true transition of the SQL rung and reset on a true-to-false transition. • DN (bit 13) – The done bit. This bit is set after the instruction has operated on the last word in the sequencer load file. It is reset on the next false-to-true rung transition after the rung goes false. • ER (bit 11) – The error bit.
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Chapter 24 Sequencer Instructions Operation Instruction parameters have been programmed in the SQL instruction shown below. Input word I:1.0 is the source. Data in this word is loaded into integer file #N7:30 by the sequencer load instruction. SQL SEQUENCER LOAD File #N7:30 Source I:1.0 Control R6:4 Length 4 Position 2 External inputs associated with I:1.0 (EN) (DN) Source I:1.
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Chapter A–B 25 Control Instructions This chapter covers the following control instructions. Instructions for Use with fixed, SLC 5/01, and SLC 5/02 processors: • Jump to Label (JMP) and Label (LBL) • Jump to Subroutine (JSR) and Subroutine (SBR) • Return from Subroutine (RET) • Master Control Reset (MCR) • Temporary End (TND) • Suspend (SUS) Instructions for use with SLC 5/02 processors only: The following instructions apply to the Selectable Timed Interrupt (STI) function, discussed in chapter 30.
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Chapter 25 Control Instructions Jump to Label (JMP) Jump to Label JMP Output Instruction HHT Ladder Display: (JMP) HHT Zoom Display: (online monitor mode) ZOOM on JMP –(JMP)– NAME: JUMP TO LABEL LABEL: 1 2.3.0.0.2 EDT_DAT F1 Ladder Diagrams and APS Displays: F2 F3 F4 F5 1 (JMP) When the rung condition for this output instruction is true, the processor jumps forward or backward to the corresponding label instruction (LBL) and resumes program execution at the label.
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Chapter 25 Control Instructions Label (LBL) Label HHT Ladder Display: HHT Zoom Display: (online monitor mode) LBL Input Instruction LBL ZOOM on LBL –|LBL|– NAME: LABEL LABEL: 1 2.3.0.0.1 EDT_DAT F1 Ladder Diagrams and APS Displays: F2 F3 F4 F5 1 [LBL] This input instruction is the target of the JMP instruction having the same label number. You must program this instruction as the first instruction of a rung. The Jump (JMP) and its corresponding Label (LBL) must be in the same program file.
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Chapter 25 Control Instructions Jump to Subroutine (JSR) Jump to Subroutine JSR Output Instruction HHT Ladder Display: (JSR) HHT Zoom Display: (online monitor mode) ZOOM on JSR –(JSR)– NAME: JUMP TO SUBROUTINE FILE: 3 2.3.0.0.2 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: JSR JUMP TO SUBROUTINE SBR file number 3 The Jump to Subroutine (JSR), Subroutine (SUB), and Return (RET) are used in conjunction, as shown on the following page.
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Chapter 25 Control Instructions The example below illustrates jumping to successive subroutines, then returning in reverse order.
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Chapter 25 Control Instructions Subroutine (SBR) Subroutine HHT Ladder Display: (online monitor mode) HHT Zoom Display: SBR Input Instruction SBR ZOOM on SBR –|SBR|– NAME: SUBROUTINE 2.3.0.0.1 EDT_DAT F1 F2 F3 F4 F5 Ladder Diagrams and APS Displays: SBR SUBROUTINE This instruction serves as a label or identifier of a program file as a regular subroutine file (SBR label) versus an interrupt subroutine (INT label).
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Chapter 25 Control Instructions This output instruction marks the end of subroutine execution or the end of the subroutine file. It causes the processor to resume execution in the main program file at the instruction following the JSR instruction where it exited the program. If a sequence of nested subroutines is involved, the instruction causes the processor to return program execution to the previous subroutine.
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Chapter 25 Control Instructions ! ATTENTION: If you start instructions such as timers or counters in an MCR zone, instruction operation ceases when the zone is disabled. Reprogram critical operations outside the zone if necessary. The TOF timer will activate when placed inside of a false MCR zone. The MCR instruction is not a substitute for a hard-wired master control relay.
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Chapter 25 Control Instructions Important: Use of this instruction inside a nested subroutine or interrupt subroutine terminates execution of all nested subroutines. Suspend (SUS) Suspend SUS Output Instruction HHT Ladder Display: (SUS) HHT Zoom Display: (online monitor mode) ZOOM on SUS –(SUS)– NAME: SUSPEND SUS ID: 1 2.3.0.0.
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Chapter 25 Control Instructions Selectable Timed Interrupt (STI) SLC 5/02 Processors Only Selectable Timed Disable Selectable Timed Enable Selectable Timed Start HHT Ladder Display: HHT Zoom Display: (online monitor mode) STD STE STS (STD) Output Instruction Output Instruction Output Instruction (STE) (STS) ZOOM on STD –(STD)– 2.6.0.0.1 NAME: SELECTABLE TIMED DISABLE EDT_DAT F1 F2 F3 F4 F5 ZOOM on STE –(STE)– 2.3.0.0.
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Chapter 25 Control Instructions Important: The information here is for reference only and is optional. Program these instructions using the information appearing in chapter 30. Selectable Timed Interrupt Disable and Enable (STD, STE) These instructions are generally used in pairs. The purpose is to prevent the STI from occurring during a portion of the ladder program. Selectable Timed Interrupt Start (STS) The Selectable Timed Start (STS) function is used to initiate or restart the STI function.
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Chapter A–B 26 PID Instruction This chapter applies to the SLC 5/02 processor only. It explains the PID instruction. All application examples shown are in the HHT zoom display. Proportional, Integral, Derivative (PID) SLC 5/02 Processors Only It is an output instruction that controls physical properties such as temperature, pressure, liquid level, or flow rate of process loops.
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Chapter 26 PID Instruction Proportional Integral Derivative HHT Ladder Display: HHT Zoom Display: (monitor mode) auto PID Output Instruction (PID) ZOOM on PID –(PID)– 1/2 NAME: PROP INT DERIV MODE: GAIN: 255 [/10] OUT LIM: RESET: 10 [/10 M/R] DEADBND: RATE: 5 [/100 MIN] OUTPUT: SETPOINT: 500 PROCESS: ENTER GAIN: 255 NEXT PG MANUAL F1 F2 F3 F4 ZOOM on PID –(PID)– 1/2 NAME: PROP INT DERIV MODE: PROCESS: 14 SETPOINT: 500 OUTPUT: 0% MIN OUT: 5% MAX OUT: 95% manual ENTER OUTPUT PCT: 0 NEXT PG AUTO
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Chapter 26 PID Instruction The PID instruction normally controls a closed loop using inputs from an analog input module and providing an output to an analog output module. For temperature control, you can convert the analog output to a time proportioning on/off output for driving a heater or cooling unit. An example appears on pages 26–20 and 26–22. The PID instruction can be operated in the timed mode or the STI mode. In the timed mode, the instruction updates its output periodically at the rate you set.
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Chapter 26 PID Instruction The PID Equation The PID instruction uses the following equation: Output + K C [(E) ) 1ńT I ŕ(E)dt ) T D · D(PV)ńdt] ) bias Standard Gains constants: Term Range (Low to High) Reference Controller Gain KC 0.1 to 25.5 (dimensionless) Proportional Reset Term 1/TI 25.5 to 0.1 (minutes per repeat) Integral Rate Term TD 0.01 to 2.55 (minutes) Derivative The derivative term (rate) provides smoothing by means of a low pass filter.
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Chapter 26 PID Instruction • Process (also called the Process Variable, PV) – This is an element address that stores the process input value. This address can be the location of the analog input word where the value of the input A/D is stored. This value could also be an integer value if you choose to pre-scale your input value to the range 0–16383. • Output (also called Control Variable, CV) – This is an element address that stores the output of the PID instruction.
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Chapter 26 PID Instruction • Minimum output (control block word 12) – If you want to use output limiting or alarms, enter a value. If the output limit bit is also set, this value is the minimum control output percent (word 16) that the control variable (CV) obtains or outputs. • Maximum output (control block word 11) – If the output limit bit is also set, the value you enter is the maximum control output percent (word 16) that the control variable (CV) obtains or outputs.
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Chapter 26 PID Instruction • Scaled setpoint minimum (Smin) (control block word 8) – If the setpoint is to read in engineering units, then this parameter corresponds to the value of the setpoint in engineering units when the control input is zero. Range: –16383 to +16383. • Scaled setpoint maximum (Smax) (control block word 7) – If the setpoint is to read in engineering units, then this parameter corresponds to the value of the setpoint in engineering units when the control input is 16383.
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Chapter 26 PID Instruction • Control (control block word 0, bit 2) – Reverse, the default condition, corresponds to E=SP–PV. Forward corresponds to E=PV–SP. Direct acting (E=PV–SP) will cause the output CV to increase when the input PV is larger than the setpoint SP (for example, a cooling application). Reverse acting (E=SP–PV) will cause the output CV to increase when the input PV is smaller than the setpoint SP (for example, a heating application).
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Chapter 26 PID Instruction Control Block Layout 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 EN DN PV SP LL UL DB TF SC OL CM AM TM Word 0 PID Sub Error Code (MSbyte)* 1 Setpoint SP * 2 Gain KC * 3 Reset Ti * 4 Rate Td * 5 Feed Forward Bias* 6 Setpoint Max (Smax) * 7 Setpoint Min (Smin) * 8 Deadband * 9 INTERNAL USE DO NOT CHANGE OL, CM, AM, TM * 10 Output Max % * 11 Output Min % * 12 Loop Update * 13 Scaled Process Variable 14 Scaled Error SE 15 Control Output Perce
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Chapter 26 PID Instruction • Output limiting enabled bit OL (word 0, bit 3) – This bit is set when you have selected to limit the control variable. This bit can be set or cleared by instructions in your ladder program. • Scale setpoint flag SC (word 0, bit 5) – This bit is cleared when setpoint scaling values have been specified.
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Chapter 26 PID Instruction Runtime Errors Error Code (Decimal) Error Code (Hex) 4352 Error code 0036 appears in the status file (S:6) when a PID instruction runtime error occurs. Code 0036 covers the following PID error conditions, each of which has been assigned a unique single byte code value that appears in the MSbyte (most significant byte or upper 8 bits) of the second word (word 1) of the PID control block.
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Chapter 26 PID Instruction PID and Analog I/O Scaling For the SLC 500 PID instruction, the numerical scale for both the process variable (PV) and the control variable (CV) is 0 to 16383. To use engineering units, such as PSI or degrees, you must first scale your analog I/O ranges within the above numerical scale. To do this, use the Scale (SCL) instruction and follow the steps described below. Refer to the Analog I/O Modules User Manual, catalog number 1746–NM003 for more information.
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Chapter 26 PID Instruction The following ladder diagram shows a typical PID loop that is programmed in the STI mode. This example (in APS format) is provided primarily to show the proper scaling techniques. It shows a 4 to 20mA analog input and a 4 to 20mA analog output. This rung immediately updates the analog input used for PV. IIM IMMEDIATE IN w MASK Slot I:1.0 Mask FFFF Rung 3:0 Rung 3:1 These two rungs ensure the analog input value to be scaled remains within the limits of 3277 to 16384.
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Chapter 26 PID Instruction Rung 3:5 The PID control variable is the input for the scale instruction. The PID instruction guarantees that the CV remains within the range of 0 to 16383. This value is to be scaled to the range of 6242 to 31208, which represents the numeric range that is needed to produce 4 to 20mA analog output signal. SCL SCALE Source N10:29 0 Rate [/10000] 15239 Offset Dest 6242 O:1.
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Chapter 26 PID Instruction The second display shows the status bits discussed in the last section: ZOOM on PID –(PID)– 2/2 2.0.0.0.
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Chapter 26 PID Instruction Normally, when the (CV) Output % is changed, the scaled value in the “Output” location is changed. This value is a number from 0 to 16383 corresponding to the (CV) Output % of 0 to 100. Although the (CV) Output % is displayed in the control block (word 16), modifying this word in the manual mode has no effect on the “Output” value.
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Chapter 26 PID Instruction Select scaling as follows: 1. Enter the maximum and minimum scaling values Smax and Smin in the PID control block. Refer to the control block of the PID instruction on page 26–9. The Smin value corresponds to an analog value of zero for the lowest reading of the process variable, and Smax corresponds to an analog value of 16383 for the highest reading. These values reflect the process limits. Setpoint scaling is selected by entering a non-zero value for one or both parameters.
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Chapter 26 PID Instruction Output Alarms You may set an output alarm on the control output (CO) at a selected value above and/or below a selected output percent. When the instruction detects that the output (CO) has exceeded either value, it sets an alarm bit (bit 10 for lower limit, bit 9 for upper limit) in word 0 of the PID control block. Alarm bits are reset by the instruction when the output (CO) comes back inside the limits.
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Chapter 26 PID Instruction The Manual Mode In the manual mode, the PID algorithm does not compute the value of the control variable. Rather, it uses the value as an input to adjust the integral sum (words 17 and 18) so that a bumpless transfer takes place upon re-entering the AUTO mode. In the manual mode, the HHT allows you to enter a new CO value from 0 to 100%. This value is converted into a number from 0 to 16383 and written to the Control Variable address.
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Chapter 26 PID Instruction Example – To Manually Control the CV Output A/M Bit Manual I:2.0 ] [ 2 N7:10 (L) 1 A/M Bit Auto I:2.0 ] [ 1 A/M Bit N7:10 ] [ 1 N7:10 (U) 1 Accept CV I:2.0 ] [ 0 FRD B3 [OSR] 0 FROM BCD Source I1:1.0 Dest LIM LIMIT TEST Low Lim Test High Lim N7:0 MUL 0 MULTIPLY Source A N7:0 N7:0 Source B 16384 100 Dest N7:2 DDV DOUBLE DIVIDE Source Dest Notes on Operation A 3-digit BCD thumbwheel is wired to an input module at I1:1.0 (range 0–100).
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Chapter 26 PID Instruction Feed Forward Applications involving transport lags may require that a bias be added to the CV output in anticipation of a disturbance. This bias can be accomplished in the SLC 5/02 processor by writing a value to the Feed Forward Bias element, the seventh element (word 6) in the control block file (see page 26–7). The value you write will be added to the output, allowing a feed forward action to take place.
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Chapter 26 PID Instruction Example – Time Proportioning Outputs PID PID Control Process Control Control Block Variable Variable Block Length N7:2 N7:0 N7:1 23 TON TIMER ON DELAY Timer T4:0 Time Base 0.01 Preset 1000 Accum 0 GRT (EN) (DN) Cycle Time of the Output O:1.0 (U) 0 GREATER THAN Source A T4:0.ACC 0 Source B N7:25 0 Time Proportioning Output Contact T4:0 (RES) T4:0 ] [ DN NEQ NOT EQUAL Source A Source B N7:25 0 0 O:1.
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Chapter 26 PID Instruction PID Tuning PID tuning requires a knowledge of process control. If you are inexperienced, it will be helpful if you obtain training on the process control theory and methods used by your company. There are a number of techniques that can be used to tune a PID loop. The following PID tuning method is general, and is limited in terms of handling load disturbances. When tuning, changes should be made in the manual mode, followed by a return to auto.
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Chapter 26 PID Instruction 8. Adjust the gain while observing the relationship of the output to the setpoint over time. Note that gain adjustments disrupt the process when you change values. To avoid this disruption, switch to the MANUAL mode prior to making your gain change, then switch back to the AUTO mode. 9. When you notice that the process is oscillating above and below the setpoint in an even manner, record the time of 1 cycle. That is, obtain the natural period of the process.
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Chapter 27 The Status File This chapter discusses the status file functions of the: • fixed • SLC 5/01 • SLC 5/02 processors All application examples shown are in the HHT zoom display. Status File Functions The SLC 5/02 processor has the functions of the fixed and SLC 5/01 processors plus the functions listed in the right-hand column of the figure below. The status file gives you information concerning the various instructions you use in your program, and other information such as EEPROM functionality.
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Chapter 27 The Status File The following tables describe the status file functions, beginning at address S:0 and ending at address S:32. If a bullet (•) is present in the columns headed SLC 5/02 and SLC 5/01, Fixed, the function applies to the indicated processor(s). Address Description 5/02 5/01, Fixed S:0 Arithmetic Flags Read/write. The arithmetic flags are assessed by the processor following the execution of any math, logical, or move instruction.
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Chapter 27 The Status File Address Description 5/02 5/01, Fixed S:1/0 thru S:1/4 Processor Mode/Status Read only.
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Chapter 27 The Status File Address Description 5/02 S:1/9 Startup Protection Fault Bit Read/write. When this bit is set and power is cycled while the processor is in the Run mode, the processor will execute your fault routine prior to the execution of the first scan of your program. You then have the option of clearing the Major Error Halted bit S:1/13 to resume operation in the Run mode. If your fault routine does not reset bit S:1/13, the fault mode will result.
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Chapter 27 The Status File Address S:1/11 Description Continued from previous page: 5/02 5/01, Fixed • • You must set S:1/11 in the status file of the program in the memory module. Loading will take place if the master password and/or password in the processor and memory module match. Loading will also take place if the processor has neither a password nor master password.
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Chapter 27 The Status File Address Description 5/02 5/01, Fixed S:1/13 Major Error Halted Bit Read/write. This bit is set by the processor any time a major error is encountered. The processor then enters a fault condition. Word S:6 Fault Code will contain a code which can be used to diagnose the fault condition.
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Chapter 27 The Status File Address Description 5/02 5/01, Fixed S:1/14 Access Denied Bit Read/write. You can allow or deny future access to a processor file. If you deny access, the processor sets this bit, indicating that a programming device must have a matching copy of the processor file in its memory in order to monitor the ladder program. A programming device that does not have a matching copy of the processor file is denied access.
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Chapter 27 The Status File Address Description 5/02 S:2/2 STI (Selectable Timed Interrupt) Executing Bit Read only. This bit, when set, indicates that the STI timer has timed out and the STI subroutine is currently being executed. Application example: You could examine this bit in your fault routine to determine if your STI was executing when the fault occurred. This bit is cleared upon completion of the STI routine, powerup, or Run mode entry. • S:2/3 Index Addressing File Range Bit Read only.
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Chapter 27 The Status File Address Description 5/02 S:2/7 DH–485 Outgoing Message Command Pending Bit Read only. This bit is set when one or more messages in your program are enabled and waiting, but no message is being transmitted at the time. As soon as transmission of a message begins, the bit is cleared. After transmission, the bit is set again if there are further messages waiting, or it remains cleared if there are no further messages waiting.
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Chapter 27 The Status File Address S:2/14 Description Math Overflow Selection Bit Applies to Series C and later SLC 5/02 processors only. Set this bit when you intend to use 32-bit addition and subtraction.
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Chapter 27 The Status File Address Description 5/02 S:2/15 DH–485 Communications Servicing Selection Bit Read/write. When set, only one communication request/command will be serviced per END, TND, REF, or SVC. When clear, all serviceable incoming or outgoing communication requests /commands will be serviced per END, TND, REF, or SVC. When clear, your communications throughput will increase. However, your scan time will increase if several communication commands/requests are received in the same scan.
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Chapter 27 The Status File Address Description 5/02 5/01, Fixed S:3L Current/Last 10 ms Scan Time Byte Read/write. The value of this byte tells you how much time elapses in a program cycle. A program cycle includes the ladder program scan, I/O scan, and servicing the communication port. The byte value is zeroed by the processor each scan, immediately preceding the execution of rung 0 of program file 2 (main program file) or on return from the REF instruction.
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Chapter 27 The Status File Address Description 5/02 5/01, Fixed S:3H Watchdog Scan Time Byte Read/write. This byte value contains the number of 10 ms ticks allowed to occur during a program cycle. The default value is 10 (100 ms) but you can increase this to 250 (2.5 seconds) or decrease it to 2, as your application requires. If the program scan S:3L value equals the watchdog value, a watchdog major error will be declared (code 0022).
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Chapter 27 The Status File Address Description 5/02 5/01, Fixed S:5 Minor Error Bits The bits of this word are set by the processor to indicate that a minor error has occurred in your ladder program. Minor errors, bits 0–7, revert to major error 0020H if any bit is detected as being set at the end of the scan. If the processor faults for error code 0020H, you must clear minor error bits S:5/0–7 along with S:1/13 to attempt error recovery. • • S:5/0 Overflow Trap Bit Read/write.
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Chapter 27 The Status File Address Description 5/02 S:5/3 Major Error Detected while Executing User Fault Routine Bit Read/write. When set, the major error code (S:6) will then represent the major error that occurred while processing the fault routine due to another major error. • 5/01, Fixed If this bit is ever set upon execution of the END, TND, or REF instruction, a major error (0020) will be declared.
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Chapter 27 The Status File Address Description 5/02 5/01, Fixed S:5/8 Memory Module Boot Bit Read/write. When this bit is set by the processor, it indicates that a memory module program has been transferred to the processor. This bit is not cleared by the processor. • • • • Your program can examine the state of this bit every Run mode entry to determine if the memory module content has been transferred. S:1/15 will be set to indicate Run mode entry.
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Chapter 27 The Status File Address Description 5/02 5/01, Fixed S:6 Major Error Fault Code Read/write. A hex code will be entered in this word by the processor when a major error is declared (refer to S:1/13). The code defines the type of fault, as indicated on the following pages. This word is not cleared by the processor. • • Error codes are presented, stored, and displayed in hexadecimal. (appendix B explains hex numbering system.
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Chapter 27 The Status File Fault Classification Description Address Error Code (Hex) S:6 0001 NVRAM error. 0002 Processor User 5/02 5/01, Fixed X • • Unexpected hardware watchdog timeout. X • • 0003 Memory module memory error. X • 0004 Memory integrity check failed (runtime). X • Powerup Errors Non-User Non-Recov Recov Fault Classification Description Address Error Code (Hex) S:6 0010 Processor does not meet proper revision level.
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Chapter 27 The Status File Fault Classification Description Address S:6 Error Code (Hex) Runtime Errors 0020 A minor error bit is set at the end of the scan. (See S:5 minor error bits.) 0021 Remote power failure of an expansion I/O rack occurred.
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Chapter 27 The Status File Fault Classification Description Address Error Code (Hex) S:6 0030 Attempt was made to jump to one too many nested subroutine files. Can also mean that a program has potentially recursive routines. 0031 Unsupported instruction reference was detected. 0032 Sequencer length/position points past end of data file. 0033 0034 27–20 Processor User 5/02 5/01, Fixed X • • X • • X • • Length of LFU, LFL, FFU, FFL, BSL, or BSR points past end of data file.
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Chapter 27 The Status File SLOT NUMBERS (xx) IN HEXADECIMAL ERROR CODES: The characters xx in the following codes represent the slot number, in hex. If the exact slot cannot be determined, the characters xx become 1F.
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Chapter 27 The Status File Fault Classification Description Address S:6 27–22 Error Code (Hex) I/O Errors xx5C Processor User Non-User Non-Recov Recov 5/02 M0–M1 file configuration error – user program M0–M1 file size exceeds capacity of the module. X • xx5D Interrupt service requested is not supported by the processor. X • xx5E Processor I/O driver (software) error. X • xx60 thru xx6F Identifies an I/O module specific recoverable major error.
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Chapter 27 The Status File Address Description 5/02 5/01, Fixed S:7 and S:8 Suspend Code/Suspend File Read/write. When a non-zero value appears in S:7, it indicates that the SUS instruction identified by this value has been evaluated as true, and the Suspend Idle mode is in effect. This pinpoints the conditions in the application that caused the Suspend Idle mode. This value is not cleared by the processor.
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Chapter 27 The Status File Address Description 5/02 5/01, Fixed S:11 and S:12 I/O Slot Enables Read/write. These two words are bit mapped to represent the 30 possible I/O slots in an SLC 500 system. S:11/0 represents I/O slot 0 for fixed I/O systems (slot 0 is used for the CPU in modular systems); S:11/1 through S:12/14 represent I/O slots 1–30. S:12/15 is unused.
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Chapter 27 The Status File Address Description 5/02 5/01, Fixed S:13 and S:14 Math Register Read/write. Use this double register to produce 32 bit signed divide and multiply operations, precision divide or double divide operations, and 5 digit BCD conversions. • • These two words are used in conjunction with the MUL, DIV, DDV, FRD, and TOD math instructions.
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Chapter 27 The Status File Address Description 5/02 5/01, Fixed S:15H Baud Rate Read/write. This byte value contains a code used to select the baud rate of the processor on the DH–485 link. • • SLC 5/02 processors provide a baud rate of 19200, 9600, 2400, or 1200. SLC 5/01 and fixed processors provide a baud rate of 19200 or 9600 only. To change the baud rate from the default value of 19200, use either the EDT_DAT or NODE_CFG functions of your HHT.
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Chapter 27 The Status File Address Description 5/02 S:16 and S:17 Test Single Step – Start Step On – Rung/File Read only. These registers indicate the executable rung (word S:16) and file (word S:17) number that the processor will execute next when operating in the Test Single Step mode. To enable this feature, you must select the Test Single Step option at the time you save your program. • 5/01, Fixed These values are updated upon completion of every rung (see S:2/4).
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Chapter 27 The Status File Address Description 5/02 S:20 and S:21 Test – Fault/Powerdown – Rung/File Read/write. These registers indicate the executable rung (word S:20) and file (word S:21) number that the processor last executed before a major error or powerdown occurred. To enable this feature, you must select the Test Single Step option at the time you save your program. You can use these registers to pinpoint the execution point of the processor at the last powerdown or fault routine entry.
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Chapter 27 The Status File Address S:22 Description Maximum Observed Scan Time Read/write. This word indicates the maximum observed interval between consecutive scans. 5/02 5/01, Fixed • Consecutive scans are defined as: Intervals between file 2/rung 0 and the END instruction, TND instruction, or the REF instruction. This value indicates, in 10 ms increments, the time elapsed in the longest program cycle of the processor. The processor compares each last scan value to the value contained in S:22.
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Chapter 27 The Status File Address Description 5/02 S:25 and S:26 I/O Interrupt Pending Read only. These two words are bit-mapped to the 30 I/O slots. Bit S:25/1 through S:26/14 refer to slots 1–30. Bits S:25/0 and S:26/15 are reserved. • The pending bit associated with an interrupting slot is set when the corresponding I/O slot interrupt enable bit is clear at the time of an interrupt request.
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Chapter 27 The Status File Address Description 5/02 S:30 Selectable Timed Interrupt – Setpoint Read/Write. You enter the time base, in tens of milliseconds, to be used in the selectable timed interrupt. Your STI routine will execute per the value you enter. Write a 0 value to disable the STI.
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Chapter 27 The Status File Status File Display –SLC 5/02 Processors The status file displays that apply to SLC 5/02 processors are shown below. The displays are accessible offline and online under the EDT DAT function. To move between data files: Press NEXT FL or PREV FL. To move between displays: Press NEXT PG or PREV PG. To move the cursor from any data file address to any other data file address: Press ADDRESS, enter the address, then press ENTER.
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Chapter 27 The Status File Status File Display – SLC 5/01 and Fixed Processors The figures below are the status file displays that apply to the SLC 5/01 and fixed processors. The displays are accessible offline and online under the EDT DAT function. To move between data files: Press NEXT FL or PREV FL. To move between displays: Press NEXT PG or PREV PG. To move the cursor from any data file address to any other data file address: Press ADDRESS, enter the address, then press ENTER.
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Chapter 28 Troubleshooting Faults This chapter: • lists the major error fault codes • indicates the probable causes of faults • recommends corrective action Chapter 27 also lists the error codes, under word S:6. Troubleshooting Overview The following general information applies to troubleshooting.
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Chapter 28 Troubleshooting Faults Status File Fault Display The status file displays applying to major and minor faults are shown below. The displays are accessible offline and online under the EDT DAT function. Press NEXT__FL until you get to the status file. Move between displays by pressing NEXT__PG or PREV__PG.
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Chapter 28 Troubleshooting Faults Powerup Errors Error Code (Hex) 0001 Description NVRAM error. Probable Cause Recommended Action • Either Noise, • lightning, • improper grounding, • lack of surge suppression on outputs Correct the problem, reload the program, and run. You can use the autoload feature with a memory module to automatically reload the program and enter the Run mode. with inductive loads, or • poor power source. • Loss of battery or capacitor backup.
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Chapter 28 Troubleshooting Faults Error Code (Hex) 0014 Description Internal file error. Probable Cause Recommended Action • Either noise, • lightning, • improper grounding, • lack of surge suppression on outputs Correct the problem, reload the program, and run. If the error persists, be sure to use A-B approved programming device to develop and load the program. with inductive loads, or • poor power source. 0015 Configuration file error.
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Chapter 28 Troubleshooting Faults Error Code (Hex) 0021 Description A remote power failure of an expansion I/O rack has occurred. Note: A modular system that encounters an overvoltage or overcurrent condition in any of its power supplies can produce any of the I/O error codes listed on pages 28–8 to 28–10 (instead of code 0021). The overvoltage or overcurrent condition is indicated by the power supply LED being off.
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Chapter 28 Troubleshooting Faults Error Code (Hex) Description Probable Cause Recommended Action 0026 Excessive stack depth/JSR calls for an I/O interrupt routine. A JSR instruction is calling for a file number assigned to an I/O interrupt routine. Correct the user program to meet the requirements and restrictions for the JSR instruction, then reload the program and run. 0027 Excessive stack depth/JSR calls for the user fault routine.
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Chapter 28 Troubleshooting Faults Error Code (Hex) Description Probable Cause Recommended Action 0032 A sequencer instruction length/position parameter points past the end of a data file. The program is referencing an element beyond a file boundary set up by the sequencer instruction. Correct the user program or allocate more data file space using the memory map, then reload and run. 0033 The length parameter of an LFU, LFL, FFU, FFL, BSL, or BSR instruction points past the end of a data file.
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Chapter 28 Troubleshooting Faults I/O Errors SLOT NUMBERS (xx) IN HEXADECIMAL ERROR CODES: The characters xx in the following codes represent the slot number, in hex. The characters xx become 1F if the exact slot cannot be determined. RECOVERABLE I/O FAULTS (SLC 5/02 processors only): Many I/O faults are recoverable. To recover, you must disable the specified slot, xx, in the user fault routine. If you do not disable slot xx, the processor will fault at the end of the scan.
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Chapter 28 Troubleshooting Faults Error Code (Hex) xx55 Description A discrete I/O module required for the user program is detected as having the wrong I/O count. This code can also mean that a specialty card driver is incorrect. Probable Cause Recommended Action • If this is a discrete I/O module, the I/O • If this is a discrete I/O module, replace it count is different from that selected in the I/O configuration. • If this is a specialty I/O module, the card driver is incorrect.
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Chapter 28 Troubleshooting Faults Error Code (Hex) Description Probable Cause Recommended Action xx60 through xx6F Identifies an I/O module specific recoverable major error. Refer to the user manual for the specialty module for further details. – – xx70 through xx7F Identifies an I/O module specific non-recoverable major error. Refer to the user manual for the specialty module for further details. – – xx90 Interrupt problem on a disabled slot.
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Chapter 29 Understanding the User Fault Routine – SLC 5/02 Processor Only This chapter applies to the SLC 5/02 processor only. It covers the following topics: • recoverable and non–recoverable user faults • application examples of user fault subroutines Overview of the User Fault Routine The SLC 5/02 processor allows you to designate a subroutine file as a User Fault Routine. This file will be executed when any recoverable or non-recoverable user fault occurs.
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Chapter 29 Understanding the User Fault Routine – 5/02 Processor Only Recoverable User Faults GOING TO RUN ERRORS 0013 The required memory module is absent or either S:1/10 or S:1/11 is not set (and the program requires it). 0016 Startup protection after power loss. Error condition exists at powerup when bit S:1/9 is set and powerdown occurred while running. RUNTIME ERRORS 0020 A minor error bit is set at the end of the scan.
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Chapter 29 Understanding the User Fault Routine 5/02 Processor Only I/O ERRORS Recoverable only if you disable slot xx in the user fault routine xx50 A rack data error is detected. xx52 A module required for the user program is detected as missing or removed. xx53 At going-to-run, a user program declares a slot as unused, and that slot is detected as having an I/O module inserted. Can also mean that the I/O module has reset itself.
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Chapter 29 Understanding the User Fault Routine – 5/02 Processor Only Non-Recoverable User Faults An example of using a non-recoverable user fault in a user fault routine would be to initiate a MSG instruction to inform another node of the fault condition. Non-recoverable user faults: RUNTIME ERRORS 0022 User watchdog scan time exceeded. 0023 Invalid or non-existent STI interrupt file. 0024 Invalid STI interrupt interval (greater than 2559ms or negative).
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Chapter 29 Understanding the User Fault Routine 5/02 Processor Only Creating a User Fault Subroutine To utilize the user fault routine, create a subroutine file (3–255), then enter this file number in word S:29 of the status file.
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Chapter 29 Understanding the User Fault Routine – 5/02 Processor Only Word S:6 is the fault code (in decimal).
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Chapter 29 Understanding the User Fault Routine 5/02 Processor Only SBR C5:0 (U) CU S:5 ] [ SUBROUTINE 0 CTU COUNT UP Counter Preset Accum GRT (CU) C5:0 120 0 (DN) RET GREATER THAN Source A C5:0.ACC 0 Source B 5 RETURN S:5 (U) 0 S:5 ] [ 0 S:1 (U) 13 RET RETURN END Subroutine File 4 – Executed for error 0020 MINOR ERROR AT END OF SCAN If the overflow trap bit S:5/0 is set, counter C5:0 will increment.
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Chapter 29 Understanding the User Fault Routine – 5/02 Processor Only SBR LES SUBROUTINE S:1 (U) 13 LESS THAN Source A T4:0.ACC 0 Source B 0 CLR CLEAR Dest T4:0.ACC 0 O:3.0 ( ) 3 RET RETURN END Subroutine File 5 – Executed for error 0034 NEGATIVE VALUE IN TIMER PRE OR ACC If the accumulator value of timer T4:0 is negative, the major error halted bit, S:1/13 is unlatched, preventing the processor from entering the fault mode. At the same time, the accumulator value T4:0.
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Chapter A–B 30 Understanding Selectable Timed Interrupts – SLC 5/02 Processor Only This chapter applies to the SLC 5/02 processor only. It covers the following topics: • STI operation • STI parameters • STD and STE instructions • STS instruction • INT instruction STI Overview The STI (selectable timed interrupt) function can be used with the SLC 5/02 processor only.
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Chapter 30 Understanding Selectable Timed Interrupts – 5/02 Processor Only STI Subroutine Content For identification of your STI subroutine, include an INT instruction as the first instruction. This identifies the subroutine as an interrupt subroutine versus a normal subroutine. The STI subroutine will contain the rungs of your application logic. You can program any instruction inside the STI subroutine except a TND, REF, or SVC instruction.
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Chapter 30 Understanding Selectable Timed Interrupts – 5/02 Processor Only Interrupt Priorities Interrupt priorities are as follows: 1. Fault routine 2. STI subroutine 3. I/O interrupt subroutine (ISR) An executing interrupt can only be interrupted by an interrupt having higher priority. Status File Data Saved Data in the following words is saved on entry to the STI subroutine and re-written upon exiting the STI subroutine.
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Chapter 30 Understanding Selectable Timed Interrupts – 5/02 Processor Only STI Parameters The following parameters are associated with the STI function. These parameters have status file addresses. They are described here and also in chapter 27. Word S:31 STI file number – This can be any number from 3 to 255. A value of zero disables the STI function. An invalid number will generate fault 0023. Word S:30 Setpoint – This is the time between the starting point of successive scans of the STI file.
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Chapter 30 Understanding Selectable Timed Interrupts – 5/02 Processor Only Enter and monitor STI parameters at the status file displays under EDT_DAT. Parameters are pointed out in the displays that follow.
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Chapter 30 Understanding Selectable Timed Interrupts – 5/02 Processor Only STD and STE Instructions The STD and STE instructions are used to create zones in which STI interrupts cannot occur. These instructions are not required to configure a basic STI interrupt application. Selectable Timed Disable Selectable Timed Enable HHT Ladder Display: HHT Zoom Display: (monitor mode) STD STE (STD) Output Instruction Output Instruction (STE) ZOOM on STD –(STD)– 2.6.0.0.
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Chapter 30 Understanding Selectable Timed Interrupts – 5/02 Processor Only STD/STE Zone Example In the program below, the STI function is in effect. The STD and STE instructions in rungs 6 and 12 are included in the ladder program to avoid having STI subroutine execution at any point in rungs 7 thru 11. The STD instruction (rung 6) resets the STI enable bit and the STE instruction (rung 12) sets the enable bit again.
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Chapter 30 Understanding Selectable Timed Interrupts – 5/02 Processor Only STS Instruction The STS instruction can be used to condition the start of the STI timer upon entering the Run mode – rather than starting automatically. It can also be used to set up or change the file number or setpoint/frequency of the STI routine that will be executed when the STI timer expires. This instruction is not required to configure a basic STI interrupt application.
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Chapter 30 Understanding Selectable Timed Interrupts – 5/02 Processor Only INT Instruction The Interrupt Subroutine (INT) instruction is used in selectable timed interrupt subroutines and I/O event–driven interrupt subroutines to distinguish the subroutine as an interrupt subroutine versus a regular subroutine. Use of the instruction is optional. Interrupt Subroutine HHT Ladder Display: HHT Zoom Display: (online monitor mode) INT INT ZOOM on INT –|INT|– NAME: I/O INTERRUPT 2.3.0.0.
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Chapter A–B 31 Understanding I/O Interrupts – SLC 5/02 Processor Only This chapter applies to the SLC 5/02 processor only. It covers the following topics: • I/O interrupt operation • I/O interrupt parameters • IID and IIE instructions • RPI instruction • INT instruction I/O Overview The I/O event-driven interrupt function can be used with the SLC 5/02 processor only.
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Chapter 31 Understanding I/O Interrupts – 5/02 Processor Only Operation When you download your program and enter the Run mode, the I/O interrupt begins operation as follows: • The specialty I/O module determines that it needs servicing and generates an interrupt request to the SLC processor. • The processor is interrupted from what it is doing, and the specified interrupt subroutine file (ISR) is scanned. • When the ISR scan is completed, the specialty I/O module is notified.
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Chapter 31 Understanding I/O Interrupts – 5/02 Processor Only Interrupt Latency The interrupt latency (interval between the detection of an interrupt request from the specialty I/O module and the start of the interrupt subroutine) is 3.7 milliseconds max. for the SLC 5/02 series B processor, and 2.4 milliseconds max. for the SLC 5/02 series C and later. During the latency period, the processor is performing operations that cannot be disturbed by the I/O interrupt function.
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Chapter 31 Understanding I/O Interrupts – 5/02 Processor Only Status File Data Saved Data in the following words is saved on entry to the I/O interrupt subroutine and re-written upon exiting the I/O interrupt subroutine. • S:0 Arithmetic flags • S:13 and S:14 Math register • S:24 Index register I/O Interrupt Parameters The I/O interrupt parameters below have status file addresses. They are described here and also in chapter 27. S:11 and S:12 I/O Slot Enables – Read/Write.
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Chapter 31 Understanding I/O Interrupts – 5/02 Processor Only You can enter and monitor parameters at the status file displays, under EDT_DAT. Parameters are pointed out in the displays below.
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Chapter 31 Understanding I/O Interrupts – 5/02 Processor Only IID and IIE Instructions The IID and IIE instructions are used to create zones in which I/O interrupts cannot occur. These instructions are not required to configure a basic I/O interrupt application. I/O Interrupt Disable I/O Interrupt Enable HHT Ladder Display: HHT Zoom Display: (online monitor mode) IID IIE (IID) Output Instruction Output Instruction (IIE) ZOOM on IID –(IID)– 2.4.0.0.
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Chapter 31 Understanding I/O Interrupts – 5/02 Processor Only IID I/O Interrupt Disable – When true, this instruction clears the I/O interrupt enable bits (S:27/1 through S:28/14) corresponding to the slots parameter of the instruction (slots 1, 2, 7 in the following example). Interrupt subroutines of the affected slots will not be able to execute when an interrupt request is made. Instead, the corresponding I/O pending bits (S:25/1 through S:26/14) will be set.
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Chapter 31 Understanding I/O Interrupts – 5/02 Processor Only IID/IIE Zone Example In the program below, slots 1, 2, and 7 are capable of generating I/O interrupts. The IID and IIE instructions in rungs 6 and 12 are included to avoid having I/O interrupt ISRs execute as a result of interrupt requests from slots 1, 2, or 7. This allows rungs 7 through 11 to execute without interruption.
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Chapter 31 Understanding I/O Interrupts – 5/02 Processor Only RPI Instruction The RPI instruction is used to purge unwanted I/O interrupt requests. This instruction is not required to configure a basic I/O interrupt application. Reset Pending Interrupt HHT Ladder Display: HHT Zoom Display: (online monitor mode) RPI Output Instruction (RPI) ZOOM on RPI –(RPI)– 2.0.0.0.
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Appendix A HHT Messages and Error Definitions This appendix provides details about the messages that appear on the prompt line of the HHT display. These messages prompt you regarding programming procedures, restrictions, and limitations. They also bring your attention to errors such as incorrect procedures, incorrect data entry, failure of selftest functions, and hardware/software incompatibility. The messages in this chapter refer specifically to HHT operations. They are listed in alphabetical order.
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Appendix A HHT Messages and Error Definitions Message: Appears when: Respond by: The instruction or rung you are attempting to delete may contain the only reference to a data location. Answering YES if you want to continue the deletion. Answering NO if you wish to abort the deletion. Forces are present on the instruction or in the rung you are attempting to delete. Answering YES if you want to continue the deletion. Answering NO if you wish to abort the deletion.
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Appendix A HHT Messages and Error Definitions Message: Appears when: Respond by: HSC INSTRUCTION, FILE X, RUNG Y This processor type does not allow HSC instructions. Removing any HSC instructions in your ladder program. ILLEGAL ADDRESS The processor is requested to read/write data to a non–existent ladder program file address or non–existent data table. Creating the ladder program file address or aborting the procedure. The processor does not understand the command received from the HHT.
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Appendix A HHT Messages and Error Definitions Message: Appears when: Respond by: INVALID OPERAND The address entered is not a valid data file operand. Entering a valid address. INVALID PROCESSOR TYPE This processor type is incompatible with your present ladder program. There are references to inputs and outputs in your program which do not exist in this processor type. Choosing a different processor type or modifying your ladder program.
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Appendix A HHT Messages and Error Definitions Message: Appears when: Respond by: You are trying to attach the HHT to either itself or a non–processor device while in the WHO utility. Using the [ ↓ ] or [ ↑ ] keys to change the order of the nodes listed on the WHO screen. Put the processor at the top of the list and try to attach. You are trying to attach the HHT to a non–existent device, or no devices are shown on the WHO screen.
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Appendix A HHT Messages and Error Definitions Message: Appears when: Respond by: PASSWORD NOT CHANGED The password or master password currently protecting the ladder program or processor has not been entered correctly. You must enter the old password before changing it. Entering the current password correctly. POSITION IS TOO LARGE The position parameter entered is larger than the data file indicated. Correcting the position value.
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Appendix A HHT Messages and Error Definitions Message: Appears when: Respond by: The syntax of the current rung is incorrect. Correcting the rung. The syntax of the current rung is incorrect. Correcting the rung. TOO MANY INSTRUCTIONS ON RUNG The rung contains more than 127 instructions. Changing the rung to contain fewer instructions. TOO MANY INSTRUCTIONS ON RUNG The rung contains more than 127 instructions. Changing the rung to contain fewer instructions.
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Appendix A HHT Messages and Error Definitions Message: UPDATE ACCUMULATOR (UA) IN OUTPUT ENERGIZE/ OUTPUT LATCH (OTE/OTL) AND NO HIGH SPEED COUNTER (HSC) Appears when: Respond by: You have programmed an update accumulator (UA) bit without first programming a high–speed counter (HSC). Programming the high–speed counter (HSC) instruction. You have programmed an update accumulator (UA) bit without first programming a high–speed counter (HSC). Programming the high–speed counter (HSC) instruction.
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Appendix B Number Systems, Hex Mask This appendix: • describes the different number systems you need to understand for use of the HHT with SLC 500 family controllers • covers binary, Binary Coded Decimal (BCD), and hexadecimal. • explains the use of a Hex mask used to filter data in certain programming instructions Binary Numbers The processor memory stores 16-bit binary numbers.
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Appendix B Number Systems, Hex Mask Other examples: 16 bit pattern = 0000 1001 0000 11102 = 211 + 28 + 23 + 22 + 21 = 2048 + 256 + 8 + 4 + 2 = 2318 16 bit pattern = 0010 0011 0010 10002 = 213 + 29 + 28 + 25 + 23 = 8192 + 512 + 256 + 32 + 8 = 9000 Negative Decimal Values The 2s complement notation is used. The far left position is always 1 for negative values.
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Appendix B Number Systems, Hex Mask Another example: 16–bit pattern = 1111 1000 0010 00112 = ( 214 + 213 + 212 + 211 + 25 = ( 16384 + 8192 + 4096 + 2048 + 32 = 30755 = –2013 + 21 + 2 + 20 ) – 215 + 1 ) – 32768 – 32768 An easier way to calculate a negative value is to locate the last “1” in the string of 1s beginning at the left, then subtract its value from the total value of positions to the right of that position.
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Appendix B Number Systems, Hex Mask Example: BCD bit pattern 01112, for one digit, has a decimal equivalent value of 7: 0x23 = 0 1x22 = 4 1x21 = 2 1x20 = 1 + 0 4 2 1 7 0 1 1 1 To form multiple digit numbers, BCD uses a 16–bit pattern similar to binary. This allows up to 4 digits, using the above 4–bit binary code. BCD numbers have a range of 0 to 32,767 in the SLC 500 family processors.
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Appendix B Number Systems, Hex Mask Hexadecimal and binary numbers have the following equivalence: Hexadecimal Binary 2 1 8 A = 8586 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 8192 1x213 256 1x28 128 1x27 10 1x23+1x21 = 8586 Example: Decimal number –8586 in equivalent binary and hexadecimal forms: Binary 1 1 0 1 1 1 1 0 Hexadecimal 0 1 1 1 D E 7 6 0 1 1 0 = –8586 = 56950 (negative number, –8586) Hex number DE76 = 13x163+14x162+7x161+6x160 = 56950.
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Appendix B Number Systems, Hex Mask Bits of the mask word that are set (1) pass data from a source to a destination. Reset bits (0) do not. In the example below, data in bits 0–7 of the source word is passed to the destination word. Data in bits 8–15 of the source word is not passed to the destination word. Destination bits 8–15 are not affected (they are left in their last state).
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Appendix A–B C Memory Usage, Instruction Execution Times This appendix covers the following topics: • memory usage • instruction execution times for the fixed and SLC 5/01 processors • instruction execution times for the SLC 5/02 processor series A and B • instruction execution times for the SLC 5/02 processor series C and later Memory Usage SLC 500 controllers have the following user memory capacities: Type of Processor Type of Controller User Memory Capacity Fixed I/O Controllers Fixed and SLC 5/0
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Appendix C Memory Usage, Instruction Execution Times Fixed and SLC 5/01 Processors Instruction Words for the Fixed and SLC 5/01 Processors Instruction C–2 Instruction Words (approx) ADD AND 1.5 1.5 BSL BSR 2 2 CLR COP CTD CTU 1 1.5 1 1 DCD DDV DIV 1.5 1 1.5 EQU 1.5 FLL FRD 1.5 1 GEQ GRT 1.5 1.5 HSC 1 IIM IOM 1.5 1.5 JMP JSR 1 1 LBL LEQ LES 0.5 1.5 1.5 Instruction Instruction Words (approx) MCR MEQ MOV MUL MVM 0.5 1.5 1.5 1.5 1.5 NEG NEQ NOT 1.5 1.5 1 OR OSR OTE OTL OTU 1.
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Appendix C Memory Usage, Instruction Execution Times Estimating Total Memory Usage of Your System Using a Fixed or SLC 5/01 Processor 1. Calculate the total instruction words used by the instructions in your program and enter the result. Refer to the table on page C–2. 2. Multiply the total number of rungs by .375 and enter the result. 3. Multiply the total number of data words (excluding the status file and I/O data words) by .25 and enter the result. 4.
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Appendix C Memory Usage, Instruction Execution Times Example: L20B Fixed I/O Controller 42 XIC and XIO 10 OTE instructions 10 TON instructions 1 CTU instruction 1 RES instruction Instruction Usage 42 10 10 1 1 x x x x x 1.00 0.75 1.00 1.00 1.00 = 42.00 = 7.50 = 10.00 = 1.00 = 1.00 61.50 21 rungs 37 data words User Program Total 21 x.375 = 37 x.250 = 7.87 9.25 78.62 2 I/O data words 1 slot Overhead I/O Configuration Total 2 x 0.75 = 1 x 0.75 = 1.50 0.75 65.00 67.
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Appendix C Memory Usage, Instruction Execution Times Instruction Execution Times for the Fixed and SLC 5/01 Processors Execution Time in Microseconds (approx.
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Appendix C Memory Usage, Instruction Execution Times SLC 5/02 Processor The number of instruction words used by an instruction is indicated in the following table. Since the program is compiled by the programmer, it is only possible to establish estimates for the instruction words used by individual instructions. The calculated memory usage will normally be greater than the actual memory usage, due to compiler optimization.
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Appendix C Memory Usage, Instruction Execution Times Estimating Total Memory Usage of Your System Using a SLC 5/02 Processor 1. Calculate the total instruction words used by the instructions in your program and enter the result. Refer to the table on page C–6. 2. Multiply the total number of rungs by .375 and enter the result. 3. If you are using a 1747–L524 and have enabled the Single Step Test mode, multiply the total number of rungs by .375 and enter the result. 4.
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Appendix C Memory Usage, Instruction Execution Times Instruction Execution Times for the SLC 5/02 Processor Series A or B Instruction (Series A or B SLC 5/02) C–8 Execution Time in Microseconds (approx.) False True Instruction (Series A or B SLC 5/02) Execution Time in microseconds (approx.
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Appendix C Memory Usage, Instruction Execution Times Instructions Having Indexed Addresses For each operand having an indexed address, add 50 microseconds to the execution time for a true instruction. For example, if a MOV instruction has an indexed address for both the source and destination, the execution time when the instruction is true is 24 + 50 + 50 = 124 microseconds. Instructions Having M0 or M1 Data File Addresses For each bit or word instruction, add 1928 microseconds to the execution time.
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Appendix C Memory Usage, Instruction Execution Times Instruction Execution Times for the SLC 5/02 Processor Series C and Later The SLC 5/02 series C processor performance is on the average 40% faster than that of the SLC 5/02 series B processor. The table below lists the instruction execution times for the SLC 5/02 series C processor. Instruction (Series C SLC 5/02) Execution Time in Microseconds (approx.) False True Instruction (Series C SLC 5/02) Execution Time in Microseconds (approx.
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Appendix C Memory Usage, Instruction Execution Times Example: 1747-L524 series C processor, 30-slot configuration, (15) 1746-IA16, (10) 1746-OA8, (1) 1747-DCM full configuration, (1) 1746-NI4, (1) 1746-NIO4I 50 XIC and XIO 15 OTE instructions 5 TON instructions 3 GRT instructions 1 SCL instruction 1 TOD instruction 3 MOV instructions 10 CTU instructions 10 RES instructions Instruction Usage 50 15 5 3 1 1 3 10 10 x x x x x x x x x 1.00 0.75 1.00 1.50 1.75 1.00 1.50 1.00 1.00 30 rungs 30 x 0.
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Appendix C Memory Usage, Instruction Execution Times Instructions Having Indexed Addresses For each operand having an indexed address, add 30 microseconds to the execution time for a true instruction. For example, if a MOV instruction has an indexed address for both the source and destination, the execution time when the instruction is true is 14 + 30 + 30 = 74 microseconds. Instructions Having M0 and M1 Data File Addresses For each bit or word instruction, add 1157 microseconds to the execution time.
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Appendix A–B D Estimating Scan Time This appendix: • contains worksheets that allow you to estimate the scan time for your particular controller configuration and program • includes scan time calculation for an example controller and program Use the instruction execution times listed in appendix C. Events in the Operating Cycle The diagram and table below breaks down the processor operating cycle into events. Directions for calculating the scan time of these events appear in the worksheets.
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Appendix D Estimating Scan Time Scan Time Worksheets Worksheets A, B, and C on the following pages are for use with SLC 500 systems as follows: • Worksheet A – Fixed controllers • Worksheet B – 1747-L511 or 1747-L514 processor • Worksheet C – 1747-L524 processor These worksheets are intended to assist you in estimating scan time for your application. Refer to appendix C for instruction execution times. Refer to the SLC 500 System Overview, publication 1747–2.30, for I/O module part numbers and sizes.
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Appendix D Estimating Scan Time Worksheet A — Estimating the Scan Time of Your Fixed Controller Procedure 1. B. C. D. E. F. 2. C. D. E. F. Calculate the processor input scan of your discrete input modules. Number of 8 point modules ________ x 197 = Number of 16 point modules ________ x 313 = Number of 32 point modules ________ x 545 = b.)________ c.)________ d.)________ Calculate the processor input scan of your specialty I/O modules.
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Appendix D Estimating Scan Time Worksheet B — Estimating the Scan Time of Your 1747–L511 or 1747–L514 Processor Procedure Min Scan Time 1. Estimate your input scan time (µs). A. Calculate the processor input scan of your discrete input modules. Number of 8 point modules ________ x 197 = Number of 16 point modules ________ x 313 = Number of 32 point modules ________ x 545 = B. Calculate the processor input scan of your specialty I/O modules.
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Appendix D Estimating Scan Time Worksheet C — Estimating the Scan Time of Your 1747–L524 Processor Procedure Min Scan Time Max ScanTime 1. Estimate your input scan time (µs). A. Calculate the processor input scan of your discrete input modules. Number of 8 point modules ________ x 126 = a.)________ Number of 16 point modules ________ x 195 = b.)________ Number of 32 point modules ________ x 335 = c.)________ B. Calculate the processor input scan of your specialty I/O modules.
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Appendix D Estimating Scan Time Example Scan Time Calculation Suppose you have a system consisting of the following components: System Configuration Description Catalog Number Quantity 1747–L514 1746–IA8 1746–IB16 1746–OA16 1746–OB8 1746–NIO4V 1 2 1 3 1 1 4K Processor 8 point 120VAC Input Module 16 point 24VDC Sinking Input Module 16 point 120VAC Relay Output Module 16 point 24VDC Sourcing Output Module 4 Channel Analog Combination Module Since you are using the 1747-L514 processor, worksheet B must
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Appendix D Estimating Scan Time Example: Worksheet B – Estimating the Scan Time of a 1747–L514 Processor Application Procedure: Min Scan Time: 1. Estimate your input scan time (µs). A. Calculate the processor input scan of your discrete input modules. Number of 8 point modules 2 Number of 16 point modules 1 Number of 32 point modules 0 x 197 = x 313 = x 545 = a.) b.) c.) 394 313 0 B. Calculate the processor input scan of your specialty I/O modules.
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Index Hand–Held Terminal User Manual Symbols #, addressing user–created files with, 4–16 Numbers 1–rung ladder program, 5–2 1747–AIC, link coupler, 1–6 1747–BA battery installation, 1–5 memory retention, 1–1 1747–C10, communication cable, 1–6 1747–NP1, –NP2, remote programming with, 1–1 1747–PTA1E, memory pak installation, 1–3 4–rung ladder program, 5–8 5/01 processor instruction words, C–2 status file displays, 27–33 5/02 processor controller memory usage, C–1 instruction words, C–6 status file, 27–1 sta
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Index Hand–Held Terminal User Manual clear (CLR) math instruction, 15–5, 20–11 mnemonic listing, 2–14 clearing the memory of the HHT, 6–1 communication cable, installing, 1–3 comparison instructions, 15–4, 19–1 equal (EQU), 15–4, 19–2 greater than (GRT), 15–4, 19–6 greater than or equal (GEQ), 15–4, 19–7 less than (LES), 15–4, 19–4 less than or equal (LEQ), 15–4, 19–5 limit test (LIM), 15–4, 19–9 masked comparison for equal (MEQ), 15–4, 19–8 not equal (NEQ), 15–4, 19–3 configure your HHT for online communi
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Index Hand–Held Terminal User Manual timer files, 12–8 data file G, 4–27 editing data, 4–28 data file protection, 12–3 data file types file 2 – status, 4–3 file 3 – bit, 4–8 file 4 – timers, 4–9 file 5 – counters, 4–10 file 6 – control, 4–11 file 7 – integer, 4–12 file G, 4–27 file M0, 4–21 file M1, 4–21 files 0 and 1 – outputs and inputs, 4–4 influence on address formatting, 4–3 data files, 3–3 addressing, 4–2 default types, 3–3, 4–2 monitoring, 12–2 organization of, 4–1 protection of, 12–3 residing in sp
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Index Hand–Held Terminal User Manual equal (EQU) comparison instruction, 15–4, 19–2 mnemonic listing, 2–14 error codes, 28–2 going to run, 28–3 I/O, 28–8 powerup, 28–3 recoverable I/O faults, 28–8 runtime, 28–4 user program instruction, 28–6 ESCAPE key, 2–2 estimating scan time for your controller and program, D–1 example, D–6 worksheets, D–2 examine if closed (XIC) bit instruction, 5–1, 15–1, 16–2 mnemonic listing, 2–15 file fill (FLL) file copy and file fill instruction, 15–6, 22–4 mnemonic listing, 2–1
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Index Hand–Held Terminal User Manual cursor keys, 1–10 data entry keys, 1–9 ENTER key, 2–2 ESCAPE key, 2–2 menu function keys, 1–9 RUNG key, 1–12 ZOOM key, 1–12 HHT main menu functions, 2–3 HHT messages and error definitions alphabetical listing, A–1 warning messages, A–8 HHT program, in relation to APS, 3–1 high–speed counter (HSC) mnemonic listing, 2–14 timer and counter instructions, 15–2, 17–9 immediate input with mask (IIM) I/O message and communications instructions, 15–3, 18–15 mnemonic listing, 2–
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Index Hand–Held Terminal User Manual selectable timed enable (STE), 25–10 selectable timed interrupt (STI), 25–10 selectable timed start (STS), 25–10 sequencer load (SQL), 24–7 service communications (SVC), 18–14 square root (SQR), 20–20 subtract (SUB), 20–5 LIFO load (LFL) 5/02 processor, 23–8 LIFO instruction, 15–7, 23–8 mnemonic listing, 2–14 integer data file display, 12–9 LIFO unload (LFU) 5/02 processor, 23–8 LIFO instruction, 15–7, 23–8 mnemonic listing, 2–14 interrupt subroutine (INT) 5/02 proc
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Index Hand–Held Terminal User Manual instruction status bits, 18–7 mnemonic listing, 2–14 modifying branches, 7–19 appending a branch, 7–24 extending a branch down, 7–22 extending a branch up, 7–19 modifying instructions, 7–16 changing the address of an instruction, 7–16 changing the instruction type, 7–18 modifying rungs, 7–14 adding an instruction to a rung, 7–14 number systems, B–1 BCD, B–3 binary, B–1 hex mask, B–5 hexadecimal, B–4 O one–shot rising (OSR) bit instruction, 15–1, 16–7 mnemonic listing,
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Index Hand–Held Terminal User Manual explanation of, 26–3 instruction flags, 26–9 mnemonic listing, 2–15 online data changes, 26–14 runtime errors, 26–11 processor modes, 11–1 program mode, 11–1 run mode, 11–1 test mode, 11–2 search function, 7–35 reversing the search direction, 7–41 searching for an address, 7–38 searching for an instruction, 7–37 searching for an instruction within an address, 7–40 searching for forced I/O, 7–42, 13–6 searching for rungs, 7–44 program, 3–2 searching for an address, 7
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Index Hand–Held Terminal User Manual mnemonic listing, 2–15 sequencer instruction, 15–7, 24–7 sequencer output (SQO) mnemonic listing, 2–15 sequencer instruction, 15–7, 24–2 series logic, 5–4 service communications (SVC) 5/02 processor, 18–14 I/O message and communications instructions, 15–3, 18–14 mnemonic listing, 2–15 specifications certification, 1–1 communications, 1–1 compatibility, 1–1 dimensions, 1–1 display, 1–1 environmental, 1–1 humidity rating, 1–1 keyboard, 1–1 memory retention, 1–1 operating
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Index Hand–Held Terminal User Manual creating a user fault subroutine, 29–5 non–recoverable faults, 29–1 recoverable faults, 29–1 uploading a program from a processor to the HHT, 10–3 uploading program from processor to HHT, 3–4 using memory modules (EEPROM and UVPROM), EEPROM burning options, 14–5 5/01 and fixed controller, 14–5 5/02 processor, 14–5 using the file indicator #, 4–16 UVPROMs, 3–4 program loading with, 14–6 W WHO function, 9–4 attach, 9–7 diagnostics, 9–6 node configuration, 9–8 set and cle
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Allen-Bradley has been helping its customers improve productivity and quality for 90 years. A-B designs, manufactures and supports a broad range of control and automation products worldwide. They include logic processors, power and motion control devices, man-machine interfaces and sensors. Allen-Bradley is a subsidiary of Rockwell International, one of the world’s leading technology companies. With major offices worldwide.