User guide

Chapter 27
The Status File
27–13
Address Description 5/02
5/01,
Fixed
S:3H Watchdog Scan Time Byte
Read/write. This byte value contains the number of 10 ms ticks
allowed to occur during a program cycle. The default value is 10 (100
ms) but you can increase this to 250 (2.5 seconds) or decrease it to 2,
as your application requires. If the program scan S:3L value equals
the watchdog value, a watchdog major error will be declared (code
0022).
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S:4 Free Running Clock
Discussion applies to SLC 5/01 and fixed processors only.
Read only.
Only the first 8 bits (byte value) of this word are assessed
by the processor. This value is zeroed at powerup in the Run mode.
With the Series B SLC 5/01 processor, this value is also zeroed at
each entry into the run or test mode. It is incremented every 10 ms
thereafter.
You can use any individual bit of this byte in your user program as a
50% duty cycle clock bit. Clock rates for S:4/0 to S:4/7 are:
20, 40, 80, 160, 320, 640, 1280, and 2560 milliseconds.
The application using the bit must be evaluated at a rate more than
two times faster than the clock rate of the bit. This is illustrated in the
example below for SLC 5/02 processors.
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Free Running Clock
Discussion applies to SLC 5/02 processors only.
Read/write. All 16 bits of this word are assessed by the processor.
The value of this word is zeroed upon power up in the Run mode or
entry into the run or test mode. It is incremented every 10 ms
thereafter.
Application note: You can write any value to S:4. It will begin
incrementing from this value.
You can use any individual bit of this word in your user program as a
50% duty cycle clock bit. Clock rates for S:4/0 to S:4/15 are:
20, 40, 80, 160, 320, 640, 1280, 2560, 5120, 10240, 20480,
40960, 81920, 163840, 327680, and 655360 milliseconds.
The application using the bit must be evaluated at a rate more than
two times faster than the clock rate of the bit. In the example below,
bit S:4/3 toggles every 80 ms, producing a 160 ms clock rate. To
maintain accuracy of this bit in your application, the instruction using
bit S:4/3 (O:1/0 in this case) must be evaluated at least once every
79.999 ms.
160 ms
S:4/3 cycles in 160 ms
Both S:4/3 and Output O:1/0 toggle
every 80 ms. O:1/0 must be evaluated
at least once every 79.999 ms.
] [
S:4
3
( )
O:1
0
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