Datasheet

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 2011 Microchip Technology Inc. Preliminary DS41576B

PIC12F752/HV752

Data Sheet

8-Pin, Flash-Based 8-Bit

CMOS Microcontrollers

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450.

Additional U.S. and foreign patents and applications may be issued or pending.

Summary of content (210 pages)

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PIC12F752/HV752 Data Sheet 8-Pin, Flash-Based 8-Bit CMOS Microcontrollers *8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.  2011 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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PIC12F752/HV752 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers High-Performance RISC CPU: Peripheral Features: • Only 35 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 20 MHz clock input - DC – 200 ns instruction cycle • 1024 x 14 On-chip Flash Program Memory • Self Read/Write Program Memory • 64 x 8 General Purpose Registers (SRAM) • Interrupt Capability • 8-Level Deep Hardware Stack • Direct, Indirect and Relative Addressing modes • 5 I/O Pins and 1 Inp
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PIC12F752/HV752 4 2 3/1 1 Y N 6 4 2 3/1 1 Y Y Note: DS41576B-page 4 I/Os SRAM (bytes) 8-PIN DIAGRAM, PIC12F752/HV752 (PDIP, SOIC, DFN) VDD 1 RA5 2 RA4 3 MCLR/VPP/RA3 4 PIC12F752/HV752 FIGURE 1: CCP 6 64 Timers 8/16-bit 64 Y Comparators Y 1024 10-bit A/D (ch) 1024 PIC12HV752 Self Read/Write Flash Memory PIC12F752 Device Flash Program Memory (User) (words) Shunt Regulator PIC12F752/HV752 FEATURE SUMMARY Complementary Output Generator (COG) TABLE 1: 8 VSS 7 RA
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PIC12F752/HV752 CCP Interrupts Pull-up Complementary Output Generator (COG) AN0 C1IN0+ C2IN0+ — — IOC Y COG1OUT1(2) DACOUT REFOUT ICSPDAT RA1 6 AN1 C1IN0C2IN0- — — IOC Y — VREF+ ICSPCLK RA2(5) 5 AN2 C1OUT C2OUT T0CKI CCP1 IOC INT Y COG1OUT0(2) — — RA3(1) 4 — — T1G(3) IOC Y(4) COG1FLT(3) — MCLR/VPP (2) — Basic Timers 7 Voltage Reference ADC RA0(5) Comparators Pin PIC12F752/HV752 PIN SUMMARY (PDIP, SOIC, DFN) I/O TABLE 2: (2) — IOC Y COG1FLT COG1OU
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PIC12F752/HV752 Table of Contents 1.0 Device Overview ......................................................................................................................................................................... 9 2.0 Memory Organization ................................................................................................................................................................ 11 3.0 Flash Program Memory Self Read/Self Write Control ............................................
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PIC12F752/HV752 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.
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PIC12F752/HV752 NOTES: DS41576B-page 8 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 1.0 DEVICE OVERVIEW Block Diagrams and pinout descriptions of the devices are in Figure 1-1 and Table 1-1. The PIC12F752/HV752 devices are covered by this data sheet. They are available in 8-pin PDIP, SOIC and DFN packages.
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PIC12F752/HV752 TABLE 1-1: PIC12F752/HV752 PINOUT DESCRIPTION Name Function RA0 RA0/COG1OUT1(2)/C1IN0+/ C2IN0+/AN0/DACOUT/ COG1OUT1 REFOUT/ C1IN0+ ICSPDAT C2IN0+ RA1/C1IN0-/C2IN0-/AN1/ VREF+/ICSPCLK RA2/INT/CCP1/C2OUT/ C1OUT/T0CKI/ COG1OUT0(2)/AN2 RA3(1)/T1G(3)/COG1FLT(3)/ VPP/MCLR(4) RA4/T1G(2)/COG1OUT1(3)/ COG1FLT(2)/C1IN1-/AN3/ CLKOUT RA5/T1CKI/COG1OUT0(3)/ C2IN1-/CLKIN Input Type Output Type TTL HP General purpose I/O with IOC and WPU. — HP COG output channel 1.
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PIC12F752/HV752 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization 2.2 The PIC12F752/HV752 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh) is physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 1K x 14 space for PIC12F752/HV752. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).
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PIC12F752/HV752 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 64 x 8 in the PIC12F752/HV752. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM.
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PIC12F752/HV752 FIGURE 2-2: DATA MEMORY MAP OF THE PIC12F752/HV752 BANK 0 INDF TMR0 PCL STATUS FSR PORTA — — IOCAF — PCLATH INTCON PIR1 PIR2 — TMR1L TMR1H T1CON T1GCON CCPR1L CCPR1H CCP1CON — — — — — — ADRESL ADRESH ADCON0 ADCON1 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h BANK 1 INDF OPTION_REG PCL STATUS FSR TRISA — — IOCAP — PCLATH INTCON PIE1 PIE2 — OSCCON FVRCON DACCON0 DACCON1 — — — — — — — — CM2CON0 CM2CON1 CM
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PIC12F752/HV752 TABLE 2-1: Adr PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Reset Value on all other Resets(1) Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h TMR0 Holding register for the 8-bit TMR0 xxxx xxxx uuuu uuuu 02h PCL Program Counter's (PC) Least Significant Byte 03h STATUS 04h FSR 05h PORTA 06h — Unimplemen
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PIC12F752/HV752 TABLE 2-2: Addr Name PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Reset Values on all other Resets(1) Bank 1 80h INDF 81h OPTION_REG Addressing this location uses contents of FSR to address data memory (not a physical register) RAPU INTEDG T0CS T0SE PSA xxxx xxxx uuuu uuuu 1111 1111 1111 1111 PS<2:0> 82h PCL 83h STATUS Program Counter's (PC) Least Significant Byte 84h FSR 85h TRISA 86h — Un
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PIC12F752/HV752 TABLE 2-3: Adr PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 2 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Reset Value on all other Resets(1) Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h TMR0 Holding Register for the 8-bit Timer0 Register xxxx xxxx uuuu uuuu 102h PCL Program Counter's (PC) Least Significant Byte 103h STATUS IRP RP1 RP0 0000 0000
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PIC12F752/HV752 TABLE 2-4: Addr Name PIC12F752/HV752 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Value on POR/BOR Reset Bit 0 Values on all other Resets(1) Bank 3 180h INDF 181h OPTION_REG Addressing this location uses contents of FSR to address data memory (not a physical register) RAPU INTEDG T0CS T0SE PSA TO PD xxxx xxxx uuuu uuuu 1111 1111 1111 1111 PS<2:0> 182h PCL 183h STATUS Program Counter's (PC) Least Significant Byte 184h FSR
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PIC12F752/HV752 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (RAM) For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). The STATUS register can be the destination for any instruction, like any other register.
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PIC12F752/HV752 2.2.2.2 OPTION Register The OPTION register is a readable and writable register, which contains various control bits to configure: • • • • Note: Timer0/WDT prescaler External RA2/INT interrupt Timer0 Weak pull-ups on PORTA REGISTER 2-2: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit to ‘1’ of the OPTION register. See Section 6.1.3 “Software Programmable Prescaler”.
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PIC12F752/HV752 2.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, IOCIE change and external RA2/INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register.
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PIC12F752/HV752 2.2.2.4 PIE1 Register The PIE1 register contains the Peripheral Interrupt Enable bits, as shown in Register 2-4. REGISTER 2-4: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
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PIC12F752/HV752 2.2.2.5 PIE2 Register The PIE2 register contains the Peripheral Interrupt Enable bits, as shown in Register 2-5. REGISTER 2-5: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
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PIC12F752/HV752 2.2.2.6 PIR1 Register The PIR1 register contains the Peripheral Interrupt flag bits, as shown in Register 2-6. REGISTER 2-6: R/W-0 TMR1GIF Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
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PIC12F752/HV752 2.2.2.7 PIR2 Register The PIR2 register contains the Peripheral Interrupt flag bits, as shown in Register 2-7. REGISTER 2-7: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
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PIC12F752/HV752 2.2.2.8 PCON Register The Power Control (PCON) register (see Table 17-2) contains flag bits to differentiate between a: • • • • Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 2-8.
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PIC12F752/HV752 2.3 PCL and PCLATH 2.3.2 The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0>  PCH).
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PIC12F752/HV752 FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC12F752/HV752 Direct Addressing RP1 RP0 Bank Select 6 From Opcode Indirect Addressing 0 IRP 7 Bank Select Location Select 00 01 10 File Select Register 0 Location Select 11 00h 180h Data Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail, see Figure 2-2.  2011 Microchip Technology Inc.
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PIC12F752/HV752 NOTES: DS41576B-page 28 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 3.0 FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL 3.1 PMADRH and PMADRL Registers The PMADRH and PMADRL registers can address up to a maximum of 1K words of program memory. The Flash program memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (see Registers 3-1 to 3-5).
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PIC12F752/HV752 3.
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PIC12F752/HV752 REGISTER 3-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 — — — — — WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7-3 Unimplemented: Read as ‘0’ bit 2 WREN: Program/Erase Enable bit 1 = Allow
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PIC12F752/HV752 3.4 Reading the Flash Program Memory To read a program memory location, the user must write two bytes of the address to the PMADRL and PMADRH registers, and then set control bit RD (PMCON1<0>). Once the read control bit is set, the program memory Flash controller will use the second instruction cycle after to read the data. This causes the second instruction immediately following the “BSF PMCON1,RD” instruction to be ignored.
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PIC12F752/HV752 FIGURE 3-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Flash ADDR Q2 Q3 Q4 PC Flash DATA Q1 Q2 Q4 PC + 1 INSTR (PC) INSTR (PC - 1) Executed here Q3 Q1 Q2 Q3 Q4 Q1 PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD Executed here Q2 Q3 PC+3 PC +3 PMDATH,PMDATL INSTR (PC + 1) Executed here Q4 Q1 Q2 Q3 Q4 NOP Executed here Q2 Q3 Q4 PC + 5 PC + 4 INSTR (PC + 3) Q1 INSTR (PC + 4) INSTR (PC + 3) Executed here INSTR (PC + 4) Executed here RD bit PMDATH PMDATL
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PIC12F752/HV752 3.5 Writing the Flash Program Memory A word of the Flash program memory may only be written to if the word is in an unprotected segment of memory. Flash program memory must be written in four-word blocks. See Figure 3-2 and Figure 3-3 for more details. A block consists of four words with sequential addresses, with a lower boundary defined by an address, where PMADRL<1:0> = 00. All block writes to program memory are done as 16-word erase by fourword write operations.
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PIC12F752/HV752 FIGURE 3-2: BLOCK WRITES TO 1K FLASH PROGRAM MEMORY 7 5 0 0 7 PMDATH If at a new row sixteen words of Flash are erased, then four buffers are transferred to Flash automatically after this word is written PMDATL 6 8 14 14 First word of block to be written 14 PMADRL<1:0> = 00 PMADRL<1:0> = 10 PMADRL<1:0> = 01 Buffer Register Buffer Register 14 PMADRL<1:0> = 11 Buffer Register Buffer Register Program Memory FIGURE 3-3: FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION Q1 Q2
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PIC12F752/HV752 An example of the complete four-word write sequence is shown in Example 3-2. The initial address is loaded into the PMADRH and PMADRL register pair; the four words of data are loaded using indirect addressing.
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PIC12F752/HV752 TABLE 3-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — — — WREN WR RD 31 PMCON1 PMCON2 Program Memory Control Register 2 29* PMADRL PMADRL<7:0> 30 PMADRH — — — — PMDATL PMDATH — — INTCON GIE PEIE Legend: * CONFIG Legend: — PMADRH<1:0> 30 PMDATH<5:0> T0IE INTE 30 IOCIE 30 T0IF INTF IOCIF 20 — = unimplemented location, read as ‘0’.
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PIC12F752/HV752 NOTES: DS41576B-page 38 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 4.0 OSCILLATOR MODULE The internal oscillator module provides the following selectable system clock modes: 4.1 Overview • • • • The oscillator module has a variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 4-1 illustrates a block diagram of the oscillator module.
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PIC12F752/HV752 4.2 Clock Source Modes Clock Source modes can be classified as external or internal: • The External Clock mode relies on an external clock for the clock source. For example, a clock module or clock output from another circuit. • Internal clock sources are contained internally within the oscillator module.
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PIC12F752/HV752 4.3 System Clock Output 4.4 The CLKOUT pin is available for general purpose I/O or system clock output. The CLKOUTEN bit of the Configuration Word controls the function of the CLKOUT pin. When the CLKOUTEN bit is cleared, the CLKOUT pin is driven by the selected internal oscillator frequency divided by 4. The corresponding I/O pin always reads ‘0’ in this configuration.
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PIC12F752/HV752 4.
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PIC12F752/HV752 4.5.1 OSCTUNE REGISTER The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. The oscillator is factory calibrated, but can be adjusted in software by writing to the OSCTUNE register (Register 4-2). REGISTER 4-2: When the OSCTUNE register is modified, the frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.
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PIC12F752/HV752 NOTES: DS41576B-page 44 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 5.0 I/O PORTS EXAMPLE 5-1: For this device there is one port available, PORTA. In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. However, the pin can still be read. PORTA has three standard registers for its operation.
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PIC12F752/HV752 5.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 5-1. For this device family, the following functions can be moved between different pins. • Timer1 Gate • COG1 These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. 5.
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PIC12F752/HV752 5.3 PORTA and the TRISA Registers PORTA is a 6-bit wide port with 5 bidirectional and 1 input-only pin. The corresponding data direction register is TRISA (Register 5-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin).
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PIC12F752/HV752 5.
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PIC12F752/HV752 5.5 Additional Pin Functions 5.5.3 Every PORTA pin on the PIC12F752 has an interrupton-change option and a weak pull-up option. The next three sections describe these functions. 5.5.1 ANSELA REGISTER INTERRUPT-ON-CHANGE Each PORTA pin is individually configurable as an interrupt-on-change pin. Control bits IOCA enable or disable the interrupt function for each pin. Refer to Register 5-8. The interrupt-on-change is disabled on a Power-on Reset.
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PIC12F752/HV752 REGISTER 5-5: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 ANSA<5:4>: Analog Select Between Analog or Digital Function on Pin RA<5:4> bits 1 = Analog input.
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PIC12F752/HV752 REGISTER 5-7: SLRCONA: SLEW RATE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 — — — — — SLRA2 — SLRA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 SLRA2: Slew Rate Control bit 1 = Pin voltage slews at limited rate 0 = Pin voltage slews at maximum rate bit 1 Unimplemented: Read as ‘0’ bit 0 SLRA0: Slew Rate Contro
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PIC12F752/HV752 REGISTER 5-8: IOCAP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAP<5:0>: Interrupt-on-Change Pos
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PIC12F752/HV752 TABLE 5-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 ADCON0 ADFM VCFG ADCON1 — ANSELA — APFCON CM1CON0 Bit 5 Bit 4 Bit 2 ANSA5 ANSA4 Bit 1 Bit 0 Register on Page GO/DONE ADON 106 — — — — 107 — ANSA2 ANSA1 ANSA0 50 CHS<3:0> ADCS<2:0> — Bit 3 — — — T1GSEL — COG1FSEL COG1O1SEL COG1O0SEL 46 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 127 C2OE C2POL CM2CON0 C2ON C2OUT CM1CON1 C1INTP C1INTN C2ZLF C2SP C2HYS C2SYNC
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PIC12F752/HV752 NOTES: DS41576B-page 54 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 6.0 TIMER0 MODULE 6.1 Timer0 Operation The Timer0 module is an 8-bit timer/counter with the following features: When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. • • • • • 6.1.
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PIC12F752/HV752 6.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register.
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PIC12F752/HV752 6.
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PIC12F752/HV752 NOTES: DS41576B-page 58 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 7.0 TIMER1 MODULE WITH GATE CONTROL • • • • The Timer1 module is a 16-bit timer/counter with the following features: Figure 7-1 is a block diagram of the Timer1 module.
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PIC12F752/HV752 7.1 Timer1 Operation 7.2 Clock Source Selection The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. The TMR1CS<1:0> bits of the T1CON register are used to select the clock source for Timer1. Table 7-2 displays the clock source selections. When used with an internal clock source, the module is a timer and increments on every instruction cycle.
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PIC12F752/HV752 7.3 Timer1 Prescaler 7.5 Timer1 Gate Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 gate count enable.
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PIC12F752/HV752 7.5.2.1 T1G Pin Gate Operation 7.5.5 The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 7.5.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-tohigh pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 7.5.2.3 C1OUT/C2OUT Gate Operation The outputs from the Comparator C1 and C2 modules can be used as gate sources for the Timer1 module. 7.5.
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PIC12F752/HV752 7.6 Timer1 Interrupt 7.8 The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: 7.
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PIC12F752/HV752 FIGURE 7-3: TIMER1 GATE COUNT ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL TIMER1 N FIGURE 7-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL TIMER1 DS41576B-page 64 N N+1 N+2 N+3 N+4 Preliminary N+5 N+6 N+7 N+8  2011 Microchip Technology Inc.
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PIC12F752/HV752 FIGURE 7-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 TMR1GIF N N+1 Set by hardware on falling edge of T1GVAL Cleared by software  2011 Microchip Technology Inc.
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PIC12F752/HV752 FIGURE 7-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 TMR1GIF DS41576B-page 66 N Cleared by software N+1 N+2 N+3 Set by hardware on falling edge of T1GVAL Preliminary N+4 Cleared by software  2011 Microchip Technology Inc.
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PIC12F752/HV752 7.
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PIC12F752/HV752 REGISTER 7-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0 R/W-0 T1GSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0
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PIC12F752/HV752 TABLE 7-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 50 APFCON — — — T1GSEL — COG1SEL COG1O1SEL COG1O0SEL 46 CCP1CON — — GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF 20 PIE1 TMR1GIE ADIE — — — HLTMR1IE TMR2IE TMR1IE 21 PIR1 TMR1GIF ADIF — — — HLTMR1IF TMR2IF TMR1IF 23 — — RA5 RA4 RA3 RA2 RA1 RA0 INTCON PORTA DC1
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PIC12F752/HV752 NOTES: DS41576B-page 70 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 8.0 TIMER2 MODULE The Timer2 module is an 8-bit timer with the following features: • • • • • 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) See Figure 8-1 for a block diagram of Timer2. 8.1 Timer2 Operation The clock input to the Timer2 module is the system instruction clock (FOSC/4).
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PIC12F752/HV752 8.
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PIC12F752/HV752 9.0 HARDWARE LIMIT TIMER (HLT) MODULE The HLT module incorporates the following features: • 8-bit Read-Write Timer Register (HLTMR1) • 8-bit Read-Write Period register (HLTPR1) • Software programmable prescaler: - 1:1 - 1:4 - 1:16 • Software programmable postscaler - 1:1 to 1:16, inclusive • Interrupt on HLTMR1 match with HLTPR1 • 8 selectable timer Reset inputs (5 reserved) • Reset on rising and falling event The Hardware Limit Timer (HLT) module is a version of the Timer2-type modules.
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PIC12F752/HV752 9.1 HLT Operation 9.3 The clock input to the HLT module is the system instruction clock (FOSC/4). HLTMR1 increments on each rising clock edge. A 4-bit counter/prescaler on the clock input provides the following prescale options: • Direct input • Divide-by-4 • Divide-by-16 The prescale options are selected by the prescaler control bits, H1CKPS<1:0> of the HLT1CON0 register. The value of HLTMR1 is compared to that of the Period register, HLTPR1, on each clock cycle.
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PIC12F752/HV752 9.
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PIC12F752/HV752 REGISTER 9-2: HLT1CON1: HLT1 CONTROL REGISTER 1 U-0 U-0 U-0 — — — R/W-0/0 R/W-0/0 R/W-0/0 H1ERS<2:0> R/W-0/0 R/W-0/0 H1FEREN H1REREN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-2 H1ERS<2:0>: Hardware Limit Timer 1 Peripheral Reset Select bits 000 =
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PIC12F752/HV752 10.0 CAPTURE/COMPARE/PWM MODULES 10.1.2 The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. 10.
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PIC12F752/HV752 10.1.5 CAPTURE DURING SLEEP Capture mode depends upon the Timer1 module for proper operation. If the Timer1 clock input source is a clock that is not disabled during Sleep, Timer1 will continue to operate and Capture mode will operate during Sleep to wake the device. The T1CKI is an example of a clock source that will operate during Sleep. When the input source to Timer1 is disabled during Sleep, such as the HFINTOSC, Timer1 will not increment during Sleep.
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PIC12F752/HV752 10.2 Compare Mode 10.2.2 Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPR1H:CCPR1L register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair.
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PIC12F752/HV752 10.2.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep.
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PIC12F752/HV752 10.3 PWM Overview FIGURE 10-3: Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps.
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PIC12F752/HV752 10.3.2 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP1 module for standard PWM operation: 1. 2. 3. 4. 5. 6. Disable the CCP1 pin output driver by setting the associated TRIS bit. Load the PR2 register with the PWM period value. Configure the CCP1 module for the PWM mode by loading the CCP1CON register with the appropriate values. Load the CCPR1L register and the DC1B<1:0> bits of the CCP1CON register, with the PWM duty cycle value.
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PIC12F752/HV752 10.
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PIC12F752/HV752 NOTES: DS41576B-page 84 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 11.0 11.1 COMPLEMENTARY OUTPUT GENERATOR (COG) MODULE The primary purpose of the Complementary Output Generator (COG) is to convert a single output PWM signal into a two output complementary PWM signal. The COG can also convert two separate input events into a single or complementary PWM output. The COG PWM frequency and duty cycle are determined by a rising event input and a falling event input. The rising event and falling event may be the same source.
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SIMPLIFIED COG BLOCK DIAGRAM HFINTOSC 10 Fosc/4 Fosc 01 COG_clock 00 GxCS<1:0> HLTimer1 or COGxFLT HLTimer1 or CCP1 HLTimer1 or C2OUT HLTimer1 or C1OUT COGxFLT CCP1 C2OUT C1OUT 7 6 5 4 3 2 1 0 Preliminary HLTimer1 or COGxFLT HLTimer1 or CCP1 HLTimer1 or C2OUT HLTimer1 or C1OUT COGxFLT CCP1 C2OUT C1OUT Rising event source Phase Delay Blanking = Cnt/R 7 6 5 4 3 2 1 0 GxFS0<2:0>  2011 Microchip Technology Inc.
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PIC12F752/HV752 FIGURE 11-2: TYPICAL COG OPERATION WITH CCP1 COG_clock Source CCP1 COGxOUT0 Rising Source Dead Band Falling Source Dead Band Falling Source Dead Band COGxOUT1 FIGURE 11-3: COG OPERATION WITH CCP1 AND PHASE DELAY COG_clock Source CCP1 COGxOUT0 Rising Source Dead Band Falling Source Dead Band Phase Delay COGxOUT1  2011 Microchip Technology Inc.
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PIC12F752/HV752 11.2 Clock Sources FIGURE 11-4: The COG_clock is used as the reference clock to the various timers in the peripheral.
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PIC12F752/HV752 11.4 Output Control 11.5.1 RISING EVENT DEAD BAND Immediately after the COG module is enabled, the complementary drive is configured with COGxOUT0 drive cleared and COGxOUT1 drive active. Rising event dead-band delays the turn-on of COGxOUT0 from when COGxOUT1 is turned off. The rising event dead-band time starts when the rising event output goes true. 11.4.1 The rising event output into the dead-band counter may be delayed by the phase delay.
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PIC12F752/HV752 11.6 Blanking Control 11.7 Input blanking is a function whereby the event inputs can be masked or blanked for a short period of time. This is to prevent electrical transients caused by the turn-on/off of power components from generating a false input event. The COG contains two 4-bit blanking counters. The counters are cross coupled with the events they are blanking.
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PIC12F752/HV752 EXAMPLE 11-1: Given: TIMER UNCERTAINTY Count = Ah = 10d F COG_Clock = 8MHz Therefore: 1 T uncertainty = -------------------------F COG_clock 1 = --------------- = 125ns 8MHz Proof: Count T min = -------------------------FCOG_clock = 125ns  10d = 1.25s Count + 1 T max = -------------------------FCOG_clock = 125ns   10d + 1  = 1.375s Therefore: T uncertainty = T max – T min = 1.375s – 1.25s = 125ns  2011 Microchip Technology Inc.
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PIC12F752/HV752 11.8 Auto-shutdown Control 11.8.2 Auto-shutdown is a method to immediately override the COG output levels with specific overrides that allow for safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. 11.8.1 SHUTDOWN The shutdown state can be entered by either of the following two mechanisms: • Software generated • External Input 11.8.1.1 Note: The polarity control does not apply to the override level.
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FIGURE 11-5: 2 3 4 5 CCP1 GxARSEN Next rising event Shutdown input Next rising event Preliminary GxASDE Cleared in hardware Cleared in software GxASDL0 GxASDL1 COGxOUT1 Operating State NORMAL OUTPUT SHUTDOWN NORMAL OUTPUT SOFTWARE CONTROLLED RESTART SHUTDOWN NORMAL OUTPUT AUTO-RESTART DS41576B-page 93 PIC12F752/HV752 COGxOUT0 AUTO-SHUTDOWN WAVEFORM – CCP1 AS RISING AND FALLING EVENT INPUT SOURCE  2011 Microchip Technology Inc.
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PIC12F752/HV752 11.9 Buffer updates 11.12 Configuring the COG Changes to the phase, dead band, and blanking count registers need to occur simultaneously during COG operation to avoid unintended operation that may occur as a result of delays between each register write. This is accomplished with the GxLD bit of the COGxCON0 register and double buffering of the phase, blanking, and dead-band count registers.
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PIC12F752/HV752 11.
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PIC12F752/HV752 REGISTER 11-2: R/W-0/0 COGxCON1: COG CONTROL REGISTER 1 R/W-0/0 GxFSIM GxRSIM R/W-0/0 R/W-0/0 R/W-0/0 GxFS<2:0> R/W-0/0 R/W-0/0 R/W-0/0 GxRS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 GxFSIM: COGx Falling Source Input mode bit 1 = Input is edge sensit
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PIC12F752/HV752 REGISTER 11-3: COGxASD: COG AUTO-SHUTDOWN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 GxASDE GxARSEN GxASDL1 GxASDL0 GxASDSHLT GxASDSC2 GxASDSC1 GxASDSFLT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 GxASDE: Auto-Shu
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PIC12F752/HV752 REGISTER 11-4: R/W-x/u COGxDB: COG DEAD-BAND COUNT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u GxDBR<3:0> R/W-x/u R/W-x/u GxDBF<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-4 GxDBR<3:0>: Rising Event Dead-band Count Value bits = Number of COG clock p
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PIC12F752/HV752 TABLE 11-1: Name ANSELA SUMMARY OF REGISTERS ASSOCIATED WITH COG Bit 7 Bit 6 Bit 5 — — APFCON — — COG1PH — — Bit 2 Bit 1 Bit 0 Register on Page Bit 4 Bit 3 ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 50 — T1GSEL — COG1FSEL COG1O1SEL COG1O0SEL 46 — — G1PH<3:0> 98 COG1BLK G1BLKR<3:0> G1BLKF<3:0> 98 COG1DB G1DBR<3:0> G1DBF<3:0> G1EN G1OE1 COG1CON1 G1FSIM G1RSIM COG1ASD G1ASDE G1ARSEN G1ASDL1 G1ASDL0 G1ASDSHLT G1ASDSC2 G1ASDSC1 G1ASDSFLT 97 GIE PEIE
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PIC12F752/HV752 NOTES: DS41576B-page 100 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 12.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE Note: The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
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PIC12F752/HV752 12.1 ADC Configuration 12.1.3 When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting 12.1.1 12.1.2 CONVERSION CLOCK The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register.
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PIC12F752/HV752 TABLE 12-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V) ADC Clock Period (TAD) ADC Clock Source Device Frequency (FOSC) ADCS<2:0> 20 MHz 8 MHz (2) 2.0 s 1.0 s(2) 4.0 s 2.0 s 8.0 s(3) 2.0 s 4.0 s 16.0 s(3) 4.0 s 8.0 s(3) 32.0 s(3) FOSC/2 000 100 ns 100 200 ns(2) 500 ns(2) 001 400 ns (2) (2) 800 ns (2) FOSC/16 101 FOSC/32 010 500 ns 1.0 s (3) FOSC/64 110 3.
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PIC12F752/HV752 12.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 12-4 shows the two output formats. FIGURE 12-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH (ADFM = 0) ADRESL MSB LSB bit 7 bit 0 bit 7 10-bit A/D Result Unimplemented: Read as ‘0’ MSB (ADFM = 1) bit 7 LSB bit 0 Unimplemented: Read as ‘0’ 12.2 12.2.1 12.2.2 ADC Operation 12.2.
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PIC12F752/HV752 12.2.6 A/D CONVERSION PROCEDURE EXAMPLE 12-1: This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
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PIC12F752/HV752 12.
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PIC12F752/HV752 REGISTER 12-2: U-0 ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 — R/W-0/0 R/W-0/0 ADCS<2:0> U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (c
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PIC12F752/HV752 REGISTER 12-3: R-x ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 (READ-ONLY) R-x R-x R-x R-x R-x R-x R-x ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 12-4: R-x ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 (READ-ONLY) R-x ADRES<1:0> U-0 U-
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PIC12F752/HV752 12.4 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 12-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 12-4.
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PIC12F752/HV752 FIGURE 12-4: ANALOG INPUT MODEL VDD ANx Rs Cpin 5 pF VA Vt = 0.6V Vt = 0.
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PIC12F752/HV752 TABLE 12-2: Name SUMMARY OF ASSOCIATED ADC REGISTERS Bit 7 Bit 6 ADCON0 ADFM VCFG ADCON1 — ANSELA Bit 5 — — ANSA5 A/D Result Register High Byte ADRESL(2) A/D Result Register Low Byte INTCON Bit 3 Bit 2 CHS<3:0> ADCS<2:0> ADRESH(2) PORTA Bit 4 ANSA4 Bit 1 Bit 0 Register on Page GO/DONE ADON 106 — — — — 107 — ANSA2 ANSA1 ANSA0 50 108* 106* — — RA5 RA4 RA3 RA2 RA1 RA0 48 GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF 20 PIE1 TMR1GIE ADIE —
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PIC12F752/HV752 NOTES: DS41576B-page 112 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 13.0 FIXED VOLTAGE REFERENCE (FVR) 13.2 When the Fixed Voltage Reference module is enabled, it requires time for the reference circuit to stabilize. Once the circuit stabilizes and is ready for use, the FVRRDY bit of the FVRCON register will be set. See Section 20.0 “Electrical Specifications” for the minimum delay requirement. The Fixed Voltage Reference (FVR) is a stable voltage reference, independent of VDD, with 1.2V output level.
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PIC12F752/HV752 13.
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PIC12F752/HV752 14.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The 5-bit, dual range Digital-to-Analog Converter (DAC) module supplies a variable voltage reference, with 64 selectable output levels of which 3 levels are duplicated. The output is ratiometric with respect to the input source, VSRC+. See Figure 14-1 for a block diagram of the DAC module.
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PIC12F752/HV752 14.1 DAC Positive Voltage Source 14.3 The DACPSS bit of the DACCON0 register selects the positive voltage source, VSRC+. The following voltage sources are available: The DAC output value is derived using a resistor ladder with one end of the ladder tied to the positive voltage reference and the other end tied to VSS. If the voltage of the input source fluctuates, a similar fluctuation will result in the DAC output value.
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PIC12F752/HV752 FIGURE 14-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance 14.5 + – DACOUT DAC Voltage Reference Output Buffered DAC Output FIGURE 14-3: DAC/FVR OUTPUT PIN The DAC output (dac_ref) can be applied to the DACOUT pin as an unbuffered signal by: • Setting the DACOE bit of the DACCON0 register • Clearing the FVRBUFSS bit of the FVRCON register. • Clearing the FVRBUFEN bit of the FVRCON register.
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PIC12F752/HV752 14.
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PIC12F752/HV752 TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 DACCON0 DACEN DACRNG DACOE — — DACCON1 — — — FVREN FVRRDY FVRCON Legend: Bit 2 Bit 1 Bit 0 DACPSS — — DACR<4:0> FVRBUFEN FVRBUFSS — — Register on page 118 118 — — 114 — = unimplemented, read as ‘0’. Shaded cells are unused by the DAC module.  2011 Microchip Technology Inc.
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PIC12F752/HV752 NOTES: DS41576B-page 120 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 15.0 COMPARATOR MODULE FIGURE 15-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution.
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PIC12F752/HV752 FIGURE 15-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM CxNCH0 CxINTP Interrupt CxON(1) det Set CxIF CXIN0- 0 CXIN1- 1 MUX CxINTN Interrupt (2) det CXPOL CxVN 0 Cx CxVP dac_ref To Data Bus EN Q1 CXZLF CxHYS 1 MUX 2 fvr_ref CXOUT MCXOUT Q 1 + 0 CXIN+ ZLF D To COG Module CxSP (2) CXSYNC 3 CxON VSS 0 CXOE TRIS bit CXOUT CXPCH<1:0> D 2 Note 1: 2: (from Timer1) T1CLK Q 1 To Timer1 SYNCCXOUT When CxON = 0, the comparator will produce a ‘0’ at the out
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PIC12F752/HV752 15.2 Comparator Control 15.2.3 Each comparator has 2 control registers: CMxCON0 and CMxCON1. The CMxCON0 registers (see Register 15-1) contain Control and Status bits for the following: • • • • • • • Enable Output selection Output pin enable Output polarity Speed/Power selection Hysteresis enable Output synchronization Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs.
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PIC12F752/HV752 15.4.1 15.6 COMPARATOR OUTPUT SYNCHRONIZATION Comparator Positive Input Selection The output from either comparator, C1 or C2, can be synchronized with Timer1 by setting the CxSYNC bit of the CMxCON0 register. Configuring the CxPCH<1:0> bits of the CMxCON1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock.
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PIC12F752/HV752 15.10 Zero Latency Filter In high-speed operation, and under proper circuit conditions, it is possible for the comparator output to oscillate. This oscillation can have adverse effects on the hardware and software relying on this signal. Therefore, a digital filter has been added to the comparator output to suppress the comparator output oscillation. Once the comparator output changes, the output is prevented from reversing the change for a nominal time of 20 ns.
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PIC12F752/HV752 15.11 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 15-4. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur.
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PIC12F752/HV752 15.
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PIC12F752/HV752 REGISTER 15-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 CxPCH<1:0> U-0 U-0 U-0 R/W-0/0 — — — CxNCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bit 1 = The CxIF interrupt flag wil
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PIC12F752/HV752 TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 127 CM1CON1 C1INTP C1INTN CM2CON0 C2ON C2OUT CM2CON1 C2INTP C2INTN — — — DACCON0 DACEN DACRNG DACOE DACCON1 — — — FVRCON FVREN FVRRDY FVRBUFEN FVRBUFSS — INTCON Name CMOUT C1PCH<1:0> C2OE — — — C1NCH0 128 C2ZLF C2SP C2HYS C2SYNC 127 — — — C2NCH0
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PIC12F752/HV752 NOTES: DS41576B-page 130 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 16.0 INSTRUCTION SET SUMMARY The PIC12F752/HV752 instruction set is highly orthogonal and is comprised of three basic categories: TABLE 16-1: Field Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 16-1, while the various opcode fields are summarized in Table 16-1.
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PIC12F752/HV752 TABLE 16-2: PIC12F752/HV752 INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with
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PIC12F752/HV752 16.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0  k  255 Operation: (W) + k  (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. k BCF Bit Clear f Syntax: [ label ] BCF Operands: 0  f  127 0b7 Operation: 0  (f) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared.
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PIC12F752/HV752 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0  f  127 0b<7 Operands: None Operation: 00h  WDT 0  WDT prescaler, 1  TO 1  PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
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PIC12F752/HV752 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0  f  127 d  [0,1] Operands: 0  f  127 d  [0,1] Operation: (f) - 1  (destination); skip if result = 0 Operation: (f) + 1  (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
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PIC12F752/HV752 MOVWF Move W to f Syntax: [ label ] MOVF Move f Syntax: [ label ] Operands: 0  f  127 d  [0,1] Operands: 0  f  127 Operation: (W)  (f) Operation: (f)  (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register ‘f’ is moved to a destination dependent upon the status of ‘d’. If d = 0, destination is W register. If d = 1, the destination is file register ‘f’ itself.
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PIC12F752/HV752 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0  k  255 Operation: TOS  PC, 1  GIE Operation: k  (W); TOS  PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
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PIC12F752/HV752 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0  f  127 d  [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
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PIC12F752/HV752 SUBWF Subtract W from f XORWF Exclusive OR W with f Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORWF Operands: 0 f 127 d  [0,1] Operands: 0  f  127 d  [0,1] Operation: (f) - (W) destination) Operation: (W) .XOR. (f) destination) Status Affected: C, DC, Z Status Affected: Z Description: Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.
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PIC12F752/HV752 NOTES: DS41576B-page 140 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 17.0 SPECIAL FEATURES OF THE CPU The PIC12F752/HV752 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide powersaving features and offer code protection. These features are: 17.1 The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 17-1. These bits are mapped in program memory location 2007h.
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PIC12F752/HV752 REGISTER 17-1: CONFIGURATION WORD R/P-1 R/P-1 DEBUG CLKOUTEN R/P-1 R/P-1 R/P-1 WRT<1:0> R/P-1 BOREN<1:0> bit 13 bit 8 U-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 U-1 — CP MCLRE PWRTE WDTE — — bit 7 R/P-1 FOSC0 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 DEBUG: Debug Mode Enable bit(2) 1 = Background debugger is disabled 0 = Background debug
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PIC12F752/HV752 17.2 Calibration Bits The 8 MHz internal oscillator is factory calibrated. These calibration values are stored in fuses located in the Calibration Word (2008h). The Calibration Word is not erased when using the specified bulk erase sequence in the Memory Programming Specification (DS41561) and thus, does not require reprogramming. 17.
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PIC12F752/HV752 TABLE 17-1: TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration EC, INTOSC TABLE 17-2: Power-up Brown-out Reset PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 Wake-up from Sleep TPWRT — TPWRT — — STATUS/PCON BITS AND THEIR SIGNIFICANCE POR BOR TO PD Condition 0 x 1 1 Power-on Reset u 0 1 1 Brown-out Reset u u 0 u WDT Reset u u 0 0 WDT Wake-up u u u u MCLR Reset during normal operation u u 1 0 MCLR Reset during Sleep Legend: u = unchanged, x =
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PIC12F752/HV752 17.3.1 POWER-ON RESET (POR) FIGURE 17-2: The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 20.0 “Electrical Specifications” for details.
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PIC12F752/HV752 17.3.4 BROWN-OUT RESET (BOR) On any Reset (Power-on, Brown-out Reset, Watchdog timer, etc.), the chip will remain in Reset until VDD rises above VBOR (see Figure 17-3). If enabled, the Powerup Timer will be invoked by the Reset and keep the chip in Reset an additional 64 ms. The BOREN<1:0> bits in the Configuration Word register select one of three BOR modes. One mode has been added to allow control of the BOR enable for lower current during Sleep.
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PIC12F752/HV752 17.3.5 TIME-OUT SEQUENCE 17.3.6 On power-up, the time-out sequence is as follows: • PWRT time-out is invoked after POR has expired. • OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 17-4, Figure 17-5 and Figure 17-6 depict time-out sequences.
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PIC12F752/HV752 FIGURE 17-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) VDD MCLR Internal POR TPWRT PWRT Time-out TIOSCST OST Time-out Internal Reset DS41576B-page 148 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 TABLE 17-4: Register W INITIALIZATION CONDITION FOR REGISTERS Address Power-on Reset MCLR Reset WDT Reset Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h/ 100h/180h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h/ 102h/182h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h/ 103h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h/ 104h/184
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PIC12F752/HV752 TABLE 17-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out (Continued) Address Power-on Reset MCLR Reset WDT Reset (Continued) Brown-out Reset(1) CM2CON1 9Ch 0000 ---0 0000 ---0 uuuu ---u CM1CON0 9Dh 0000 0100 0000 0100 uuuu uuuu CM1CON1 9Eh 0000 ---0 0000 ---0 uuuu ---u CMOUT 9Fh ---- --00 ---- --00 ---- --uu LATA 105h --xx -xxx --uu -uuu --uu -uuu IOCAN 108h --00 0000 --00 0000
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PIC12F752/HV752 TABLE 17-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program Counter Status Register PCON Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during Sleep 000h 0001 0uuu ---- --uu 000h 0000 uuuu ---- --uu PC + 1 uuu0 0uuu ---- --uu Condition WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep 000h 0001 1uuu ---- --u0 PC + 1(1) uuu1 0uuu ---- --uu Legend: u = unchanged, x = u
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PIC12F752/HV752 17.4 Interrupts The PIC12F752/HV752 has multiple sources of interrupt: • • • • • • • • • • • External Interrupt (INT pin) Interrupt-On-Change (IOC) Interrupts Timer0 Overflow Interrupt Timer1 Overflow Interrupt Timer2 Match Interrupt Hardware Limit Timer (HLT) Interrupt Comparator Interrupt (C1/C2) ADC Interrupt Complementary Output Generator (COG) CCP1 Interrupt Flash Memory Self Write Figure 17-8). The latency is the same for one or twocycle instructions.
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PIC12F752/HV752 17.4.2 TIMER0 INTERRUPT An overflow (FFh  00h) in the TMR0 register will set the T0IF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing T0IE bit of the INTCON register. See Section 6.0 “Timer0 Module” for operation of the Timer0 module. 17.4.3 PORTA INTERRUPT-ON-CHANGE An input change on PORTA sets the IOCIF bit of the INTCON register. The interrupt can be enabled/ disabled by setting/clearing the IOCIE bit of the INTCON register.
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PIC12F752/HV752 FIGURE 17-8: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN CLKOUT (3) (4) INT pin (1) (1) INTF flag (INTCON reg.) Interrupt Latency (2) (5) GIE bit (INTCON reg.) INSTRUCTION FLOW PC Instruction Fetched PC + 1 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) — Dummy Cycle Inst (PC) Inst (PC – 1) 0004h PC + 1 Inst (PC + 1) Inst (PC) Instruction Executed Note 1: PC INTF flag is sampled here (every Q1).
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PIC12F752/HV752 17.5 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Temporary holding registers W_TEMP and STATUS_TEMP should be placed in the last 16 bytes of GPR (see Figure 2-2). These 16 locations are common to all banks and do not require banking. This makes context save and restore operations simpler.
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PIC12F752/HV752 17.6.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken in account that under worstcase conditions (i.e., VDD = Min., Temperature = Max., Max. WDT prescaler) it may take several seconds before a WDT time-out occurs.
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PIC12F752/HV752 TABLE 17-8: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 OPTION_REG RAPU INTEDG T0CS T0SE PSA Bit 2 Bit 1 Bit 0 Register on Page PS<2:0> 57 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 17-1 for operation of all Configuration Word register bits.
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PIC12F752/HV752 17.7 Power-Down Mode (Sleep) The Power-Down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • • • • • WDT will be cleared but keeps running. PD bit in the STATUS register is cleared. TO bit is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance).
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PIC12F752/HV752 FIGURE 17-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN TIOSCST CLKOUT INT pin INTF flag (INTCON reg.) Interrupt Latency (3) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 17.
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PIC12F752/HV752 17.10 In-Circuit Serial Programming™ ThePIC12F752/HV752 microcontrollers can be serially programmed while in the end application circuit. This is simply done with five connections for: • • • • • clock data power ground programming voltage This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
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PIC12F752/HV752 18.0 SHUNT REGULATOR (PIC12HV752 ONLY) The PIC12HV752 devices include a permanent internal 5 volt (nominal) shunt regulator in parallel with the VDD pin. This eliminates the need for an external voltage regulator in systems sourced by an unregulated supply. All external devices connected directly to the VDD pin will share the regulated supply voltage and contribute to the total VDD supply current (ILOAD). 18.
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PIC12F752/HV752 NOTES: DS41576B-page 162 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 19.0 DEVELOPMENT SUPPORT 19.
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PIC12F752/HV752 19.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 19.
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PIC12F752/HV752 19.7 MPLAB SIM Software Simulator 19.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
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PIC12F752/HV752 19.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 19.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
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PIC12F752/HV752 20.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40° to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ............................................................................................
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PIC12F752/HV752 FIGURE 20-1: PIC12F752 VOLTAGE-FREQUENCY GRAPH, -40°C  TA  +125°C 5.5 5.0 VDD (V) 4.5 4.0 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 20-2: PIC12HV752 VOLTAGE-FREQUENCY GRAPH, -40°C  TA  +125°C 5.0 VDD (V) 4.5 4.0 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
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PIC12F752/HV752 20.1 DC Characteristics: PIC12F752/HV752-I (Industrial) PIC12F752/HV752-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param No. Min Typ† Max Units 2.0 — 5.5 V V FOSC < = 4 MHz V FOSC < = 8 MHz Sym Characteristic Conditions Supply Voltage D001 VDD PIC12F752 FOSC < = 4 MHz D001 PIC12HV752 2.0 — 5.0(2) D001B VDD PIC12F752 2.0 — 5.
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PIC12F752/HV752 20.2 DC Characteristics: PIC12F752-I (Industrial) PIC12F752-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended DC CHARACTERISTICS Param No. D010 Device Characteristics Supply Current (IDD) PIC12F752 D011* D012* D013* D014 D015 D016 (1, 2) Min Typ† Max Units Conditions VDD — 8 TBD A 2.0 — 16 TBD A 3.0 — 31 TBD A 5.0 — 140 TBD A 2.
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PIC12F752/HV752 20.3 DC Characteristics: PIC12HV752-I (Industrial) PIC12HV752-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended DC CHARACTERISTICS Param No. D010 Device Characteristics Supply Current (IDD) PIC12HV752 D011* D012* (1, 2) Conditions Min Typ† Max Units — 20 TBD A 2.0 — 40 TBD A 3.0 VDD — 65 TBD A 4.5 — 215 TBD A 2.0 — 375 TBD A 3.
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PIC12F752/HV752 20.4 DC Characteristics: PIC12F752 - I (Industrial) DC CHARACTERISTICS Param No. D020 Device Characteristics Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial Conditions Min Typ† Max Units Power-down Base Current (IPD)(2) — 0.01 TBD A 2.0 — 0.3 TBD A 3.0 PIC12F752 — 0.5 TBD A 5.0 150 TBD nA 3.0 -40°C  TA  +25°C for industrial — 3.0 TBD A 2.0 WDT Current(1) — 4.0 TBD A 3.
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PIC12F752/HV752 20.5 DC Characteristics: PIC12F752 - E (Extended) DC CHARACTERISTICS Param No. D020E Device Characteristics Power-down Base Current (IPD)(2) PIC12F752 D021E D022E D023E D024E D025E D026E D027E Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended Min Typ† Max Units Conditions VDD Note WDT, BOR, Comparator, DAC and FVR disabled — 0.1 TBD A 2.0 — 0.3 TBD A 3.0 — 0.5 TBD A 5.0 — 3.0 TBD A 2.0 — 4.
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PIC12F752/HV752 20.6 DC Characteristics: PIC12HV752 - I (Industrial) DC CHARACTERISTICS Param No. D020 Device Characteristics Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial Min Typ† Max Units Conditions — 135 TBD A 2.0 — 210 TBD A 3.0 PIC12HV752 — 260 TBD A 4.5 — 135 TBD A 2.
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PIC12F752/HV752 20.7 DC Characteristics: PIC12HV752-E (Extended) DC CHARACTERISTICS Param No. D020E Device Characteristics Power-down Base Current (IPD)(2,3) PIC12HV752 D021E Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended Min Typ† Max Units — 135 TBD A Conditions VDD 2.0 — 210 TBD A 3.0 — 260 TBD A 4.5 — 135 TBD A 2.0 — 210 TBD A 3.0 — 265 TBD A 4.5 D022E — 215 TBD A 3.0 — 265 TBD A 4.
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PIC12F752/HV752 20.8 DC Characteristics: PIC12F752/HV752-I (Industrial) PIC12F752/HV752-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ† Max Units Vss Vss Conditions — 0.8 V 4.5V  VDD  5.5V — 0.15 VDD V 2.0V  VDD  4.5V Vss — 0.2 VDD V 2.0V  VDD  5.5V 2.0 — VDD V 4.5V  VDD 5.
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PIC12F752/HV752 20.8 DC Characteristics: PIC12F752/HV752-I (Industrial) PIC12F752/HV752-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended DC CHARACTERISTICS Param No.
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PIC12F752/HV752 20.9 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. Sym Characteristic Typ Units 84.6* 149.5* 60* 41.2* 39.
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PIC12F752/HV752 20.10 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
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PIC12F752/HV752 20.11 AC Characteristics: PIC12F752/HV752 (Industrial, Extended) FIGURE 20-4: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS02 OS04 OS04 OS03 CLKOUT CLKOUT (CLKOUT Mode) TABLE 20-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No.
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PIC12F752/HV752 TABLE 20-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym Characteristic OS06 TWARM Internal Oscillator Switch when running(3) OS07 INTOSC Internal Calibrated INTOSC Frequency(2) (4 MHz) OS08 INTOSC OS10* Internal Calibrated INTOSC Frequency(2) (8 MHz) TIOSC ST INTOSC Oscillator Wakeup from Sleep Start-up Time Legend: * † Note 1: 2: 3: Freq.
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PIC12F752/HV752 FIGURE 20-5: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS20 CLKOUT OS21 OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 20-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No.
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PIC12F752/HV752 FIGURE 20-6: RESET, WATCHDOG TIMER, AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: FIGURE 20-7: Asserted low. BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR + VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset (due to BOR) * 33* 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.
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PIC12F752/HV752 TABLE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No.
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PIC12F752/HV752 FIGURE 20-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 20-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No.
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PIC12F752/HV752 FIGURE 20-9: PIC12F752/HV752 CAPTURE/COMPARE/PWM TIMINGS (CCP) CCP1 (Capture mode) CC01 CC02 CC03 Note: TABLE 20-6: Refer to Figure 20-3 for load conditions. PIC12F752/HV752 CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. CC01* CC02* CC03* Sym TccL TccH TccP Characteristic CCP1 Input Low Time CCP1 Input High Time Min Typ† Max Units No Prescaler 0.
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PIC12F752/HV752 TABLE 20-8: DIGITAL-TO-ANALOG (DAC) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. Sym Characteristics Min Typ† Max Units — V DA01* CLSB Step Size — VDD/32 DA02* CACC Absolute Accuracy —  1/2 — LSB DA03* CR Unit Resistor Value (R) — TBD —  DA04* CST Settling Time — 10 — s Comments Legend: TBD = To Be Determined * These parameters are characterized but not tested.
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PIC12F752/HV752 TABLE 20-11: PIC12F752/HV752 A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym No. Characteristic Min Typ† Max Units Conditions AD01 NR Resolution — — 10 bits AD02 EIL Integral Error — — 1 LSb VREF = 5.12V(5) AD03 EDL Differential Error — — 1 LSb No missing codes to 10 bits VREF = 5.12V(5) AD04 EOFF Offset Error — +1.5 +2.0 LSb VREF = 5.
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PIC12F752/HV752 TABLE 20-12: PIC12F752/HV752 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. Sym Characteristic Min Typ† 1.6 — 9.0 s TOSC-based, VREF 3.0V 3.0 — 9.0 s TOSC-based, VREF full range(3) 3.0 6.0 9.0 s ADCS<2:0> = 11 At VDD = 2.5V 1.6 4.0 6.0 s At VDD = 5.
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PIC12F752/HV752 FIGURE 20-11: PIC12F752/HV752 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY) 1 TCY AD131 Q4 AD130 A/D CLK 9 A/D Data 7 8 6 OLD_DATA ADRES 3 2 1 0 NEW_DATA ADIF 1 TCY GO DONE Sample AD132 DS41576B-page 190 Sampling Stopped Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 21.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time.  2011 Microchip Technology Inc.
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PIC12F752/HV752 NOTES: DS41576B-page 192 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 22.0 PACKAGING INFORMATION 22.1 Package Marking Information 8-Lead PDIP (300 mil) Example XXXXXXXX XXXXXNNN 12F752 E/P e3 121 YYWW 1109 8-Lead SOIC (3.90 mm) Example 12F752 ESN1109 121 NNN Legend: XX...
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PIC12F752/HV752 22.2 Package Marking Information 8-Lead DFN (3x3x0.9 mm) Example XXXX YYWW NNN MFU0 1109 121 PIN 1 TABLE 22-1: PIN 1 8-LEAD 3X3 DFN (MF) TOP MARKING Part Number PIC12F752-E/MF MFU0 PIC12F752-I/MF MFV0 PIC12HV752-E/MF MFW0 PIC12HV752-I/MF MFX0 Legend: XX...
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PIC12F752/HV752 22.3 Package Details The following sections give the technical details of the packages. 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6 &! ' ! 9 ' &! 7"') % ! 7,8.
PAGE 196
PIC12F752/HV752 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41576B-page 196 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc.
PAGE 198
PIC12F752/HV752 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41576B-page 198 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 ! " # $ % % &' 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4  2011 Microchip Technology Inc.
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PIC12F752/HV752 NOTES: DS41576B-page 200 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 APPENDIX A: DATA SHEET REVISION HISTORY APPENDIX B: MIGRATING FROM PIC12HV615 This compares the features of the PIC12HV615 to the PIC12HV752 family of devices. Revision A Original release (4/2011). B.1 Revision B PIC12HV615 to PIC12HV752 TABLE B-1: Redefined operation of the COG module; Added slew rate control to the COG module; Added zero latency filter to the comparator; Updated Electrical Specifications.
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PIC12F752/HV752 NOTES: DS41576B-page 202 Preliminary  2011 Microchip Technology Inc.
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PIC12F752/HV752 INDEX A A/D Specifications.................................................... 188, 189 Absolute Maximum Ratings .............................................. 167 AC Characteristics Industrial and Extended ............................................ 180 Load Conditions ........................................................ 179 ADC .................................................................................. 101 Acquisition Requirements .........................................
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PIC12F752/HV752 Configuration Bits.............................................................. 141 CPU Features ................................................................... 141 Customer Change Notification Service ............................. 207 Customer Notification Service........................................... 207 Customer Support ............................................................. 207 D DACCON0 (Digital-to-Analog Converter Control 0) Register....................................
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PIC12F752/HV752 O R OPCODE Field Descriptions ............................................. 131 Operation During Code Protect........................................... 34 Operation During Write Protect ........................................... 34 Operational Amplifier (OPA) Module AC Specifications...................................................... 187 OPTION Register ................................................................ 19 OPTION_REG Register .............................................
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PIC12F752/HV752 Slew Rate Control ............................................................... 49 Software Simulator (MPLAB SIM)..................................... 165 Special Event Trigger........................................................ 104 Special Function Registers ................................................. 12 STATUS Register................................................................ 18 T T1CON Register..................................................................
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PIC12F752/HV752 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC12F752/HV752 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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PIC12F752/HV752 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO.
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Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.