Datasheet

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SBFS026B − JUNE 2004 − REVISED SEPTEMBER 2007
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26
DIGITAL DE-EMPHASIS FILTER
The SRC4184 includes digital de-emphasis filtering
following the input serial ports. The de-emphasis filter
processes audio data that has been pre-emphasized
using the 50/15µs transfer function, commonly used in
consumer and professional audio systems. Pre-emphasis
is utilized to increase the amplitude of the higher frequency
components within the audio band. The de-emphasis filter
normalizes the frequency response over the audio band.
The SRC4184 supports three sampling frequencies for the
de-emphasis filter: 32kHz, 44.1kHz, and 48kHz. The
de-emphasis filter can also be disabled. Table 6 shows the
configuration table for the de-emphasis filter options.
Table 6. Digital De-Emphasis Filter Configuration
(x = A or B)
DEMx1 DEMx0 DE-EMPHASIS FILTER FUNCTION
0 0 Disabled
0 1 48kHz Input Sample Rate
1 0 44.1kHz Input Sample Rate
1 1 32kHz Input Sample Rate
In Hardware mode, the DEMA0 (pin 12) and DEMA1
(pin 13) inputs are used to select the de-emphasis filter for
SRC A, while DEMB0 (pin 37) and DEMB1 (pin 36) inputs
are used for SRC B.
In Software mode, the DEM[1:0] bits in Control Register 2
are used to select the de-emphasis filter in both the SRC A
and SRC B register banks. De-emphasis filtering is
disabled by default in Software mode.
SOFT MUTE FUNCTION
The soft mute function of the SRC4184 may be invoked by
forcing the MUTEA (pin 19) or MUTEB (pin 30) inputs high.
In Software mode, the mute function may also be
accessed using the MUTE bit in Control Register 1 for
either the SRC A and SRC B register banks. The soft mute
function slowly attenuates the output signal level down to
an all zeros output. For normal output, the soft mute
function should be disabled by forcing the control pin or bit
low. The soft mute function is disabled by default in
Software mode.
DIGITAL ATTENUATION
(Software Mode Only)
The SRC4184 includes independent digital attenuation for
the Left and Right audio channels in Software mode. The
attenuation ranges from 0dB (unity gain) to −127.5dB in
0.5dB steps. The attenuation settings are programmed
using Control Register 4 and Control Register 5 for either
the SRC A and SRC B register banks. The attenuation
setting is programmed to 0dB (unity gain) by default.
The TRACK bit in Control Register 1 is used to select
Independent or Tracking attenuation modes. When
TRACK = 0, the Left and Right channels are controlled
independently. When TRACK = 1, the attenuation setting
for the Left channel is also used for the Right channel,
providing a tracking function. The digital attenuation mode
is set to Independent by default.
READY OUTPUT
The SRC4184 includes active low ready outputs for both
SRC A and SRC B. The outputs are designated RDYA
(pin 18) and RDYB (pin 31). The ready output is provided
from the rate estimator block, with a low output state
indicating that the input-to-output sampling frequency ratio
has been determined and that the coefficients and address
pointers for the re-sampling block have been updated. The
ready signal may be used as a flag output for an external
indicator or host.
RATIO OUTPUT
The SRC4184 includes a sampling ratio flag output for
both SRC A and SRC B. The outputs are designated
RATIOA (pin 17) and RATIOB (pin 32). When the ratio
output is low, it indicates that the output sampling
frequency is lower than the input sampling frequency.
When ratio output is high, it indicates that the output
sampling frequency is higher than the input sampling
frequency. The ratio output can be used as a flag output for
either an external indicator or host.
SAMPLING RATIO READBACK
(Software Mode Only)
In Software mode, Control Registers 6 and 7 in either the
SRC A and SRC B register banks function as status
registers, which contain the integer and fractional part of
the input-to-output sampling ratio, or f
sIN
:f
sOUT
. Given that
f
sOUT
or f
sIN
is known, the unknown sampling rate can be
computed using the contents of Registers 6 and 7. This
function may be useful for controlling end application
display or control processes. Refer to the Control Register
Definition section of this datasheet for additional
information regarding Registers 6 and 7.
SERIAL PERIPHERAL INTERFACE (SPI)
PORT
(Software Mode Only)
The SPI port is a four-wire synchronous serial interface
used to access the on-chip control registers of the
SRC4184. The interface is comprised of a serial data clock
input, CCLK (pin 34); a serial data input, CDIN (pin 33); a
serial data output, CDOUT (pin 36); and an active low
chip-select input, CS
(pin 35). The CDOUT pin is a tri-state
output and is forced to a high impedance state when the
CS
input is forced high.