Datasheet

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SBFS026B − JUNE 2004 − REVISED SEPTEMBER 2007
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The left/right word clock, LRCKOA (pin 62) and LRCKOB
(pin 51), may be configured as an input or output pin. In
Slave mode, the left/right clock is an input pin, while in
Master mode it is an output pin. In either case, the clock
rate is equal to f
s
, the output sampling frequency. The clock
duty cycle is fixed to 50% for I
2
S, Left-Justified, and
Right-Justified formats in Master mode. The pulse width is
fixed to 32-bit clock cycles for the TDM format in Master
mode.
Table 3 illustrates data format selection for the output port.
In Hardware mode, the OFMTA0 (pin 4), OFMTA1 (pin 5),
OWLA0 (pin 6), and OWLA1 (pin 7) inputs are utilized to
set the output port data format and word length for SRC A.
The OFMTB0 (pin 45), OFMTB1 (pin 44), OWLB0 (pin 43),
and OWLB1 (pin 42) inputs are utilized to set the output
port data format and word length for SRC B.
Table 3. Output Port Data Format/Word Length
Selection (x = A or B)
OFMTx1 OFMTx0 OUTPUT PORT DATA FORMAT
0 0 Left-Justified
0 1 I
2
S
1 0 TDM
1 1 Right-Justified
OWLx1 OWLx0 OUTPUT PORT DATA WORD LENGTH
0 0 24 Bits
0 1 20 Bits
1 0 18 Bits
1 1 16 Bits
In Software mode, the OFMT[1:0] and OWL[1:0] bits in
Control Register 3 are used to select the data format and
word length for the SRC A and SRC B register banks. The
default format is Left-Justified data with a default word
length of 24-bits.
BYPASS MODE
The SRC4184 includes a bypass function for both SRC A
and SRC B, which routes the input port data directly to the
output port, bypassing the sample rate conversion block.
Bypass mode may be invoked by forcing BYPA (pin 8) or
BYPB (pin 41) high in either Hardware or Software mode.
In Software mode, the bypass function may also be
accessed using the BYPASS bit in Control Register 1 for
the SRC A and SRC B register banks. For normal SRC
operation, the bypass pins and control bits should be set
to 0.
No dithering is applied to the output data in Bypass mode,
and the digital attenuation, de-emphasis, and soft mute
functions are also unavailable. Bypass mode is useful for
passing through compressed or encoded audio data, as
well as non-audio data (that is, control or status
information).
INTERPOLATION FILTER GROUP DELAY
OPTIONS
The SRC4184 provides four group delay options for the
digital interpolation filter, as shown in Table 4. These
options allow the user to tailor the group delay for a given
application by selecting the number of input samples
buffered prior to the re-sampling function.
Table 4. Low Group Delay Configuration
(x = A or B)
LGRPx1 LGRPx0 BUFFER SIZE
0 0 64 Samples
0 1 32 Samples
1 0 16 Samples
1 1 8 Samples
In Hardware mode, the LGRPA0 (pin 9) and LGRPA1
(pin 10) inputs are used to select the group delay for
SRC A, while LGRPB0 (pin 40) and LGRPB1 (pin 39)
inputs are used for SRC B.
In Software mode, the LGRP[1:0] bits in Control Register 2
are used for the SRC A and SRC B register banks. The 64
sample buffer option is selected by default in Software
mode.
DIRECT DOWNSAMPLING OPTION
The SRC4184 decimation function allows the selection of
a direct downsampling option, as shown in Table 5. Unlike
the decimation filter, the direct downsampler does not
provide anti-alias filtering. This makes the direct
downsampler suitable for applications where the output
sample rate is higher than the input sample rate. The
advantage of the direct downsampler is that there is no
group delay associated with the decimation function.
Table 5. Decimation Function Configuration
(x = A or B)
DDNx DECIMATION FUNCTION
0 Decimation Filter Enabled
1 Direct Downsampler Enabled
In Hardware mode, the DDNA (pin 11) input is used to
select the direct downsampler for SRC A, while the DDNB
(pin 38) input is used for SRC B.
In Software mode, the DDN bit in Control Register 2 is
used to select the direct downsampler for the SRC A and
SRC B register banks. The decimation filter is selected by
default, with direct downsampling disabled.