MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • 23 • • • • • • • Low Supply-Voltage Range, 1.8 V to 3.6 V Ultra-Low Power Consumption – Active Mode: 270 µA at 1 MHz, 2.2 V – Standby Mode (VLO): 0.3 µA – Off Mode (RAM Retention): 0.1 µA Ultra-Fast Wake-Up From Standby Mode in Less Than 1 µs 16-Bit RISC Architecture, 62.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK Device Pinout, MSP430F23x PM OR RGC PACKAGE (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 2 47 3 46 4 5 45 6 43 7 42 44 8 41 MSP430F23x 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P5.4/MCLK P5.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 AVCC DVSS AVSS P6.2 P6.1 P6.0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK Device Pinout, MSP430F24x1 PM OR RGC PACKAGE (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 2 47 3 46 4 5 45 6 43 7 42 44 8 41 MSP430F24x1 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P5.4/MCLK P5.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Functional Block Diagram, MSP430F23x XIN/ XT2IN XOUT/ XT2OUT 2 DVCC DVSS AVCC AVSS 2 P1.x/P2.x P3.x/P4.x P5.x/P6.x 2x8 4x8 ACLK Oscillators Basic Clock SMCLK System+ Flash RAM 16kB 8kB 2kB 1kB MCLK 16MHz CPU incl.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Functional Block Diagram, MSP430F24x, MSP430F2410 XIN/ XT2IN XOUT/ XT2OUT 2 DVCC DVSS AVCC AVSS 2 P1.x/P2.x P3.x/P4.x P5.x/P6.x 2x8 4x8 ACLK Oscillators Basic Clock SMCLK System+ MCLK 16MHz CPU incl.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Functional Block Diagram, MSP430F24x1 XIN/ XT2IN XOUT/ XT2OUT 2 DVCC DVSS AVCC AVSS 2 P1.x/P2.x P3.x/P4.x P5.x/P6.x 2x8 4x8 ACLK Oscillators Basic Clock SMCLK System+ MCLK 16MHz CPU incl.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Table 2. Terminal Functions, MSP430F23x TERMINAL NAME NO. I/O DESCRIPTION AVCC 64 Analog supply voltage, positive. Supplies only the analog portion of ADC12. AVSS 62 Analog supply voltage, negative. Supplies only the analog portion of ADC12. DVCC 1 Digital supply voltage, positive. Supplies all digital parts. DVSS 63 P1.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Table 2. Terminal Functions, MSP430F23x (continued) TERMINAL NAME NO. I/O DESCRIPTION P6.3/A3 2 I/O General-purpose digital I/O / analog input A3 - 12-bit ADC P6.4/A4 3 I/O General-purpose digital I/O / analog input A4 - 12-bit ADC P6.5/A5 4 I/O General-purpose digital I/O / analog input A5 - 12-bit ADC P6.6/A6 5 I/O General-purpose digital I/O / analog input A6 - 12-bit ADC P6.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Table 3. Terminal Functions, MSP430F24x, MSP430F2410 TERMINAL NAME NO. I/O DESCRIPTION AVCC 64 Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12. AVSS 62 Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12. DVCC 1 Digital supply voltage, positive terminal. Supplies all digital parts. DVSS 63 P1.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Table 3. Terminal Functions, MSP430F24x, MSP430F2410 (continued) TERMINAL NAME NO. I/O DESCRIPTION P6.1/A1 60 I/O General-purpose digital I/O / analog input A1 - 12-bit ADC P6.2/A2 61 I/O General-purpose digital I/O / analog input A2 - 12-bit ADC P6.3/A3 2 I/O General-purpose digital I/O / analog input A3 - 12-bit ADC P6.4/A4 3 I/O General-purpose digital I/O / analog input A4 - 12-bit ADC P6.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Table 4. Terminal Functions, MSP430F24x1 TERMINAL NAME NO. I/O DESCRIPTION AVCC 64 Analog supply voltage, positive. Supplies only the analog portion of ADC12. AVSS 62 Analog supply voltage, negative. Supplies only the analog portion of ADC12. DVCC 1 Digital supply voltage, positive. Supplies all digital parts. DVSS 63 P1.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Table 4. Terminal Functions, MSP430F24x1 (continued) TERMINAL NAME NO. I/O DESCRIPTION P6.1 60 I/O General-purpose digital I/O P6.2 61 I/O General-purpose digital I/O P6.3 2 I/O General-purpose digital I/O P6.4 3 I/O General-purpose digital I/O P6.5 4 I/O General-purpose digital I/O P6.6 5 I/O General-purpose digital I/O P6.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Operating Modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: • Active mode (AM) – All clocks are active.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset vector (0xFFFE) contains 0xFFFF (for example, if flash is not programmed) the CPU enters LPM4 after powerup. Table 7.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Special Function Registers Most interrupt enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access. Legend rw rw-0, 1 rw-(0), (1) Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Memory Organization Table 12.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 • • • 20 www.ti.com 64 bytes each. Each segment in main memory is 512 bytes in size. Segments 0 to n may be erased in one step, or each segment may be individually erased. Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. Segment A contains calibration data. After reset, segment A is protected against programming and erasing.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Digital I/O There are up to six 8-bit I/O ports implemented—ports P1 through P6: • All individual I/O bits are independently programmable. • Any combination of input, output, and interrupt condition is possible. • Edge-selectable interrupt input capability for all eight bits of port P1 and P2. • Read/write access to port-control registers is supported by all instructions.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Timer_B7 (MSP430F24x(1) and MSP430F2410 Devices) Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 17.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Timer_B3 (MSP430F23x Devices) Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 18.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Peripheral File Map Table 19.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Table 19.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Table 19.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Table 19.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Table 19.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Absolute Maximum Ratings (1) Voltage applied at VCC to VSS Voltage applied to any pin -0.3 V to 4.1 V (2) -0.3 V to VCC + 0.3 V Diode current at any device terminal Storage temperature, Tstg (1) ±2 mA (3) Unprogrammed device -55°C to 150°C Programmed device -55°C to 150°C Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Typical Characteristics - Active-Mode Supply Current (Into DVCC and AVCC ) ACTIVE-MODE CURRENT vs SUPPLY VOLTAGE TA = 25°C ACTIVE-MODE CURRENT vs DCO FREQUENCY 5.0 8.0 f DCO = 16 MHz 7.0 TA = 85 °C Active Mode Current − mA Active Mode Current − mA 4.0 6.0 f DCO = 12 MHz 5.0 f DCO = 8 MHz 4.0 3.0 2.0 TA = 25 °C 3.0 VCC = 3 V 2.0 TA = 85 °C TA = 25 °C 1.0 0.0 1.5 2.0 2.5 3.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Typical Characteristics - LPM4 Current LPM4 CURRENT vs TEMPERATURE ILPM4 − Low−power mode current − µA 10.0 9.0 8.0 7.0 6.0 5.0 VCC = 3.6 V 4.0 VCC = 3 V 3.0 Vcc = 2.2V 2.0 1.0 0.0 −40.0 −20.0 0.0 Vcc = 1.8 V 20.0 40.0 60.0 80.0 100.0 120.0 TA − Temperature − °C Figure 4.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Outputs (Ports P1, P2, P3, P4, P5, P6) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS IOH(max) = -1.5 mA VOH High-level output voltage IOH(max) = -6 mA VCC (1) 2.2 V (2) IOH(max) = -1.5 mA (1) 3V IOH(max) = -6 mA (2) IOL(max) = 1.5 mA VOL Low-level output voltage (2) MAX VCC - 0.25 VCC VCC - 0.6 VCC VCC - 0.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Typical Characteristics - Outputs One output loaded at a time. TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50.0 VCC = 2.2 V P4.5 TA = 25°C 20.0 I OL − Typical Low-Level Output Current − mA I OL − Typical Low-Level Output Current − mA 25.0 TA = 85°C 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 VCC = 3 V P4.5 40.0 TA = 85°C 30.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com POR and Brownout Reset (BOR) (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(start) Operating voltage dVCC /dt ≤ 3 V/s 0.7 × V(B_IT-) V(B_IT-) Negative going VCC reset threshold voltage dVCC /dt ≤ 3 V/s 1.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Typical Characteristics - POR/Brownout Reset (BOR) VCC 3V 2 VCC(drop) − V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns t pw − Pulse Width − µs 1 ns t pw − Pulse Width − µs Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Software sets VLD >0: SVS is active AVCC V(SVS_IT−) V(SVSstart) Vhys(SVS_IT−) Vhys(B_IT−) V(B_IT−) VCC(start) Brownout Region Brownout Region Brownout 1 0 SVS out t d(BOR) t d(BOR) SVS Circuit is Active From VLD > to V CC < V( B_IT−) 1 0 td(SVSon) Set POR 1 td(SVSR) undefined 0 Figure 12. SVS Reset (SVSR) vs Supply Voltage VCC 3V t pw 2 Rectangular Drop VCC(min) VCC(min) − V 1.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Main DCO Characteristics • • • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO . Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Calibrated DCO Frequencies - Tolerance at Calibration over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Frequency tolerance at calibration TA VCC MIN TYP MAX UNIT 25°C 3V -1 ±0.2 +1 % 25°C 3V 0.990 1 1.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX 1-MHz tolerance over VCC 25°C 8-MHz tolerance over VCC 25°C 12-MHz tolerance over VCC 16-MHz tolerance over VCC UNIT 1.8 V to 3.6 V -3 ±2 +3 % 1.8 V to 3.6 V -3 ±2 +3 % 25°C 2.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Typical Characteristics - Calibrated DCO Frequency CALIBRATED 1-MHz FREQUENCY vs SUPPLY VOLTAGE CALIBRATED 8-MHz FREQUENCY vs SUPPLY VOLTAGE 8.20 1.04 8.15 1.03 Frequency − MHz Frequency − MHz 8.10 1.02 TA = −40 °C 1.01 TA = 25 °C TA = −40 °C TA = 85 °C 8.05 8.00 TA = 25 °C 7.95 7.90 1.00 TA = 85 °C 7.85 TA = 105 °C 0.99 1.5 2.0 2.5 3.0 3.5 7.80 1.5 4.0 TA = 105 °C 2.0 Figure 15.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Wake-Up From Lower-Power Modes (LPM3/4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ tDCO,LPM3/4 BCSCTL1 = CALBC1_8MHZ, DCO clock wake-up time DCOCTL = CALDCO_8MHZ from LPM3/4 (1) BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ (1) (2) UNIT 2 2.2 V, 3 V 1.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 DCO With External Resistor ROSC (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fDCO,ROSC DCO output frequency with ROSC DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0, TA = 25°C DT Temperature drift DV Drift with VCC (1) VCC TYP UNIT 2.2 V 1.8 3V 1.95 DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0 2.2 V, 3 V ±0.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Crystal Oscillator LFXT1, High-Frequency Mode (1) PARAMETER VCC MIN XTS = 1, LFXT1Sx = 0, XCAPx = 0 1.8 V to 3.6 V LFXT1 oscillator crystal frequency, HF mode 1 XTS = 1, LFXT1Sx = 1, XCAPx = 0 LFXT1 oscillator crystal frequency, HF mode 2 XTS = 1, LFXT1Sx = 2, XCAPx = 0 fLFXT1,HF0 LFXT1 oscillator crystal frequency, HF mode 0 fLFXT1,HF1 fLFXT1,HF2 TEST CONDITIONS MAX UNIT 0.4 1 MHz 1.8 V to 3.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1) OSCILLATION ALLOWANCE vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25°C Oscillation Allowance − W 100000.00 10000.00 1000.00 LFXT1Sx = 2 100.00 LFXT1Sx = 0 10.00 0.10 1.00 LFXT1Sx = 1 10.00 100.00 Crystal Frequency − MHz Figure 23.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Crystal Oscillator XT2 (1) PARAMETER VCC MIN XT2Sx = 0 1.8 V to 3.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Typical Characteristics - XT2 Oscillator OSCILLATION ALLOWANCE vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25°C Oscillation Allowance − W 100000.00 10000.00 1000.00 XT2Sx = 2 100.00 XT2Sx = 1 XT2Sx = 0 10.00 0.10 1.00 10.00 100.00 Crystal Frequency − MHz Figure 25. XT Oscillator Supply Current − µA OSCILLATOR SUPPLY CURRENT vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25°C 1600.0 1500.0 1400.0 1300.0 1200.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTA Timer_A clock frequency Internal: SMCLK, ACLK External: TACLK, INCLK Duty cycle = 50% ± 10% tTA,cap Timer_A capture timing TA0, TA1, TA2 VCC MIN TYP MAX 2.2 V 10 3V 16 2.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fUSCI USCI input clock frequency fBITCLK BITCLK clock frequency (equals baud rate in MBaud) (1) tτ UART receive deglitch time (2) (1) (2) CONDITIONS VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ± 10% 2.2 V, 3 V 2.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 27. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 28.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,SI tHD,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 29. SPI Slave Mode, CKPH = 0 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 30.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Comparator_A+ (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS I(DD) CAON = 1, CARSEL = 0, CAREF = 0 I(Refladder/RefDiode) CAON = 1, CARSEL = 0, CAREF = 1/2/3, No load at P2.3/CA0/TA1 and P2.4/CA1/TA2 VCC MIN TYP MAX 2.2 V 25 40 3V 45 60 2.2 V 30 50 3V 45 71 UNIT µA µA VIC Common-mode input voltage range CAON = 1 2.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 0V VCC 0 1 CAF CAON To Internal Modules Low Pass Filter + _ V+ V− 0 0 1 1 CAOUT Set CAIFG Flag τ ≈ 2.0 µs Figure 32. Comparator_A+ Block Diagram VCAOUT Overdrive V− 400 mV t (response) V+ Figure 33. Comparator_A+ Overdrive Definition Figure 34. Comparator_A+ Short Resistance Test Condition CASHORT CA0 CA1 1 VIN + − Comparator_A+ CASHORT = 1 IOUT = 10µA Figure 35.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Typical Characteristics, Comparator_A+ V(RefVT) vs TEMPERATURE (VCC = 3 V) 650 V(RefVT) vs TEMPERATURE (VCC = 2.2 V) 650 VCC = 2.2 V 600 V(REFVT) − Reference Volts −mV V(REFVT) − Reference Volts −mV VCC = 3 V Typical 550 500 450 400 −45 −25 −5 15 35 55 75 600 Typical 550 500 450 400 −45 95 −25 TA − Free-Air Temperature − °C −5 15 35 55 75 95 TA − Free-Air Temperature − °C Figure 1.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 12-bit ADC, Power Supply and Input Range Conditions (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC AVCC Analog supply voltage AVCC and DVCC are connected together AVSS and DVSS are connected together V(AVSS) = V(DVSS) = 0 V V(P6.x/Ax) Analog input voltage range (2) All P6.0/A0 to P6.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com 12-Bit ADC, Built-In Reference over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Positive built-in reference voltage output VREF+ AVCC(min) AVCC minimum voltage, positive built-in reference active TA REF2_5V = 1 for 2.5 V, IVREF+max ≤ IVREF+ ≤ IVREF+min -40°C to 85°C REF2_5V = 0 for 1.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 From Power Supply DVCC + − DVSS 10 µ F 100 nF AVCC + − AVSS Apply External Reference [VeREF+] or Use Internal Reference [VREF+] 10 µ F 100 nF VREF+ or V eREF+ + − 10 µ F 100 nF Apply External Reference VREF−/VeREF− + − 10 µ F 100 nF Figure 40.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com 12-Bit ADC, Timing Parameters over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS fADC12CLK fADC12OSC tCONVERT Internal ADC12 oscillator Conversion time VCC MIN For specified performance of ADC12 linearity parameters 2.2 V, 3 V 0.45 5 6.3 MHz ADC12DIV = 0, fADC12CLK = fADC12OSC 2.2 V, 3 V 3.7 5 6.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 12-Bit ADC, Temperature Sensor and Built-In VMID over recommended operating free-air temperature range (unless otherwise noted) PARAMETER ISENSOR Operating supply current into AVCC terminal (1) TEST CONDITIONS REFON = 0, INCH = 0Ah, ADC12ON = 1, TA = 25°C VSENSOR (2) (3) ADC12ON = 1, INCH = 0Ah, TA = 0°C TCSENSOR (3) ADC12ON = 1, INCH = 0Ah VCC MIN TYP MAX 2.2 V 40 120 3V 60 160 2.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC (PGM/ERASE) Program and erase supply voltage 2.2 3.6 V fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from VCC during program 2.2 V/3.6 V 1 5 mA IERASE Supply current from VCC during erase 2.2 V/3.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 APPLICATION INFORMATION Port P1 Pin Schematic: P1.0 to P1.7, Input/Output With Schmitt Trigger P1REN.x P1DIR.x Pad Logic 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK P1.5/TA0 P1.6/TA1 P1.7/TA2 P1SEL.x P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q Set P1IFG.x P1SEL.x P1IES.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Table 20. Port P1.0 to P1.7 Pin Functions PIN NAME (P1.x) x FUNCTION P1.0 (I/O) P1.0/TACLK 0 1 2 0 0 1 CAOUT 1 1 I: 0; O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 I: 0; O: 1 0 Timer_A3.CCI1A 0 1 Timer_A3.TA1 1 1 I: 0; O: 1 0 Timer_A3.CCI2A 0 1 Timer_A3.TA2 1 1 I: 0; O: 1 0 1 1 I: 0; O: 1 0 1 1 I: 0; O: 1 0 P1.3 (I/O) P1.3/TA2 3 P1.4/SMCLK 4 P1.5/TA0 5 P1.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Port P2 Pin Schematic: P2.0 to P2.4, P2.6, and P2.7, Input/Output With Schmitt Trigger Pad Logic To Comparator_A From Comparator_A CAPD.x P2REN.x P2DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.x DVSS Bus Keeper EN P2SEL.x P2IN.x EN Module X IN P2.0/ACLK/CA2 P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.6/ADC12CLK/CA6 P2.7/TA0/CA7 D P2IE.x P2IRQ.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Table 21. Port P2.0 to P2.4, P2.6, and P2.7 Pin Functions PIN NAME (P2.x) x 0 P2.0/ACLK/CA2 1 P2.1/TAINCLK/CA3 2 P2.2/CAOUT/TA0/CA4 3 P2.3/CA0/TA1 4 P2.4/CA1/TA2 6 P2.6/ADC12CLK (2)/CA6 7 P2.7/TA0/CA7 (1) (2) 70 FUNCTION CONTROL BITS / SIGNALS (1) CAPD.x P2DIR.x P2SEL.x P2.0 (I/O) 0 I: 0; O: 1 0 ACLK 0 1 1 CA2 1 X X P2.1 (I/O) 0 I: 0; O: 1 0 Timer_A3.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger Pad Logic To Comparator From Comparator CAPD.5 To DCO DCOR in DCO P2REN.5 P2DIR.5 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.5 DVSS P2.5/ROSC/CA5 Bus Keeper EN P2SEL.5 P2IN.5 EN Module X IN D P2IE.5 P2IRQ.5 EN Q Set P2IFG.5 P2SEL.5 P2IES.5 Interrupt Edge Select Table 22. Port P2.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Port P3 Pin Schematic: P3.0 to P3.7, Input/Output With Schmitt Trigger Pad Logic P3REN.x P3DIR.x Module direction P3OUT.x Module X OUT 0 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 0 1 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO P3.5/UCA0RXD/UCA0SOMI P3.6/UCA1TXD/UCA1SIMO P3.7/UCA1RXD/UCA1SOMI P3SEL.x P3IN.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Port P4 Pin Schematic: P4.0 to P4.7, Input/Output With Schmitt Trigger Pad Logic P4REN.x 0 P4DIR.x 0 Module X OUT 1 0 DVCC 1 P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3/TB3 P4.4/TB4 P4.5/TB5 P4.6/TB6 P4.7/TBCLK P4SEL.x P4IN.x EN Module X IN 1 Direction 0: Input 1: Output 1 P4OUT.x DVSS D Table 24. Port P4.0 to P4.7 Pin Functions PIN NAME (P4.x) x FUNCTION P4.0 (I/O) P4.0/TB0 0 1 2 0 0 1 Timer_B7.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Port P5 Pin Schematic: P5.0 to P5.3, Input/Output With Schmitt Trigger Pad Logic P5REN.x P5DIR.x 0 Module Direction 1 P5OUT.x 0 Module X OUT DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 P5.0/UCB1STE/UCA1CLK P5.1/UCB1SIMO/UCB1SDA P5.2/UCB1SOMI/UCB1SCL P5.3/UCB1CLK/UCA1STE P5SEL.x P5IN.x EN Module X IN D Table 25. Port P5.0 to P5.3 Pin Functions PIN NAME (P5.x) P5.0/UCB1STE (2)/UCA1CLK (2) P5.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Port P5 Pin Schematic: P5.4 to P5.7, Input/Output With Schmitt Trigger Pad Logic P5REN.x P5DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P5OUT.x DVSS P5.4/MCLK P5.5/SMCLK P5.6/ACLK P5.7/TBOUTH/SVSOUT P5SEL.x P5IN.x EN D Module X IN Table 26. Port P5.4 to P5.7 Pin Functions PIN NAME (P5.x) P5.4/MCLK P5.5/SMCLK x 4 5 P5.6/ACLK 6 P5.7/TBOUTH/SVSOUT 7 FUNCTION P5.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com Port P6 Pin Schematic: P6.0 to P6.6, Input/Output With Schmitt Trigger Pad Logic ADC12 Ax From ADC12 P6REN.x P6DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P6OUT.x DVSS P6.0/A0 P6.1/A1 P6.2/A2 P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 Bus Keeper EN P6SEL.x P6IN.x EN Module X IN D Table 27. Port P6.0 to P6.6 Pin Functions PIN NAME (P6.x) P6.0/A0 (2) P6.1/A1 (2) P6.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 Port P6 Pin Schematic: P6.7, Input/Output With Schmitt Trigger Pad Logic To SVS Mux VLD = 15 ADC12 A7 From ADC12 P6REN.7 P6DIR.7 0 P6OUT.7 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P6.7/A7/SVSIN Bus Keeper EN P6SEL.7 P6IN.7 EN Module X IN D Table 28. Port P6.7 Pin Functions PIN NAME (P6.x) x FUNCTION P6.7 (I/O) P6.7/A7/SVSIN (1) (2) 7 CONTROL BITS / SIGNALS (1) P6DIR.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.
MSP430F23x MSP430F24x(1) MSP430F2410 www.ti.com SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 JTAG Fuse Check Mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned.
MSP430F23x MSP430F24x(1) MSP430F2410 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PACKAGE MATERIALS INFORMATION www.ti.com 12-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F233TPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F235TPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F2410TPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 12-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F233TPMR LQFP PM 64 1000 336.6 336.6 41.3 MSP430F235TPMR LQFP PM 64 1000 336.6 336.6 41.3 MSP430F2410TPMR LQFP PM 64 1000 336.6 336.6 41.3 MSP430F2410TPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F2471TPMR LQFP PM 64 1000 336.6 336.6 41.3 MSP430F247TPMR LQFP PM 64 1000 336.6 336.6 41.
MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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