Datasheet

www.ti.com Timer_B Operation
13.2 Timer_B Operation
The Timer_B module is configured with user software. The setup and operation of Timer_B is discussed in
the following sections.
13.2.1 16-Bit Timer Counter
The 16-bit timer/counter register, TBR, increments or decrements (depending on mode of operation) with
each rising edge of the clock signal. TBR can be read or written with software. Additionally, the timer can
generate an interrupt when it overflows.
TBR may be cleared by setting the TBCLR bit. Setting TBCLR also clears the clock divider and count
direction for up/down mode.
NOTE: Modifying Timer_B Registers
It is recommended to stop the timer before modifying its operation (with exception of the
interrupt enable, interrupt flag, and TBCLR) to avoid errant operating conditions.
When the timer clock is asynchronous to the CPU clock, any read from TBR should occur
while the timer is not operating or the results may be unpredictable. Alternatively, the timer
may be read multiple times while operating, and a majority vote taken in software to
determine the correct reading. Any write to TBR will take effect immediately.
13.2.1.1 TBR Length
Timer_B is configurable to operate as an 8-, 10-, 12-, or 16-bit timer with the CNTLx bits. The maximum
count value, TBR
(max)
, for the selectable lengths is 0FFh, 03FFh, 0FFFh, and 0FFFFh, respectively. Data
written to the TBR register in 8-, 10-, and 12-bit mode is right-justified with leading zeros.
13.2.1.2 Clock Source Select and Divider
The timer clock can be sourced from ACLK, SMCLK, or externally via TBCLK or INCLK (INCLK is device-
specific, often assigned to the inverted TBCLK, refer to device-specific data sheet). The clock source is
selected with the TBSSELx bits. The selected clock source may be passed directly to the timer or divided
by 2,4, or 8, using the IDx bits. The clock divider is reset when TBCLR is set.
13.2.2 Starting the Timer
The timer may be started or restarted in the following ways:
• The timer counts when MCx > 0 and the clock source is active.
• When the timer mode is either up or up/down, the timer may be stopped by loading 0 to TBCL0. The
timer may then be restarted by loading a nonzero value to TBCL0. In this scenario, the timer starts
incrementing in the up direction from zero.
13.2.3 Timer Mode Control
The timer has four modes of operation as described in Table 13-1: stop, up, continuous, and up/down.
The operating mode is selected with the MCx bits.
Table 13-1. Timer Modes
MCx Mode Description
00 Stop The timer is halted.
01 Up The timer repeatedly counts from zero to the value of compare register TBCL0.
10 Continuous The timer repeatedly counts from zero to the value selected by the CNTLx bits.
11 Up/down The timer repeatedly counts from zero up to the value of TBCL0 and then back down to zero.
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SLAU144J–December 2004–Revised July 2013 Timer_B
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