Datasheet

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3.4.4 Instruction Cycles and Lengths ................................................................................. 60
3.4.5 Instruction Set Description ...................................................................................... 62
3.4.6 Instruction Set Details ............................................................................................ 64
4 CPUX .............................................................................................................................. 115
4.1 CPU Introduction ......................................................................................................... 116
4.2 Interrupts .................................................................................................................. 118
4.3 CPU Registers ............................................................................................................ 119
4.3.1 Program Counter (PC) ......................................................................................... 119
4.3.2 Stack Pointer (SP) .............................................................................................. 119
4.3.3 Status Register (SR) ............................................................................................ 121
4.3.4 Constant Generator Registers (CG1 and CG2) ............................................................. 122
4.3.5 General-Purpose Registers (R4 to R15) ..................................................................... 123
4.4 Addressing Modes ....................................................................................................... 125
4.4.1 Register Mode ................................................................................................... 126
4.4.2 Indexed Mode ................................................................................................... 127
4.4.3 Symbolic Mode .................................................................................................. 131
4.4.4 Absolute Mode .................................................................................................. 136
4.4.5 Indirect Register Mode ......................................................................................... 138
4.4.6 Indirect Autoincrement Mode .................................................................................. 139
4.4.7 Immediate Mode ................................................................................................ 140
4.5 MSP430 and MSP430X Instructions .................................................................................. 142
4.5.1 MSP430 Instructions ............................................................................................ 142
4.5.2 MSP430X Extended Instructions .............................................................................. 147
4.6 Instruction Set Description .............................................................................................. 160
4.6.1 Extended Instruction Binary Descriptions .................................................................... 161
4.6.2 MSP430 Instructions ............................................................................................ 163
4.6.3 MSP430X Extended Instructions .............................................................................. 215
4.6.4 MSP430X Address Instructions ............................................................................... 257
5 Basic Clock Module+ ........................................................................................................ 272
5.1 Basic Clock Module+ Introduction ..................................................................................... 273
5.2 Basic Clock Module+ Operation ....................................................................................... 275
5.2.1 Basic Clock Module+ Features for Low-Power Applications .............................................. 276
5.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ............................................... 276
5.2.3 LFXT1 Oscillator ................................................................................................ 276
5.2.4 XT2 Oscillator ................................................................................................... 277
5.2.5 Digitally-Controlled Oscillator (DCO) ......................................................................... 277
5.2.6 DCO Modulator .................................................................................................. 279
5.2.7 Basic Clock Module+ Fail-Safe Operation ................................................................... 279
5.2.8 Synchronization of Clock Signals ............................................................................. 280
5.3 Basic Clock Module+ Registers ........................................................................................ 282
5.3.1 DCOCTL, DCO Control Register ............................................................................. 283
5.3.2 BCSCTL1, Basic Clock System Control Register 1 ........................................................ 283
5.3.3 BCSCTL2, Basic Clock System Control Register 2 ........................................................ 284
5.3.4 BCSCTL3, Basic Clock System Control Register 3 ........................................................ 285
5.3.5 IE1, Interrupt Enable Register 1 .............................................................................. 286
5.3.6 IFG1, Interrupt Flag Register 1 ................................................................................ 286
6 DMA Controller ................................................................................................................ 287
6.1 DMA Introduction ......................................................................................................... 288
6.2 DMA Operation ........................................................................................................... 290
6.2.1 DMA Addressing Modes ....................................................................................... 290
6.2.2 DMA Transfer Modes ........................................................................................... 291
6.2.3 Initiating DMA Transfers ....................................................................................... 297
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SLAU144J–December 2004–Revised July 2013 Contents
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