Datasheet

www.ti.com Basic Clock Module+ Registers
5.3.1 DCOCTL, DCO Control Register
7 6 5 4 3 2 1 0
DCOx MODx
rw-0 rw-1 rw-1 rw-0 rw-0 rw-0 rw-0 rw-0
DCOx Bits 7-5 DCO frequency select. These bits select which of the eight discrete DCO frequencies within the range
defined by the RSELx setting is selected.
MODx Bits 4-0 Modulator selection. These bits define how often the f
DCO+1
frequency is used within a period of 32 DCOCLK
cycles. During the remaining clock cycles (32-MOD) the f
DCO
frequency is used. Not useable when
DCOx = 7.
5.3.2 BCSCTL1, Basic Clock System Control Register 1
7 6 5 4 3 2 1 0
XT2OFF XTS
(1)(2)
DIVAx RSELx
rw-(1) rw-(0) rw-(0) rw-(0) rw-0 rw-1 rw-1 rw-1
XT2OFF Bit 7 XT2 off. This bit turns off the XT2 oscillator
0 XT2 is on
1 XT2 is off if it is not used for MCLK or SMCLK.
XTS Bit 6 LFXT1 mode select.
0 Low-frequency mode
1 High-frequency mode
DIVAx Bits 5-4 Divider for ACLK
00 /1
01 /2
10 /4
11 /8
RSELx Bits 3-0 Range select. Sixteen different frequency ranges are available. The lowest frequency range is selected by
setting RSELx = 0. RSEL3 is ignored when DCOR = 1.
(1)
XTS = 1 is not supported in MSP430x20xx and MSP430G2xx devices (see Figure 5-1 and Figure 5-2 for details on supported settings for
all devices).
(2)
This bit is reserved in the MSP430AFE2xx devices.
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SLAU144J–December 2004–Revised July 2013 Basic Clock Module+
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