Datasheet

DMA Introduction

www.ti.com

6.1 DMA Introduction

The direct memory access (DMA) controller transfers data from one address to another, without CPU

intervention, across the entire address range. For example, the DMA controller can move data from the

ADC12 conversion memory to RAM.

Devices that contain a DMA controller may have one, two, or three DMA channels available. Therefore,

depending on the number of DMA channels available, some features described in this chapter are not

applicable to all devices.

Using the DMA controller can increase the throughput of peripheral modules. It can also reduce system

power consumption by allowing the CPU to remain in a low-power mode without having to awaken to

move data to or from a peripheral.

The DMA controller features include:

• Up to three independent transfer channels

• Configurable DMA channel priorities

• Requires only two MCLK clock cycles per transfer

• Byte or word and mixed byte/word transfer capability

• Block sizes up to 65535 bytes or words

• Configurable transfer trigger selections

• Selectable edge or level-triggered transfer

• Four addressing modes

• Single, block, or burst-block transfer modes

The DMA controller block diagram is shown in Figure 6-1.

288

DMA Controller SLAU144J–December 2004–Revised July 2013

Submit Documentation Feedback