Datasheet

MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
______________________________________________________________________________________ 17
In deep overload or short-circuit conditions when the
FB voltage drops below 0.4V, the switching frequency
is reduced to 1/4 x f
SW
to provide sufficient time for the
inductor to discharge. During overload conditions, if the
voltage across the inductor is not high enough to allow
for the inductor current to properly discharge, current
runaway may occur. Current runaway can destroy the
device in spite of internal thermal-overload protection.
Reducing the switching frequency during overload con-
ditions prevents current runaway.
Thermal-Overload Protection
During continuous short circuit or overload at the out-
put, the power dissipation in the IC can exceed its limit.
Internal thermal shutdown is provided to avoid irre-
versible damage to the device. When the die tempera-
ture or junction temperature exceeds +150°C, an
on-chip thermal sensor shuts down the device, forcing
the internal switches to turn off, allowing the IC to cool.
The thermal sensor turns the part on again after the
junction temperature cools by +30°C. During thermal
shutdown, both regulators shut down, RST goes low,
and soft-start resets.
Applications Information
Setting the Switching Frequency
The controller generates the clock signal by dividing
down the internal oscillator or the SYNC input signal
when driven by an external oscillator. The switching
frequency equals half the oscillator frequency (f
SW
=
f
OSC
/ 2). The internal oscillator frequency is set by a
resistor (R
OSC
) connected from OSC to SGND. The
relationship between f
SW
and R
OSC
is:
where f
SW
and f
OSC
are in hertz, and R
OSC
is in ohms.
For example, a 1250kHz switching frequency is set with
R
OSC
= 10kΩ. Higher frequencies allow designs with
lower inductor values and less output capacitance.
Consequently, peak currents and I
2
R losses are lower
at higher switching frequencies, but core losses, gate-
charge currents, and switching losses increase.
A rising clock edge on SYNC is interpreted as a syn-
chronization input. If the SYNC signal is lost, the inter-
nal oscillator takes control of the switching rate,
returning the switching frequency to that set by R
OSC
.
This maintains output regulation even with intermittent
SYNC signals. When an external synchronization signal
is used, R
OSC
should be set for the oscillator frequency
to be lower than or equal to the SYNC rate (f
SYNC
).
Buck Converter
Effective Input Voltage Range
Although the MAX5072 converters can operate from
input supplies ranging from 4.5V to 23V, the input volt-
age range can be effectively limited by the MAX5072
duty-cycle limitations for a given output voltage. The
maximum input voltage is limited by the minimum on-
time (t
ON(MIN)
):
where t
ON(MIN)
is 100ns. The minimum input voltage is
limited by the maximum duty cycle (D
MAX
= 0.88):
where V
DROP1
is the total parasitic voltage drops in the
inductor discharge path, which includes the forward
voltage drop (V
D
) of the rectifier, the series resistance of
the inductor, and the PC board resistance. V
DROP2
is
the total resistance in the charging path, which includes
the on-resistance of the high-side switch, the series
resistance of the inductor, and the PC board resistance.
Setting the Output Voltage
For 0.8V or greater output voltages, connect a voltage-
divider from OUT_ to FB_ to SGND (Figure 6). Select
R
B
(FB_ to SGND resistor) to between 1kΩ and 10kΩ.
Calculate R
A
(OUT_ to FB_ resistor) with the following
equation:
where V
FB_
= 0.8V (see the Electrical Characteristics table)
and V
OUT_
can range from V
FB_
to 28V (boost operation).
RR
V
V
AB
OUT
FB
=
⎛
⎝
⎜
⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
−1
V
VV
VV
IN MIN
OUT DROP
DROP DROP()
.
=
+
⎡
⎣
⎢
⎤
⎦
⎥
+
−
1
21
088
V
V
tf
IN MAX
OUT
ON MIN SW
()
()
≤
×
R
12.5 10
f
OSC
9
SW
=
×
R
A
LX_
FB_
V
OUT_
> 0.8V
R
B
MAX5072
R
C
FB_
LX_
BYPASS
V
OUT_
< 0.8V
R
A
MAX5072
Figure 6. Adjustable Output Voltage