Datasheet

MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
16 ______________________________________________________________________________________
Dying Gasp Comparator (PFI/PFO)
The MAX5072 contains an uncommitted comparator
with an open-drain output. The inverting input of the
comparator is connected to an internal precision 0.78V
reference. Connect the noninverting input (PFI) to V
IN
through a resistor-divider to program the input trip
threshold (V
TRIP
). The power-fail output (PFO) is pulled
low when PFI drops below 0.78V. PFI provides 20mV
hysteresis to avoid glitches during transition. The PFO
signal provides an advance signal to the processor
before the converter 1/converter 2 loses regulation. The
input trip threshold (V
TRIP
) can be adjusted to provide
advance signaling before the outputs drop to 92.5% of
the regulation voltage.
The input capacitors hold charge and provide energy
to the converter after V
IN
is disconnected. The hold-up
time (t
HOLD
) is defined as the time when the input volt-
age drops below V
TRIP
and the output falls out of regu-
lation at the low end of the input voltage range V
IN(MIN)
(Figure 5). Use the following equations to calculate the
resistor-divider and the C
IN
required for the proper
hold-up time.
where η1 and η2 are efficiencies of the converter 1 and
converter 2, respectively.
R
2
can be any value from 10kΩ to 100kΩ (Figure 5).
Current Limit
The internal switch current of each converter is sensed
using an internal current mirror. Converter 1 and con-
verter 2 have 2A and 1A internal switches. When the
peak switch current crosses the current-limit threshold
of 3A (typ) and 1.8A (typ) for converter 1 and converter
2, respectively, the on cycle is terminated immediately
and the inductor is allowed to discharge. The next
cycle resumes at the next clock pulse.
R1 R2
V
0.78
TRIP
1
= −
⎛
⎝
⎜
⎞
⎠
⎟
C
2
P
1
P
2
VV
t
IN
OUT1 OUT2
TRIP
22
IN(MIN)
HOLD
=
+
⎛
⎝
⎜
⎞
⎠
⎟
−
⎛
⎝
⎞
⎠
×
ηη
FB1FB2
EN1EN2
VL
R1R2
C1C2
VL
VL V+
MAX5072
OUTPUT2 OUTPUT1
DRAIN2
SOURCE2
DRAIN1
SOURCE1
V
IN
VL
FB1FB2
EN1EN2
SEQUENCING—OUTPUT 2 DELAYED WITH RESPECT TO OUTPUT 1. R1/C1 AND R2/C2 ARE SIZED FOR REQUIRED SEQUENCING.
VL
VL
VL V+
MAX5072
OUTPUT2 OUTPUT1
DRAIN2
SOURCE2
DRAIN1
SOURCE1
PGOOD1
V
IN
VL
Figure 4. Power-Supply Sequencing Configurations
PFI
PFO
PFO
CIN
VL
VL
VL V+
MAX5072
OUTPUT2 OUTPUT1
DRAIN2
SOURCE2
DRAIN1
SOURCE1
V
IN
R1
R2
Figure 5. Dying Gasp Feature Monitors Input Supply