Datasheet

MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
18 ______________________________________________________________________________________
Control Loop
The MAX5060/MAX5061 use an average-current-mode
control scheme to regulate the output voltage (Figure 5).
The main control loop consists of an inner current loop
and an outer voltage loop. The inner loop controls the
output current (I
PHASE
), while the outer loop controls the
output voltage. The inner current loop absorbs the
inductor pole reducing the order of the outer voltage
loop to that of a single-pole system.
The current loop consists of a current-sense resistor
(R
SENSE
), a current-sense amplifier (CA), a current-
error amplifier (CEA), an oscillator providing the carrier
ramp, and a PWM comparator (CPWM) (Figure 6). The
precision CA amplifies the sense voltage across RS by
a factor of 34.5. The inverting input to the CEA senses
the CA output. The CEA output is the difference
between the voltage-error-amplifier output (EAOUT)
and the amplified voltage from the CA. The RC com-
pensation networks connected to CLP provide external
frequency compensation for the CEA. The start of every
clock cycle enables the high-side drivers and initiates a
PWM ON cycle. Comparator CPWM compares the out-
put voltage from the CEA with a 0 to 2V ramp from the
oscillator. The PWM ON cycle terminates when the
ramp voltage exceeds the error voltage.
The MAX5060 outer voltage control loop consists of the
differential amplifier (DIFF AMP), reference voltage, and
VEA. The unity-gain differential amplifier provides true-
differential remote sensing of the output voltage. The dif-
ferential amplifier output connects to the inverting input
(EAN) of the VEA. For MAX5061, the DIFF AMP is
bypassed and the inverting input is available to the pin
for direct feedback. The noninverting input of the VEA is
internally connected to an internal precision reference
voltage. The MAX5060/MAX5061 reference voltage is set
to 0.6V. The VEA controls the inner current loop (Figure
4). Use a resistive feedback network to set the VEA gain
as required by the adaptive voltage-positioning circuit
(see the Adaptive Voltage Positioning section).
2 x f
S
(V/s)
RAMP
CLK
CSP
CSN
GM
IN
SHDN
CLP
V
DD
BST
DH
LX
DL
PGND
A
V
= 34.5
PWM
COMPARATOR
PEAK-CURRENT
COMPARATOR
60mV
S
R
Q
Q
g
m
= 550µS
CPWM
CEA
CA
MAX5060
Figure 6. Phase Circuit