Datasheet
Table Of Contents
- TABLE OF CONTENTS
- LIST OF FIGURES
- LIST OF TABLES
- General Description
- Applications
- Features and Benefits
- Application Diagram
- 16-Bit to 20-Bit SAR ADC Family
- Absolute Maximum Ratings
- Package Thermal Characteristics
- Electrical Characteristics
- Typical Operating Characteristics
- Pin Configuration
- Pin Description
- Functional Diagram
- Detailed Description
- Digital Interface
- Register Map
- Typical Application Circuit
- Layout, Grounding, and Bypassing
- Definitions
- Selector Guide
- Ordering Information
- Chip Information
- Package Information
- Revision History
- Figure 1. Signal Ranges
- Figure 2. Simplified Model of Input Sampling Circuit
- Figure 3. Conversion Frame, SAR Conversion, Track and Read Operation
- Figure 4. Ideal Transfer Characteristic
- Figure 5. Read During Track Phase
- Figure 6. Read During SAR Conversion Phase
- Figure 7. Split Read Mode
- Figure 8. SPI Interface Connection
- Figure 9. DIN Timing for Register Write Operations
- Figure 10. Timing Diagram for Data Out Reading After Conversion
- Figure 11. Mode Register Write
- Figure 12. Register Read
- Figure 13. Unipolar Single-Ended Input
- Figure 14. Bipolar Single-Ended Input
- Figure 15. Top Layer Sample Layout
- Table 1. ADC Driver Amplifier Recommendation
- Table 2. Voltage Reference Configurations
- Table 3. MAX11905 External Reference Recommendations
- Table 4. Transfer Characteristic
- Table 5. DOUT Driver Strength
Denitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. For these
devices, this straight line is a line drawn between the end
points of the transfer function, once offset and gain errors
have been nullified.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. For
these devices, the DNL of each digital output code is
measured and the worst-case value is reported in the
Electrical Characteristics table. A DNL error specification
of less than ±1 LSB guarantees no missing codes.
Offset Error
The offset error is defined as the deviation between the
actual output and ideal output measured with 0V differen-
tial analog input voltage.
Gain Error
Gain error is defined as the difference between the
actual output range measured and the ideal output range
expected. It is measured with signal applied at the input
with an amplitude close to full-scale range.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the full-
scale analog input power to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-
to-digital noise is caused by quantization noise error only
and results directly from the ADC’s resolution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantiza-
tion noise: thermal noise, reference noise, clock jitter, etc.
SNR is computed by taking the ratio of the signal power to
the noise power, which includes all spectral components
not including the fundamental, the first five harmonics,
and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s power to the power of all
the other ADC output signals:
Signal
SINAD(dB) 10 LOG
(Noise Distortion
= ×
+
Effective Number of Bits
The effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantiza-
tion noise only. With an input range equal to the full-scale
range of the ADC, calculate the ENOB as follows:
SINAD - 1.76
ENOB
6.02
=
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the power
contained in the first five harmonics of the converted data
to the power of the fundamental. This is expressed as:
2222
2345
2
1
PPPP
THD 10 log
P
+++
= ×
where P
1
is the fundamental power and P
2
through P
5
is
the power of the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
power of the fundamental (maximum signal component)
to the power of the next-largest frequency component.
Aperture Delay
Aperture delay (t
AD
) is the time delay from the sampling
clock edge to the instant when an actual sample is taken.
Aperture Jitter
Aperture jitter (t
AJ
) is the sample-to-sample variation in
aperture delay.
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. This point is defined as full-power
input bandwidth frequency.
MAX11905 20-Bit, 1.6Msps, Low-Power, Fully Differential
SAR ADC
www.maximintegrated.com
Maxim Integrated
│
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