Datasheet
Table Of Contents
- TABLE OF CONTENTS
- LIST OF FIGURES
- LIST OF TABLES
- General Description
- Applications
- Features and Benefits
- Application Diagram
- 16-Bit to 20-Bit SAR ADC Family
- Absolute Maximum Ratings
- Package Thermal Characteristics
- Electrical Characteristics
- Typical Operating Characteristics
- Pin Configuration
- Pin Description
- Functional Diagram
- Detailed Description
- Digital Interface
- Register Map
- Typical Application Circuit
- Layout, Grounding, and Bypassing
- Definitions
- Selector Guide
- Ordering Information
- Chip Information
- Package Information
- Revision History
- Figure 1. Signal Ranges
- Figure 2. Simplified Model of Input Sampling Circuit
- Figure 3. Conversion Frame, SAR Conversion, Track and Read Operation
- Figure 4. Ideal Transfer Characteristic
- Figure 5. Read During Track Phase
- Figure 6. Read During SAR Conversion Phase
- Figure 7. Split Read Mode
- Figure 8. SPI Interface Connection
- Figure 9. DIN Timing for Register Write Operations
- Figure 10. Timing Diagram for Data Out Reading After Conversion
- Figure 11. Mode Register Write
- Figure 12. Register Read
- Figure 13. Unipolar Single-Ended Input
- Figure 14. Bipolar Single-Ended Input
- Figure 15. Top Layer Sample Layout
- Table 1. ADC Driver Amplifier Recommendation
- Table 2. Voltage Reference Configurations
- Table 3. MAX11905 External Reference Recommendations
- Table 4. Transfer Characteristic
- Table 5. DOUT Driver Strength
Detailed Description
The MAX11905 is a 20-bit, 1.6Msps maximum sampling
rate, fully differential input, single-channel SAR ADC with
SPI interface. This part features industry-leading sample
rate and resolution, while consuming very low power. The
MAX11905 has an integrated reference buffer to minimize
board space, component count, and system cost. An
internal oscillator drives the conversion and sets conver-
sion time, easing external timing considerations.
Analog Inputs
Both analog inputs, AIN+ and AIN-, range from 0V to
V
REF
. Thus, the differential input interval V
DIFF
= (AIN+)
- (AIN-) ranges from -V
REF
to +V
REF
, and the full-scale
range is:
REF
FSR 2 x V=
The nominal resolution step width of the least significant
bit (LSB) is:
N
FSR
LSB ,N 20
2
= =
The differential analog input must be centered around
a signal common mode of V
REF
/2, with a tolerance of
±100mV.
The reference voltage can range from 2.5V to the refer-
ence supply, REFVDD, if an external reference buffer
is used. When using the on-board reference buffer the
reference voltage can range from 2.5V to 200mV below
reference supply REFVDD. This will guarantee adequate
headroom for the internal reference buffers.
Figure 1 illustrates signal ranges for AIN+/AIN-, reference
voltage V
REF
and reference supply voltage REFVDD.
Figure 2 shows the input equivalent circuit of MAX11905.
The ADC samples both inputs, AIN+ and AIN-, with a fully
differential on-chip track-and-hold exhibiting no pipeline
delay or latency.
The MAX11905 has dedicated input clamps to protect
the inputs from overranging. Diodes D1 and D2 provide
ESD protection and act as a clamp for the input voltages.
Diodes D1/D2 can sustain a maximum forward current
of 100mA. The sampling switches connect inputs to the
sampling capacitors.
Figure 3 shows the timing of the digitizing cycle: Conversion
frame, SAR conversion, Track and Read operations.
Figure 1. Signal Ranges
V
REF
0V
0.5 x V
REF
AIN+
AIN-
V
REF
≤ V
REFVDD
≤ 3.6V
IF BUFFER IS DISABLED
V
REF
+200mV ≤ V
REFVDD
≤ 3.6V
IF BUFFER IS ENABLED
200mV
REFVDD
V
time
MAX11905 20-Bit, 1.6Msps, Low-Power, Fully Differential
SAR ADC
www.maximintegrated.com
Maxim Integrated
│
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