Inc. Recording Equipment User Manual
Table Of Contents
- Features
- Applications
- General Description
- Basic Block Diagram
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Input/Output Termination Recommendations
- Theory of Operation
- Thermal Performance
- Power-Up
- Power Supply Partitioning
- Serial Control Port
- I/O Register Map
- I/O Register Descriptions
- Serial Port Configuration (Register 0x0000 to Register 0x0005)
- Power-Down and Reset (Register 0x0010 to Register 0x0013)
- System Clock (Register 0x0020 to Register 0x0022)
- CMOS Output Divider (S-Divider) (Register 0x0100 to Register 0x0106)
- Frequency Tuning Word (Register 0x01A0 to Register 0x01AD)
- Register 0x01A0 to Register 0x01A5—Reserved
- Register 0x01A6—FTW0 (Frequency Tuning Word)
- Register 0x01A7—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01A8—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01A9—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01AA—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01AB—FTW0 (Frequency Tuning Word) (Continued)
- Register 0x01AC—Phase
- Register 0x01AD—Phase (Continued)
- Doubler and Output Drivers (Register 0x0200 to Register 0x0201)
- Calibration (User-Accessible Trim) (Register 0x0400 to Register 0x0410)
- Harmonic Spur Reduction (Register 0x0500 to Register 0x0509)
- Outline Dimensions
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Rev. D | Page 37 of 40
Register 0x0503—Spur A (Continued)
Table 38.
Bits Bit Name Description
[7:0] Spur A phase Linear offset for Spur B phase.
Register 0x0504—Spur A (Continued)
Table 39.
Bits Bit Name Description
[8] Spur A phase Linear offset for Spur A phase.
Register 0x0505—Spur B
Table 40.
Bits Bit Name Description
7 HSR-B enable Harmonic Spur Reduction B enable.
6 Amplitude gain × 2 Setting this bit doubles the gain of the cancelling circuit and also doubles the minimum step size.
[5:4] Reserved Reserved.
[3:0] Spur B harmonic Spur B Harmonic 1 to Spur B Harmonic 15. Allows user to choose which harmonic to eliminate.
Register 0x0506—Spur B (Continued)
Table 41.
Bits Bit Name Description
[7:0] Spur B magnitude Linear multiplier for Spur B magnitude.
Register 0x0508—Spur B (Continued)
Table 42.
Bits Bit Name Description
[7:0] Spur B phase Linear offset for Spur B phase.
Register 0x0509—Spur B (Continued)
Table 43.
Bits Bit Name Description
8 Spur B phase Linear offset for Spur B phase.