GSPS Direct Digital Synthesizer with 14-Bit DAC AD9912 FEATURES APPLICATIONS 1 GSPS internal clock speed (up to 400 MHz output directly) Integrated 1 GSPS 14-bit DAC 48-bit frequency tuning word with 4 µHz resolution Differential HSTL comparator Flexible system clock input accepts either crystal or external reference clock On-chip low noise PLL REFCLK multiplier 2 SpurKiller channels Low jitter clock doubler for frequencies up to 750 MHz Single-ended CMOS comparator; frequencies of <150 MHz Programmable
AD9912 TABLE OF CONTENTS Features .............................................................................................. 1 Power Supply Partitioning............................................................. 25 Applications ....................................................................................... 1 3.3 V Supplies.............................................................................. 25 General Description ....................................................................
AD9912 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V ± 5%, AVDD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, AVSS = 0 V, DVSS = 0 V, unless otherwise noted. Table 1. Parameter SUPPLY VOLTAGE DVDD_I/O (Pin 1) DVDD (Pin 3, Pin 5, Pin 7) AVDD3 (Pin 14, Pin 46, Pin 47, Pin 49) AVDD3 (Pin 37) AVDD (Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29, Pin 30, Pin 36, Pin 42, Pin 44, Pin 45, Pin 53) SUPPLY CURRENT Min Typ Max Unit 3.135 1.71 3.135 1.71 1.71 3.30 1.80 3.30 3.30 1.80 3.465 1.89 3.465 3.
AD9912 Parameter SYSTEM CLOCK INPUT SYSCLK PLL Bypassed Input Capacitance Input Resistance Internally Generated DC Bias Voltage2 Differential Input Voltage Swing SYSCLK PLL Enabled Input Capacitance Input Resistance Internally Generated DC Bias Voltage2 Differential Input Voltage Swing Crystal Resonator with SYSCLK PLL Enabled Motional Resistance CLOCK OUTPUT DRIVERS HSTL Output Driver Differential Output Voltage Swing Common-Mode Output Voltage2 CMOS Output Driver Output Voltage High (VOH) Output Voltage L
AD9912 AC SPECIFICATIONS fS = 1 GHz, DAC RSET = 10 kΩ, unless otherwise noted. Power supply pins within the range specified in the DC Specifications section. Table 2.
AD9912 Parameter CMOS Output Driver (AVDD3/Pin 37) @ 1.8 V Frequency Range Duty Cycle Rise Time/Fall Time (20% to 80%) DAC OUTPUT CHARACTERISTICS DCO Frequency Range (1st Nyquist Zone) Output Resistance Output Capacitance Full-Scale Output Current Gain Error Output Offset Voltage Compliance Range Min 0.008 45 Max Unit Test Conditions/Comments 55 5 40 65 6.
AD9912 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Digital I/O Supply Voltage (DVDD_I/O) DAC Supply Voltage (AVDD3 Pins) Maximum Digital Input Voltage Storage Temperature Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature THERMAL RESISTANCE Rating 2V 2V 3.6 V θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance 3.
AD9912 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SCLK SDIO SDO CSB IO_UPDATE RESET PWRDOWN DVSS DVSS S4 S3 AVDD AVSS DAC_OUTB DAC_OUT AVDD3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9912 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DAC_RSET AVDD3 AVDD3 AVDD AVDD AVSS AVDD FDBK_IN FDBK_INB AVSS OUT_CMOS AVDD3 AVDD OUT OUTB AVSS NOTES 1. NC = NO CONNECT. 2.
AD9912 Pin No. 32 Input/ Output I Pin Type 1.8 V CMOS Mnemonic CLKMODESEL 33, 39, 43, 52 34 O O GND 1.8 V HSTL AVSS OUTB 35 O 1.8 V HSTL OUT 37 I Power AVDD3 38 O 3.3 V CMOS OUT_CMOS 40 I Differential input FDBK_INB 41 I FDBK_IN 48 O 50 O 51 O Differential input Current set resistor Differential output Differential output 56, 57 58 I Power 3.3 V CMOS DVSS PWRDOWN 59 I 3.3 V CMOS RESET 60 I 3.3 V CMOS IO_UPDATE 61 I 3.3 V CMOS CSB 62 O 3.
AD9912 TYPICAL PERFORMANCE CHARACTERISTICS AVDD, AVDD3, and DVDD at nominal supply voltage; DAC RSET = 10 kΩ, unless otherwise noted. See Figure 26 for 1 GHz reference phase noise used for generating these plots. –50 10 SIGNAL POWER (dBm) –10 –65 –70 +25°C –40°C +85°C 200 300 OUTPUT FREQUENCY (MHz) 400 –50 –60 –70 500 –100 0 Figure 3. Wideband SFDR vs. Output Frequency at −40°C, +25°C, and +85°C, SYSCLK = 1 GHz (SYSCLK PLL Bypassed) 100 500 10 CARRIER: SFDR: FREQ.
AD9912 10 –80 20.1MHz CARRIER: –95dBc SFDR: 500kHz FREQ. SPAN: RESOLUTION BW: 300Hz 1kHz VIDEO BW: 0 –10 PHASE NOISE (dBc/Hz) SIGNAL POWER (dBm) –20 RMS JITTER (100Hz TO 40MHz): 99MHz: 413fs 399MHz: 222fs –90 –30 –40 –50 –60 –70 –80 –100 –110 –120 –130 399MHz –140 –90 –150 –100 19.95 20.05 20.15 FREQUENCY (MHz) 20.25 20.35 Figure 9. Narrow-Band SFDR at 20.1 MHz, SYSCLK = 1 GHz (SYSCLK PLL Bypassed) 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M Figure 12.
AD9912 800 –100 RMS JITTER (100Hz TO 100MHz): 600MHz: 585fs 800MHz: 406fs POWER DISSIPATION (mW) PHASE NOISE (dBc/Hz) –110 –120 800MHz –130 TOTAL 3.3V 1.8V 700 600MHz 600 500 400 300 200 –140 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M 0 250 06763-015 –150 100 Figure 15. Absolute Phase Noise Using HSTL Driver, SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed), HSTL Output Doubler Enabled 500 625 750 875 SYSTEM CLOCK FREQUENCY (MHz) 1000 Figure 18. Power Dissipation vs.
AD9912 –115 RMS JITTER (100Hz TO 100MHz): 83fs –125 PHASE NOISE (dBc/Hz) –125 –135 –145 –155 400MHz –165 –145 –155 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M –175 100 Figure 21.
AD9912 650 0.6 0.4 550 0.2 0 FREQUENCY = 600MHz tRISE (20%→80%) = 104ps tFALL (80%→20%) = 107ps V p-p = 1.17V DIFF. DUTY CYCLE = 50% –0.2 500 NOM SKEW 25°C, 1.8V SUPPLY WORST CASE (SLOW SKEW 90°C, 1.7V SUPPLY) –0.4 0 200 400 FREQUENCY (MHz) 600 800 –0.6 06763-021 450 0 Figure 27. HSTL Output Driver Single-Ended Peak-to-Peak Amplitude vs. Toggle Rate (100 Ω Across Differential Pair) 0.5 1.0 1.5 TIME (ns) 2.0 2.5 06763-024 AMPLITUDE (V) AMPLITUDE (mV) 600 Figure 30.
AD9912 INPUT/OUTPUT TERMINATION RECOMMENDATIONS 0.1µF 0.01µF AD9912 1.8V HSTL OUTPUT 100Ω AD9912 CLOCK SOURCE WITH DIFF. OUTPUT DOWNSTREAM DEVICE (HIGH-Z) SELF-BIASING SYSCLK INPUT 100Ω 0.01µF 06763-030 06763-027 0.1µF Figure 33. AC-Coupled HSTL Output Driver Figure 36. SYSCLK Differential Input, Non-Xtal 0.01µF 50Ω AD9912 1.8V HSTL OUTPUT CLOCK SOURCE WITH SINGLE-ENDED 1.8V CMOS OUTPUT DOWNSTREAM DEVICE (HIGH-Z) AVDD/2 0.
AD9912 THEORY OF OPERATION OUT_CMOS OUT 2× OUTB ÷S FDBK_IN FDBK_INB DIGITAL SYNTHESIS CORE FREQUENCY TUNING WORD DAC_OUT CONTROL LOGIC DDS/DAC DAC_OUTB LOW NOISE CLOCK MULTIPLIER CONFIGURATION LOGIC EXTERNAL ANALOG LOW-PASS FILTER EXTERNAL LOOP FILTER AMP S1 TO S4 DIGITAL INTERFACE SYSCLK SYSCLKB 06763-031 SYSCLK PORT Figure 39.
AD9912 PHASE OFFSET 48-BIT ACCUMULATOR 48 48 48 DAC_RSET DAC (14-BIT) DAC_OUT 14 D Q 19 19 ANGLE TO 14 AMPLITUDE CONVERSION DAC_OUTB 06763-032 FREQUENCY TUNING WORD (FTW) DAC I-SET REGISTERS AND LOGIC fS Figure 40. DDS Block Diagram The input to the DDS is a 48-bit FTW that provides the accumulator with a seed value. On each cycle of fS, the accumulator adds the value of the FTW to the running total of its output.
AD9912 MAGNITUDE (dB) IMAGE 0 IMAGE 1 IMAGE 2 IMAGE 3 IMAGE 4 0 –20 PRIMARY SIGNAL FILTER RESPONSE SIN(x)/x ENVELOPE –60 –80 SPURS f –100 fs/2 fs 3fs/2 2 fs 5fs/2 BASE BAND 06763-034 –40 Figure 42. DAC Spectrum vs. Reconstruction Filter Response For applications using the fundamental frequency of the DAC output, the response of the reconstruction filter should preserve the baseband signal (Image 0), while completely rejecting all other images.
AD9912 SYSCLK INPUTS Note that although these crystals meet the preceding criteria according to their data sheets, Analog Devices, Inc., does not guarantee their operation with the AD9912, nor does Analog Devices endorse one supplier of crystals over another. Functional Description An external time base connects to the AD9912 at the SYSCLK pins to generate the internal high frequency system clock (fS).
AD9912 SYSCLK PLL Multiplier EXTERNAL LOOP FILTER When the SYSCLK PLL multiplier path is employed, the frequency applied to the SYSCLK input pins must be limited so as not to exceed the maximum input frequency of the SYSCLK PLL phase detector. A block diagram of the SYSCLK generator appears in Figure 45. AVDD C2 C1 LOOP_FILTER 29 CHARGE PUMP ICP (125µA, 250µA, 375µA) 26 31 ~2pF KVCO (HIGH/LOW RANGE) VCO 06763-038 SYSCLK PLL MULTIPLIER 2 R1 FERRITE BEAD AD9912 Figure 46.
AD9912 Note that the SYSCLK PLL bypassed and SYSCLK PLL enabled input paths are internally biased to a dc level of ~1 V. Care should be taken to ensure that any external connections do not disturb the dc bias because this may significantly degrade performance. Generally, it is recommended that the SYSCLK inputs be ac-coupled, except when using a crystal resonator. OUTPUT CLOCK DRIVERS AND 2× FREQUENCY MULTIPLIER There are two output drivers provided by the AD9912.
AD9912 The procedure for tuning the spur reduction is as follows: Although the worst spurs tend to be harmonic in origin, the fact that the DAC is part of a sampled system results in the possibility of spurs appearing in the output spectrum that are not harmonically related to the fundamental. For example, if the DAC is sampled at 1 GHz and generates an output sinusoid of 170 MHz, the fifth harmonic would normally be at 850 MHz.
AD9912 THERMAL PERFORMANCE Table 7. Thermal Parameters Symbol θJA θJMA θJMA θJB θJC ΨJT Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board Junction-to-ambient thermal resistance, 0.0 m/sec air flow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec air flow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.0 m/sec air flow per JEDEC JESD51-6 (moving air) Junction-to-board thermal resistance, 1.
AD9912 POWER-UP POWER-ON RESET On initial power-up, the AD9912 internally generates a 75 ns RESET pulse. The pulse is initiated when both of the following two conditions are met: • • The 3.3 V supply is greater than 2.35 V ± 0.1 V. The 1.8 V supply is greater than 1.4 V ± 0.05 V. Less than 1 ns after RESET goes high, the S1 to S4 configuration pins go high impedance and remain high impedance until RESET is deactivated. This allows strapping and configuration during RESET.
AD9912 POWER SUPPLY PARTITIONING The AD9912 features multiple power supplies, and their power consumption varies with its configuration. This section covers which power supplies can be grouped together and how the power consumption of each block varies with frequency. 1.8 V SUPPLIES DVDD (Pin 3, Pin 5, and Pin 7) The recommendations here are for typical applications, and for these applications, there are four groups of power supplies: 3.3 V digital, 3.3 V analog, 1.8 V digital, and 1.8 V analog.
AD9912 SERIAL CONTROL PORT The AD9912 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The AD9912 serial control port can be configured for a single bidirectional I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO and SDO).
AD9912 Read If the instruction word is for a read operation (I15 = 1), the next N × 8 SCLK cycles clock out the data from the address specified in the instruction word, where N is 1, 2, 3, or 4, as determined by [W1:W0]. In this case, 4 is used for streaming mode where four or more words are transferred per read. The data readback is valid on the falling edge of SCLK. The default mode of the AD9912 serial control port is bidirectional mode, and the data readback appears on the SDIO pin.
AD9912 Table 10. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 R/W I14 W1 I13 W0 I12 A12 I11 A11 I10 A10 I9 A9 I8 A8 I7 A7 I6 A6 I5 A5 I4 A4 I3 A3 I2 A2 LSB I0 A0 I1 A1 CSB SCLK DON'T CARE R/W W1 W0 A12 A11 A10 A9 SDIO DON'T CARE A8 A7 A6 A5 A1 A0 A4 A3 A2 D7 D6 D5 16-BIT INSTRUCTION HEADER D4 D3 D2 D1 D0 D7 REGISTER (N) DATA D6 D5 D4 D3 D2 D1 D0 DON'T CARE REGISTER (N – 1) DATA 06763-043 DON'T CARE Figure 51.
AD9912 tS tH CSB tCLK tHIGH SCLK tLOW tDS SDIO BIT N BIT N + 1 Figure 56. Serial Control Port Timing—Write Table 11.
AD9912 I/O REGISTER MAP All address and bit locations that are left blank in Table 12 are unused. Table 12. Addr (Hex) Type1 Name Bit 7 Serial port configuration and part identification Serial SDO 0x0000 config.
AD9912 Addr (Hex) Type1 Name Calibration (user-accessible trim) 0x0400 Reserved to 0x040A 0x040B DAC fullscale 0x040C current 0x040D Reserved 0x040E Reserved 0x040F Reserved and 0x0410 Harmonic spur reduction 0x0500 M Spur A 0x0501 0x0503 0x0504 M M M 0x0505 M 0x0506 0x0508 0x0509 M M M 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00 DAC full-scale current, Bits[7:0] DAC full-scale current, Bits[9:8] 0xFF 0x01 0x00 0x10 0x00 HSR-A enable Amplitude gain × 2 Spur A harmonic, Bits[3:
AD9912 I/O REGISTER DESCRIPTIONS SERIAL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005) Register 0x0000—Serial Port Configuration Table 13. Bits [7:4] 3 2 Bit Name 1 LSB first 0 SDO active Long instruction Soft reset Description These bits are the mirror image of Bits[3:0]. Read-only; the AD9912 supports only long instructions. Resets register map, except for Register 0x0000.
AD9912 Register 0x0011—Reserved Register 0x0012—Reset (Autoclearing) To reset the entire chip, the user can use the (non-autoclearing) soft reset bit in Register 0x0000. Table 17. Bits 0 Bit Name DDS reset Description Reset of the direct digital synthesis block. Reset of this block is very seldom needed. Register 0x0013—Reset (Continued) (Not Autoclearing) Table 18.
AD9912 CMOS OUTPUT DIVIDER (S-DIVIDER) (REGISTER 0x0100 TO REGISTER 0x0106) Register 0x0100 to Register 0x0103—Reserved Register 0x0104—S-Divider Table 21. Bits [7:0] Bit Name S-divider Description CMOS output divider. Divide ratio = 1 − 65,536. If the desired S-divider setting is greater than 65,536, or if the signal on FDBK_IN is greater than 400 MHz, then Bit 0 in Register 0x0106 must be set.
AD9912 Register 0x01A9—FTW0 (Frequency Tuning Word) (Continued) Table 27. Bits [31:24] Bit Name FTW0 Description These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio of the AD9912 output frequency to its DAC system clock. Register 0x01A6 is the least significant byte of the FTW. Note that the power-up default is defined by start-up Pin S1 to Pin S4. Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity.
AD9912 DOUBLER AND OUTPUT DRIVERS (REGISTER 0x0200 TO REGISTER 0x0201) Register 0x0200—HSTL Driver Table 32. Bits 4 [3:2] [1:0] Bit Name OPOL Reserved HSTL output doubler Description Output polarity. Setting this bit inverts the HSTL driver output polarity. Reserved. HSTL output doubler. 01 = doubler disabled. 10 = doubler enabled. When using doubler, Bit 5 in Register 0x0010 must also be set to 1. Register 0x0201—CMOS Driver Table 33.
AD9912 Register 0x0503—Spur A (Continued) Table 38. Bits [7:0] Bit Name Spur A phase Description Linear offset for Spur B phase. Register 0x0504—Spur A (Continued) Table 39. Bits [8] Bit Name Spur A phase Description Linear offset for Spur A phase. Register 0x0505—Spur B Table 40. Bits 7 6 [5:4] [3:0] Bit Name HSR-B enable Amplitude gain × 2 Reserved Spur B harmonic Description Harmonic Spur Reduction B enable.
AD9912 OUTLINE DIMENSIONS 9.00 BSC SQ 0.60 MAX 33 32 16 17 7.50 REF 0.80 MAX 0.65 TYP 0.50 BSC 0.20 REF 082908-B FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM SEATING PLANE *4.85 4.70 SQ 4.55 EXPOSED PAD (BOTTOM VIEW) 0.50 0.40 0.30 12° MAX 1 8.75 BSC SQ TOP VIEW PIN 1 INDICATOR 64 49 48 PIN 1 INDICATOR 1.00 0.85 0.80 0.30 0.25 0.18 0.
AD9912 ORDERING GUIDE Model AD9912ABCPZ1, 2 AD9912ABCPZ-REEL71, 2 AD9912BCPZ1 AD9912BCPZ-REEL71 AD9912A/PCBZ1, 2 AD9912/PCBZ1 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Evaluation Board Z = RoHS Compliant Part.
AD9912 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06763-0-11/09(D) Rev.
