Specifications

VLSI
Solution
y
VS1053b
VS1053B
10. VS1053B REGISTERS
10.11.3 Configuration TIMER ENABLE
TIMER ENABLE Bits
Name Bits Description
TIMER EN T1 1 Enable timer 1
TIMER EN T0 0 Enable timer 0
10.11.4 Timer X Startvalue TIMER Tx[L/H]
The 32-bit start value TIMER Tx[L/H] sets the initial counter value when the timer is reset. The timer
interrupt frequency f
t
=
f
i
c+1
where f
i
is the master clock obtained with the clock divider (see Chap-
ter 10.11.2 and c is TIMER Tx[L/H].
Example: With a 12 MHz master clock and with TIMER CF CLKDIV=3, the master clock f
i
= 3MHz.
If TIMER TH=0, TIMER TL=99, then the timer interrupt frequency f
t
=
3MHz
99+1
= 30kHz.
10.11.5 Timer X Counter TIMER TxCNT[L/H]
TIMER TxCNT[L/H] contains the current counter values. By reading this register pair, the user may get
knowledge of how long it will take before the next timer interrupt. Also, by writing to this register, a
one-shot different length timer interrupt delay may be realized.
10.11.6 Interrupts
Each timer has its own interrupt, which is asserted when the timer counter underflows.
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