Specifications

VLSI
Solution
y
VS1053b
VS1053B
10. VS1053B REGISTERS
10.10 UART v1.1 2004-10-09
RS232 UART implements a serial interface using rs232 standard.
Start
bit
D0
D1 D2 D3
D4
D5
D6 D7
Stop
bit
Figure 15: RS232 Serial Interface Protocol
When the line is idling, it stays in logic high state. When a byte is transmitted, the transmission begins
with a start bit (logic zero) and continues with data bits (LSB first) and ends up with a stop bit (logic
high). 10 bits are sent for each 8-bit byte frame.
10.10.1 Registers
UART registers, prefix UARTx
Reg Type Reset Abbrev Description
0xC028 r 0 STATUS[4:0] Status
0xC029 r/w 0 DATA[7:0] Data
0xC02A r/w 0 DATAH[15:8] Data High
0xC02B r/w 0 DIV Divider
10.10.2 Status UARTx STATUS
A read from the status register returns the transmitter and receiver states.
UARTx STATUS Bits
Name Bits Description
UART ST FRAMEERR 4 Framing error (stop bit was 0)
UART ST RXORUN 3 Receiver overrun
UART ST RXFULL 2 Receiver data register full
UART ST TXFULL 1 Transmitter data register full
UART ST TXRUNNING 0 Transmitter running
UART ST FRAMEERR is set if the stop bit of the received byte was 0.
UART ST RXORUN is set if a received byte overwrites unread data when it is transferred from the
receiver shift register to the data register, otherwise it is cleared.
UART ST RXFULL is set if there is unread data in the data register.
UART ST TXFULL is set if a write to the data register is not allowed (data register full).
UART ST TXRUNNING is set if the transmitter shift register is in operation.
Version 1.01, 2008-05-22 70