Specifications

VLSI
Solution
y
VS1053b
VS1053B
10. VS1053B REGISTERS
10.5 Serial Data Registers
SDI registers, prefix SER
Reg Type Reset Abbrev[bits] Description
0xC011 r 0 DATA Last received 2 bytes, big-endian
0xC012 w 0 DREQ[0] DREQ pin control
10.6 DAC Registers
DAC registers, prefix DAC
Reg Type Reset Abbrev[bits] Description
0xC013 rw 0 FCTLL DAC frequency control, 16 LSbs
0xC014 rw 0 FCTLH DAC frequency control 4MSbs, PLL control
0xC015 rw 0 LEFT DAC left channel PCM value
0xC016 rw 0 RIGHT DAC right channel PCM value
Every fourth clock cycle, an internal 26-bit counter is added to by (DAC FCTLH & 15) × 65536 +
DAC FCTLL. Whenever this counter overflows, values from DAC LEFT and DAC RIGHT are read and
a DAC interrupt is generated.
10.7 GPIO Registers
GPIO registers, prefix GPIO
Reg Type Reset Abbrev[bits] Description
0xC017 rw 0 DDR[7:0] Direction
0xC018 r 0 IDATA[7:0] Values read from the pins
0xC019 rw 0 ODATA[7:0] Values set to the pins
GPIO DIR is used to set the direction of the GPIO pins. 1 means output. GPIO ODATA remembers its
values even if a GPIO DIR bit is set to input.
GPIO registers don’t generate interrupts.
Note that in VS1053b the VSDSP registers can be read and written through the SCI WRAMADDR and
SCI WRAM registers. You can thus use the GPIO pins quite conveniently.
Version 1.01, 2008-05-22 67