Datasheet

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics
PARAMETER TEST CONDITIONS
T
J
TPS7301Q, TPS7333Q
TPS7348Q, TPS7350Q
UNIT
J
MIN TYP MAX
RESET time out delay
See Figure 5
25°C 140 200 260
ms
RESET
ti
me-ou
t
d
e
l
ay
See
Fig
u
re
5
–40°C to 125°C 100 300
ms
electrical characteristics at I
O
= 10 mA, EN = 0 V, C
o
= 4.7 µF (CSR
†
= 1 Ω), T
J
= 25°C, SENSE/FB
shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS
‡
TPS7301Y, TPS7333Y
TPS7348Y, TPS7350Y
UNIT
MIN TYP MAX
Ground current (active mode)
EN ≤ 0.5 V,
0 mA ≤ I
O
≤ 500 mA
V
I
= V
O
+ 1 V,
340 µA
Input current (standby mode)
EN = V
I
, 2.7 V ≤ V
I
≤ 10 V
0.01 µA
Output current limit V
O
= 0 V, V
I
= 10 V 1.2 A
Pass-element leakage current in standby mode
EN = V
I
, 2.7 V ≤ V
I
≤ 10 V
0.01 µA
RESET leakage current
Normal operation, V at RESET = 10 V
0.02 µA
Thermal shutdown junction temperature 165 °C
EN logic low (active mode)
2.7 V ≤ V
I
≤ 10 V 0.5 V
EN hysteresis voltage 50 mV
EN input current
0 V ≤ V
I
≤ 10 V 0.001 µA
Minimum V
I
for active pass element 2.05 V
Minimum V
I
for valid RESET
I
O(RESET)
= –300 µA 1 V
†
CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to C
o
.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.