Datasheet

EMIF_nCS[3:2]
25
Asserted
2
2
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
EMIF_nWE
EMIF_WAIT
SETUP
Extended Due to EMIF_WAIT
28
Deasserted
STROBE STROBE HOLD
RM46L450
RM46L850
www.ti.com SPNS184A –SEPTEMBER 2012–REVISED SEPTEMBER 2013
Figure 4-15. EMIFnWAIT Write Timing Requirements
Table 4-28. EMIF Asynchronous Memory Timing Requirements
NO. Value Unit
MIN NOM MAX
Reads and Writes
E EMIF clock period 10 ns
2 t
w(EM_WAIT)
Pulse duration, EMIFnWAIT 2E ns
assertion and deassertion
Reads
12 t
su(EMDV-EMOEH)
Setup time, EMIFDATA[15:0] 30 ns
valid before EMIFnOE high
13 t
h(EMOEH-EMDIV)
Hold time, EMIFDATA[15:0] 0.5 ns
valid after EMIFnOE high
14 t
su(EMOEL-EMWAIT)
Setup Time, EMIFnWAIT 4E+30 ns
asserted before end of Strobe
Phase
(1)
Writes
28 t
su(EMWEL-EMWAIT)
Setup Time, EMIFnWAIT 4E+30 ns
asserted before end of Strobe
Phase
(1)
(1) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended
wait states. Figure Figure 4-13 and Figure Figure 4-15 describe EMIF transactions that include extended wait states inserted during the
STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start
of where the HOLD phase would begin if there were no extended wait cycles.
Table 4-29. EMIF Asynchronous Memory Switching Characteristics
(1)(2)(3)
NO Parameter Value Unit
MIN NOM MAX
Reads and Writes
1 t
d(TURNAROUND)
Turn around time (TA)*E - 4 (TA)*E (TA)*E + 3 ns
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1], WST[64–1],
WH[8–1], and MEWC[1–256]. See the RM48x Technical Reference Manual (SPNU503) for more information.
(2) E = EMIF_CLK period in ns.
(3) EWC = external wait cycles determined by EMIFnWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note
that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See
the RM48x Technical Reference Manual (SPNU503) for more information.
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