Datasheet
Table Of Contents
- Title Page - SLWS106H
- IMPORTANT NOTICE
- Contents
- List of Illustrations
- 1 Introduction
- 2 Specifications
- 2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)†
- 2.2 Recommended Operating Conditions
- 2.3 Electrical Characteristics Over Recommended Operating Conditions, AVDD, HPVDD, BVDD = 3.3 V, DVDD = 1.5 V, Slave Mode, XTI/ MCLK = 256fs, fs = 48 kHz ( unless otherwise stated)
- 2.4 Digital-Interface Timing
- 3 How to Use the TLV320AIC23B
- Appendix A: Mechanical Data
1−6
1.5 Terminal Functions (continued)
TERMINAL
NO.
I/O
DESCRIPTION
NAME
GQE/
ZQE
PW RHD
I/O
DESCRIPTION
SCLK 15 24 21 I Control-port serial-data clock. For SPI and 2-wire control modes this is the serial-clock input.
See Section 3.1 for details.
SDIN 14 23 20 I Control-port serial-data input. For SPI and 2-wire control modes this is the serial-data input and
also is used to select the control protocol after reset. See Section 3.1 for details.
VMID 6 16 13 I Midrail voltage decoupling input. 10-µF and 0.1-µF capacitors should be connected in parallel to
this terminal for noise filtering. Voltage level is 1/2 AVDD nominal.
XTI/MCLK 16 25 22 I Crystal or external-clock input. Used for derivation of all internal clocks on the AIC23B.
XTO 18
26 23 O Crystal output. Connect to external crystal for applications where the AIC23B is the audio timing
master. Not used in applications where external clock source is used.