Datasheet

TLC1514, TLC1518
5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS252 – DECEMBER 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
control and timing (continued)
configuration
Configuration data is stored in one 12-bit configuration register (CFR) (see Table 2 for CFR bit definitions). Once
configured after first power up, the information is retained in the H/W or S/W power-down state. When the device
is being configured, a write CFR cycle is issued by the host processor. This is a 16-bit write. (If the SCLK stops
after the first 8 bits are entered, then the next eight bits can be taken after the SCLK is resumed.) The status
of the CFR can be read with a read CFR command when the device is programmed for one-shot conversion
mode (CFR.D[6,5] = 00).
Table 2. TLC1514/TLC1518 Configuration Register (CFR) Bit Definitions
BIT DEFINITION
D(15–12) All zeros, nonprogrammable
D11 Reference select
0: External
1: Internal
D10 Output select
0: Unipolar straight binary
1: 2’s complement
D9 Sample period select
0: Short sampling 12 SCLKs (1x sampling time)
1: Long sampling 24 SCLKs (2x sampling time)
D8 Conversion clock source select
0: Conversion clock = SCLK
1: Conversion clock = SCLK/2
D7 Input select
0: Normal
1: Pseudo differential CH A2(1518) or CH A1 (1514) is the differential input
D(6,5) Conversion mode select
00: Single shot mode (single conversion from selected channel)
01: Repeat mode (repeated conversions from selected channel)
10: Sweep mode (single conversion on each channel in selected sequence)
11: Repeat sweep mode (repeated conversions on selected sequence)
D(4,3)
†
TLC1518 TLC1514
Sweep auto sequence select
00: 0–1–2–3–4–5–6–7
01: 0–2–4–6–0–2–4–6
10: 0–0–2–2–4–4–6–6
11: 0–2–0–2–0–2–0–2
Sweep auto sequence select
00: N/A
01: 0–1–2–3–0–1–2–3
10: 0–0–1–1–2–2–3–3
11: 0–1–0–1–0–1–0–1
D2 EOC/INT – pin function select
0: Pin used as INT
1: Pin used as EOC
D(1,0) FIFO trigger level (sweep sequence length)
00: Full (INT
generated after FIFO level 7 filled)
01: 3/4 (INT
generated after FIFO level 5 filled)
10: 1/2 (INT
generated after FIFO level 3 filled)
11: 1/4 (INT
generated after FIFO level 1 filled)
†
These bits only take effect in conversion modes 10 and 11.
sampling
The sampling period starts after the first 4 input data are shifted in if they are decoded as one of the conversion
commands. These are select analog input (channel 0 through 7) and select test (channel 1 through 3).