Datasheet

 
   

SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
Figure 49
Package With
θ
JA
≤ 64°C/W
SO-8 Package
θ
JA
= 98°C/W
High-K Test PCB
V
CC
= ± 5 V
T
J
= 150°C
T
A
= 50°C
Both Channels
100
80
40
0
012 3
− Maximum RMS Output Current − mA
140
180
200
45
160
120
60
20
| V
O
| − RMS Output Voltage − V
I
O
||
Maximum Output
Current Limit Line
THS4082
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
SO-8 Package
θ
JA
= 167°C/W
Low-K Test PCB
Safe Operating Area
Figure 50
100
10
0369
1000
12 15
Maximum Output
Current Limit Line
| V
O
| − RMS Output Voltage − V
− Maximum RMS Output Current − mA
I
O
||
V
CC
= ± 15 V
T
J
= 150°C
T
A
= 50°C
Both Channels
THS4082
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1
SO-8 Package
θ
JA
= 167°C/W
Low-K Test PCB
DGN Package
θ
JA
= 58.4°C/W
Safe Operating Area
SO-8 Package
θ
JA
= 98°C/W
High-K Test PCB