Datasheet

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SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD
 design considerations (continued)
The actual thermal performance achieved with the THS408xDGN in its PowerPAD package depends on the
application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches,
then the expected thermal coefficient, θ
JA
, is about 58.4_C/W. For comparison, the non-PowerPAD version
of the THS408x IC (SOIC) is shown. For a given θ
JA
, the maximum power dissipation is shown in Figure 46 and
is calculated by the following formula:
P
D
+
ǒ
T
MAX
–T
A
q
JA
Ǔ
Where:
P
D
= Maximum power dissipation of THS408x IC (watts)
T
MAX
= Absolute maximum junction temperature (150°C)
T
A
= Free-ambient air temperature (°C)
θ
JA
= θ
JC
+ θ
CA
θ
JC
= Thermal coefficient from junction to case
θ
CA
= Thermal coefficient from case to ambient air (°C/W)
DGN Package
θ
JA
= 58.4°C/W
2 oz. Trace And Copper Pad
With Solder
DGN Package
θ
JA
= 158°C/W
2 oz. Trace And
Copper Pad
Without Solder
SOIC Package
High-K Test PCB
θ
JA
= 98°C/W
T
J
= 150°C
SOIC Package
Low-K Test PCB
θ
JA
= 167°C/W
2
1.5
1
0
−40 −20 0 20 40
Maximum Power Dissipation − W
2.5
3
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
3.5
60 80 100
0.5
T
A
− Free-Air Temperature − °C
NOTE A: Results are with no air flow and PCB size = 3”× 3”
Figure 46. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package. This document can be
found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be
ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.