Datasheet
Table Of Contents
- features
- description
- DEVELOPMENT TOOL SUPPORT
- pin designation, MSP430x4351IPN, MSP430x4361IPN, MSP430x4371IPN
- pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x4371IPZ
- pin designation, MSP430x435IPN, MSP430x436IPN, MSP430x437IPN
- pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x437IPZ
- pin designation, MSP430x4481IPZ, MSP430x4491IPZ
- pin designation, MSP430x447IPZ, MSP430x448IPZ, MSP430x449IPZ
- MSP430x43x1 functional block diagram
- MSP430x43x functional block diagram
- MSP430x44x1 functional block diagram
- MSP430x44x functional block diagram
- MSP430x43x1 Terminal Functions
- MSP430x43x Terminal Functions
- MSP430x44x1 Terminal Functions
- MSP430x44x Terminal Functions
- short-form description
- CPU
- instruction set
- operating modes
- interrupt vector addresses
- special function registers
- interrupt enable 1 and 2
- interrupt flag register 1 and 2
- module enable registers 1 and 2
- memory organization
- bootstrap loader (BSL)
- flash memory
- peripherals
- digital I/O
- oscillator and system clock
- brownout, supply voltage supervisor (SVS)
- hardware multiplier (MSP430x44x(1) only)
- watchdog timer (WDT)
- USART0
- USART1 (MSP430x44x(1) only)
- Timer_A3
- Timer_B3 (MSP430x43x(1) only)
- Timer_B7 (MSP430x44x(1) only)
- Comparator_A
- ADC12 (not implemented in MSP430x43x1 and MSP430x44x1)
- Basic Timer1
- LCD driver
- peripheral file map
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC excluding external current
- Schmitt-trigger inputs - ports P1, P2, P3, P4, P5, P6
- standard inputs - RST/NMI, JTAG (TCK, TMS, TDI/TCLK)
- inputs Px.x, TAx, TBx
- leakage current
- outputs - ports P1, P2, P3, P4, P5, P6
- output frequency
- wake-up LPM3
- RAM
- LCD
- Comparator_A
- POR/brownout reset (BOR)
- supply voltage supervisor/monitor (SVS)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USART0, USART1
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- flash memory
- JTAG interface
- JTAG fuse
- APPLICATION INFORMATION
- input/output schematics
- port P1, P1.0 to P1.5, input/output with Schmitt trigger
- port P1, P1.6, P1.7, input/output with Schmitt trigger
- port P2, P2.0, P2.4 to P2.5, input/output with Schmitt trigger
- port P2, P2.1 to P2.3, input/output with Schmitt trigger
- port P2, P2.6 to P2.7, input/output with Schmitt trigger
- port P3, P3.0 to P3.3, input/output with Schmitt trigger
- port P3, P3.4 to P3.7, input/output with Schmitt trigger
- port P4, P4.0 to P4.7, input/output with Schmitt trigger
- port P5, P5.0 to P5.1, input/output with Schmitt trigger
- port P5, P5.2 to P5.4, input/output with Schmitt trigger
- port P5, P5.5 to P5.7, input/output with Schmitt trigger
- port P6, P6.0 to P6.6, input/output with Schmitt trigger
- port P6, P6.0 to P6.6, input/output with Schmitt trigger
- port P6, P6.7, input/output with Schmitt trigger
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
- JTAG fuse check mode
- input/output schematics
- Data Sheet Revision History
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
46
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical characteristics (Continued)
V
CC
0
0.5
1
1.5
2
V
CC(drop)
t
pw
t
pw
− Pulse Width − µs
3 V
0.001 1 1000
t
f
t
r
t
pw
− Pulse Width − µs
t
f
= t
r
Typical Conditions
V
CC
= 3 V
V
CC(drop)
− V
Figure 12. V
CC(drop)
Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
supply voltage supervisor/monitor (SVS)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
t
dV
CC
/dt > 30 V/ms (see Figure 13) 5 150 µs
t
(SVSR)
dV
CC
/dt ≤ 30 V/ms 2000 µs
t
d(SVSon)
SVSon, switch from VLD=0 to VLD ≠ 0, V
CC
= 3 V 20 150 µs
t
settle
VLD ≠ 0
‡
12 µs
V
(SVSstart)
VLD ≠ 0, V
CC
/dt ≤ 3 V/s (see Figure 13) 1.55 1.7 V
VLD = 1 70 120 155 mV
V
h
y
s
(
SVS_IT−
)
V
CC
/dt ≤ 3 V/s (see Figure 13)
VLD = 2 to 14
V
(SVS_IT−)
× 0.004
V
(SVS_IT−)
× 0.008
V
hys(SVS
_
IT
−
)
V
CC
/dt ≤ 3 V/s (see Figure 13),
external voltage applied on A7
VLD = 15 4.4 10.4 mV
VLD = 1 1.8 1.9 2.05
VLD = 2 1.94 2.1 2.25
VLD = 3 2.05 2.2 2.37
VLD = 4 2.14 2.3 2.48
VLD = 5 2.24 2.4 2.6
VLD = 6 2.33 2.5 2.71
V /dt ≤ 3 V/s (see Figure 13)
VLD = 7 2.46 2.65 2.86
V
(SVS IT )
V
CC
/dt ≤ 3 V/s (see Figure 13)
VLD = 8 2.58 2.8 3
V
V
(SVS_IT−)
VLD = 9 2.69 2.9 3.13
V
VLD = 10 2.83 3.05 3.29
VLD = 11 2.94 3.2 3.42
VLD = 12 3.11 3.35 3.61
†
VLD = 13 3.24 3.5 3.76
†
VLD = 14 3.43 3.7
†
3.99
†
V
CC
/dt ≤ 3 V/s (see Figure 13),
external voltage applied on A7
VLD = 15 1.1 1.2 1.3
I
CC(SVS)
(see Note 3)
VLD ≠ 0, V
CC
= 2.2 V/3 V 10 15 µA
†
The recommended operating voltage range is limited to 3.6 V.
‡
t
settle
is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 3: The current consumption of the SVS module is not included in the I
CC
current consumption data.