Datasheet
Table Of Contents
- features
- description
- DEVELOPMENT TOOL SUPPORT
- pin designation, MSP430x4351IPN, MSP430x4361IPN, MSP430x4371IPN
- pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x4371IPZ
- pin designation, MSP430x435IPN, MSP430x436IPN, MSP430x437IPN
- pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x437IPZ
- pin designation, MSP430x4481IPZ, MSP430x4491IPZ
- pin designation, MSP430x447IPZ, MSP430x448IPZ, MSP430x449IPZ
- MSP430x43x1 functional block diagram
- MSP430x43x functional block diagram
- MSP430x44x1 functional block diagram
- MSP430x44x functional block diagram
- MSP430x43x1 Terminal Functions
- MSP430x43x Terminal Functions
- MSP430x44x1 Terminal Functions
- MSP430x44x Terminal Functions
- short-form description
- CPU
- instruction set
- operating modes
- interrupt vector addresses
- special function registers
- interrupt enable 1 and 2
- interrupt flag register 1 and 2
- module enable registers 1 and 2
- memory organization
- bootstrap loader (BSL)
- flash memory
- peripherals
- digital I/O
- oscillator and system clock
- brownout, supply voltage supervisor (SVS)
- hardware multiplier (MSP430x44x(1) only)
- watchdog timer (WDT)
- USART0
- USART1 (MSP430x44x(1) only)
- Timer_A3
- Timer_B3 (MSP430x43x(1) only)
- Timer_B7 (MSP430x44x(1) only)
- Comparator_A
- ADC12 (not implemented in MSP430x43x1 and MSP430x44x1)
- Basic Timer1
- LCD driver
- peripheral file map
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC excluding external current
- Schmitt-trigger inputs - ports P1, P2, P3, P4, P5, P6
- standard inputs - RST/NMI, JTAG (TCK, TMS, TDI/TCLK)
- inputs Px.x, TAx, TBx
- leakage current
- outputs - ports P1, P2, P3, P4, P5, P6
- output frequency
- wake-up LPM3
- RAM
- LCD
- Comparator_A
- POR/brownout reset (BOR)
- supply voltage supervisor/monitor (SVS)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USART0, USART1
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- flash memory
- JTAG interface
- JTAG fuse
- APPLICATION INFORMATION
- input/output schematics
- port P1, P1.0 to P1.5, input/output with Schmitt trigger
- port P1, P1.6, P1.7, input/output with Schmitt trigger
- port P2, P2.0, P2.4 to P2.5, input/output with Schmitt trigger
- port P2, P2.1 to P2.3, input/output with Schmitt trigger
- port P2, P2.6 to P2.7, input/output with Schmitt trigger
- port P3, P3.0 to P3.3, input/output with Schmitt trigger
- port P3, P3.4 to P3.7, input/output with Schmitt trigger
- port P4, P4.0 to P4.7, input/output with Schmitt trigger
- port P5, P5.0 to P5.1, input/output with Schmitt trigger
- port P5, P5.2 to P5.4, input/output with Schmitt trigger
- port P5, P5.5 to P5.7, input/output with Schmitt trigger
- port P6, P6.0 to P6.6, input/output with Schmitt trigger
- port P6, P6.0 to P6.6, input/output with Schmitt trigger
- port P6, P6.7, input/output with Schmitt trigger
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
- JTAG fuse check mode
- input/output schematics
- Data Sheet Revision History
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Timer_B7 (MSP430x44x(1) only)
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_B3/B7 SIGNAL CONNECTIONS
†
INPUT PIN NUMBER
DEVICE INPUT MODULE INPUT MODULE
MODULE
OUTPUT
OUTPUT PIN NUMBER
PN PZ
DEVICE
INPUT
SIGNAL
MODULE
INPUT
NAME
MODULE
BLOCK
OUTPUT
SIGNAL
PN PZ
63 - P1.4 83 - P1.4 TBCLK TBCLK
ACLK ACLK
Timer
NA
SMCLK SMCLK
Timer NA
63 - P1.4 83 - P1.4 TBCLK INCLK
58 - P2.1 78 - P2.1 TB0 CCI0A
58 - P2.1 78 - P2.1
58 - P2.1 78 - P2.1 TB0 CCI0B
CCR0
†
TB0
ADC12 (internal)
‡
DV
SS
GND
CCR0
†
TB0
DV
CC
V
CC
57 - P2.2 77 - P2.2 TB1 CCI1A
57 - P2.2 77 - P2.2
57 - P2.2 77 - P2.2 TB1 CCI1B
CCR1
†
TB1
ADC12 (internal)
‡
DV
SS
GND
CCR1
†
TB1
DV
CC
V
CC
56 - P2.3 76 - P2.3 TB2 CCI2A
56 - P2.3 76 - P2.3
56 - P2.3 76 - P2.3 TB2 CCI2B
CCR2
†
TB2
DV
SS
GND
CCR2
†
TB2
DV
CC
V
CC
67 - P3.4 TB3 CCI3A
67 - P3.4
67 - P3.4 TB3 CCI3B
CCR3
TB3
DV
SS
GND
CCR3 TB3
DV
CC
V
CC
66 - P3.5 TB4 CCI4A
66 - P3.5
66 - P3.5 TB4 CCI4B
CCR4
TB4
DV
SS
GND
CCR4 TB4
DV
CC
V
CC
65 - P3.6 TB5 CCI5A
65 - P3.6
65 - P3.6 TB5 CCI5B
CCR5
TB5
DV
SS
GND
CCR5 TB5
DV
CC
V
CC
64 - P3.7 TB6 CCI6A
64 - P3.7
ACLK (internal) CCI6B
CCR6
TB6
DV
SS
GND
CCR6 TB6
DV
CC
V
CC
†
Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only).
‡
Not implemented in MSP430x43x1 and MSP430x44x1 devices.