Datasheet

FB
SW
L1
R1
1.0k
LM25010
BST
VCC
C3
C4
D1
V
OUT
ISEN
SGND
SS
RTN
0.47 PF
5V
GND
13
11
10
9
6
5
4
2
3
12
0.022 PF
R2
1.0k
R3
1.5
C2
22 PF
C6
0.022 PF
C1
4.4 PF
C5
0.1 PF
R
ON
200k
100 PH
6 - 40V
Input
VIN
RON/SD
C6 =
2.5V
t
SS
x 11.5 PA
LM25010
SNVS419D –DECEMBER 2005–REVISED FEBRUARY 2013 www.ti.com
C3: The capacitor at the VCC pin provides noise filtering and stability, prevents false triggering of the V
CC
UVLO
at the buck switch on/off transitions, and limits the peak voltage at V
CC
when a high voltage with a short rise time
is initially applied at V
IN
. C3 should be no smaller than 0.47 µF, and should be a good quality, low ESR, ceramic
capacitor, physically close to the IC pins.
C4: The recommended value for C4 is 0.022 µF. A high quality ceramic capacitor with low ESR is recommended
as C4 supplies the surge current to charge the buck switch gate at each turn-on. A low ESR also ensures a
complete recharge during each off-time.
C5: This capacitor suppresses transients and ringing due to lead inductance at VIN. A low ESR, 0.1 µF ceramic
chip capacitor is recommended, located physically close to the LM25010.
C6: The capacitor at the SS pin determines the soft-start time, i.e. the time for the reference voltage at the
regulation comparator, and the output voltage, to reach their final value. The capacitor value is determined from
the following:
(22)
For a 5 ms softstart time, C6 calculates to 0.022 µF.
D1: A Schottky diode is recommended. Ultra-fast recovery diodes are not recommended as the high speed
transitions at the SW pin may inadvertently affect the IC’s operation through external or internal EMI. The diode
should be rated for the maximum V
IN
(40V), the maximum load current (1A), and the peak current which occurs
when current limit and maximum ripple current are reached simultaneously (I
PK
in Figure 10), previously
calculated to be 1.86A. The diode’s forward voltage drop affects efficiency due to the power dissipated during the
off-time. The average power dissipation in D1 is calculated from:
P
D1
= V
F
× I
O
× (1 – D) (23)
where I
O
is the load current, and D is the duty cycle.
Final Circuit
The final circuit is shown in Figure 12, and its performance is shown in Figures 7 and 8. Current limit measured
approximately 1.3A.
Figure 12. Example Circuit
ITEM DESCRIPTION VALUE
C1 Ceramic Capacitor (2) 2.2 µF, 50V
C2 Ceramic Capacitor 22 µF, 16V
C3 Ceramic Capacitor 0.47 µF, 16V
C4, C6 Ceramic Capacitor 0.022 µF, 16V
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