Datasheet

t
HD, STA
t
SU, DAT
t
HD, DAT
t
SU, STA
t
SU, STO
t
HD,STA
t
LOW
t
HIGH
t
R
t
F
t
BUF
SDA
SCL
S Sr P S
S=STARTCondition
Sr=RepeatedSTARTCondition
P=STOPCondition
=ResistorPull-Up
AMC7812
SBAS513E –JANUARY 2011–REVISED SEPTEMBER 2013 www.ti.com
I
2
C-COMPATIBLE TIMING DIAGRAMS
Figure 1. Timing for Standard and Fast Mode Devices on the I
2
C Bus
TIMING CHARACTERISTICS: SDA and SCL for Standard and Fast Modes
(1)
At –40°C to +105°C, AV
DD
= DV
DD
= 4.5V to 5.5V, AGND = DGND = 0V, and IOV
DD
= 2.7V to 5.5V, unless otherwise noted.
STANDARD FAST
MODE MODE
PARAMETER MIN MAX MIN MAX UNIT
f
SCL
(2)
SCL clock frequency 0 100 0 400 kHz
t
LOW
Low period of the SCL clock 4.7 — 1.3 — µs
t
HIGH
High period of the SCL clock 4.0 — 0.6 — µs
t
SU, STA
Set-up time for a repeated start condition 4.7 — 0.6 — µs
Hold time (repeated) start condition. After this
t
HD, STA
4.0 — 0.6 — µs
period, the first clock pulse is generated
t
SU, DAT
Data set-up time 250 — 100 — ns
t
HD, DAT
Data hold time: for I
2
C-bus devices 0 3.45 0 0.9 µs
t
SU, STO
Set-up time for stop condition 4.0 — 0.6 — µs
t
R
Rise time of both SDA and SCL signals — 1000 20 + 0.1C
B
(3)
300 ns
t
F
Fall time of both SDA and SCL signals — 300 20 + 0.1C
B
(3)
300 ns
t
BUF
Bus free time between a stop and start condition 4.7 — 1.3 — µs
C
B
Capacitive load for each bus line — 400 — 400 pF
t
SP
Pulse width of spike suppressed NA NA 0 50 ns
(1) All values refer to V
IHmin
and V
ILmax
levels.
(2) An SCL operating frequency of at least 1kHz is recommended to avoid activating the I
2
C timeout function. See the Timeout Function
section for details.
(3) C
B
= total capacitance of one bus line in pF.
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