Datasheet

ADS8345
SBAS177C
12
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There are several critical items concerning the reference
input and its wide-voltage range. As the reference voltage is
reduced, the analog voltage weight of each digital output
code is also reduced. This is often referred to as the LSB
(Least Significant Bit) size and is equal to the reference
voltage divided by 65536. Any offset or gain error inherent in
the A/D converter will appear to increase, in terms of LSB
size, as the reference voltage is reduced. For example, if the
offset of a given converter is 2LSBs with a 2.5V reference,
then it will typically be 10LSBs with a 0.5V reference. In each
case, the actual offset of the device is the same, 152.8µV.
The noise or uncertainty of the digitized output will increase
with lower LSB size. With a reference voltage of 500mV, the
LSB size is 15.3µV. This level is below the internal noise of
the device. As a result, the digital output code will not be
stable and will vary around a mean value by a number of
LSBs. The distribution of output codes will be gaussian and
the noise can be reduced by simply averaging consecutive
conversion results or applying a digital filter.
With a lower reference voltage, care should be taken to
provide a clean layout including adequate bypassing, a clean
(low-noise, low-ripple) power supply, a low-noise reference,
and a low-noise input signal. Because the LSB size is lower,
the converter will also be more sensitive to nearby digital
signals and electromagnetic interference.
The voltage into the V
REF
input is not buffered and directly
drives the Capacitor Digital-to-Analog Converter (CDAC)
portion of the ADS8345. Typically, the input current is 13µA
with a 2.5V reference. This value will vary by microamps
depending on the result of the conversion. The reference
current diminishes directly with both conversion rate and
reference voltage. As the current from the reference is drawn
on each bit decision, clocking the converter more quickly
during a given conversion period will not reduce overall
current drain from the reference.
DIGITAL INTERFACE
The ADS8345 has a 4-wire serial interface compatible with
several microprocessor families (note that the digital inputs are
over-voltage tolerant up to +5.5V, regardless of +V
CC
). Figure 6
shows the typical operation of the ADS8345 digital interface.
Most microprocessors communicate using 8-bit transfers; the
ADS8345 can complete a conversion with three such trans-
fers, for a total of 24 clock cycles on the DCLK input,
provided the timing is as shown in Figure 6.
The first eight clock cycles are used to provide the control
byte via the D
IN
pin. When the converter has enough informa-
tion about the following conversion to set the input multi-
plexer appropriately, it enters the acquisition (sample) mode.
After four more clock cycles, the control byte is complete and
the converter enters the conversion mode. At this point, the
input sample-and-hold goes into the Hold mode. The next
sixteen clock cycles accomplish the actual A/D conversion.
Control Byte
Figure 6 shows placement and order of the control bits within
the control byte. Tables I and II give detailed information
about these bits. The first bit, the “S” bit, must always be
HIGH and indicates the start of the control byte. The ADS8345
will ignore inputs on the D
IN
pin until the START bit is
detected. The next three bits (A2-A0) select the active input
channel or channels of the input multiplexer (see Tables III
and IV and Figure 4).
FIGURE 6. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated
serial port.
t
ACQ
AcquireIdle Conversion
1 DCLK
CS
81
15
D
OUT
BUSY
(MSB)
(START)
(LSB)
A2S
D
IN
A1 A0
SGL/
DIF
PD1 PD0
14131211109 8 7654321 0 Zero Filled...
81 8
AcquireIdle Conversion
181
15
(MSB)
(START)
A2SA1A0
SGL/
DIF
PD1 PD0
14
BIT 7 BIT 0
(MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (LSB)
SA2A1A0— SGL/DIF PD1 PD0
TABLE I. Order of the Control Bits in the Control Byte.
TABLE II. Descriptions of the Control Bits within the Control Byte.
BIT NAME DESCRIPTION
7 S Start Bit. Control byte starts with first HIGH bit on
D
IN
.
6-4 A2-A0 Channel Select Bits. Along with the SGL/DIF bit,
these bits control the setting of the multiplexer input.
2 SGL/DIF Single-Ended/Differential Select Bit. Along with bits
A2-A0, this bit controls the setting of the multiplexer
input.
1-0 PD1-PD0 Power-Down Mode Select Bits. See Table V for
details.