Datasheet

ADS8345
SBAS177C
13
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The SGL/DIF-bit controls the multiplexer input mode:
either in single-ended mode, where the selected input chan-
nel is referenced to the COM pin, or in differential mode,
where the two selected inputs provide a differential input.
See Tables III and IV and Figure 4 for more information. The
last two bits (PD1-PD0) select the Power-Down mode and
Clock mode, as shown in Table V. If both PD1 and PD0 are
HIGH, the device is always powered up. If both PD1 and PD0
are LOW, the device enters a power-down mode between
conversions. When a new conversion is initiated, the device
will resume normal operation instantly—no delay is needed
to allow the device to power up and the very first conversion
will be valid.
FIGURE 7. Detailed Timing Diagram.
PD0
t
BDV
t
DH
t
CH
t
CL
t
DS
t
CSS
t
DV
t
BD
t
BD
t
TR
t
BTR
t
D0
t
CSH
DCLK
CS
15D
OUT
BUSY
D
IN
14
Clock Modes
The ADS8345 can be used with an external serial clock or an
internal clock to perform the successive-approximation con-
version. In both clock modes, the external clock shifts data in
and out of the device. Internal clock mode is selected when
PD1 is HIGH and PD0 is LOW.
If the user decides to switch from one clock mode to the
other, an extra conversion cycle will be required before the
ADS8345 can switch to the new mode. The extra cycle is
required because the PD0 and PD1 control bits need to be
written to the ADS8345 prior to the change in clock modes.
When power is first applied to the ADS8345, the user must
set the desired clock mode. It can be set by writing PD1 = 1
and PD0 = 0 for internal clock mode or PD1 = 1 and PD0
= 1 for external clock mode. After enabling the required clock
mode, only then should the ADS8345 be set to power-down
between conversions (i.e., PD1 = PD0 = 0). The ADS8345
maintains the clock mode it was in prior to entering the
power-down modes.
External Clock Mode
In external clock mode, the external clock not only shifts data
in and out of the ADS8345, it also controls the A/D conver-
sion steps. BUSY will go HIGH for one clock period after the
last bit of the control byte is shifted in. Successive-approxi-
mation bit decisions are made and appear at D
OUT
on each
of the next 16 DCLK falling edges (see Figure 6). Figure 7
shows the BUSY timing in external clock mode.
A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
00 0+IN–IN
00 1 +IN–IN
01 0 +IN–IN
01 1 +IN–IN
10 0–IN +IN
10 1 –IN +IN
11 0 –IN +IN
11 1 –IN +IN
TABLE IV. Differential Channel Control (SGL/DIF LOW).
TABLE III. Single-Ended Channel Selection (SGL/DIF
HIGH).
A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
00 0+IN –IN
10 0 +IN –IN
00 1 +IN –IN
10 1 +IN –IN
01 0 +IN –IN
11 0 +IN –IN
01 1 +IN –IN
11 1 +IN–IN
PD1 PD0 DESCRIPTION
0 0 Power-down between conversions. When each
conversion is finished, the converter enters a
low-power mode. At the start of the next conver-
sion, the device instantly powers up to full power.
There is no need for additional delays to assure full
operation and the very first conversion is valid.
1 0 Selects internal clock mode.
0 1 Reserved for future use.
1 1 No power-down between conversions, device al-
ways powered. Selects external clock mode.
TABLE V. Power-Down Selection.