Datasheet

Device in Hold Mode
AGND
150 W
+IN
−IN
AGND
+VA
150 W
4 pF
4 pF
40 pF
40 pF
Driver Amplifier Choice
Bipolar to Unipolar Driver
ADS8329
ADS8330
www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009
The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input
voltage, and source impedance. The current into the ADS8329/30 charges the internal capacitor array during the
sample period. After this capacitance has been fully charged, there is no further input current. The source of the
analog input voltage must be able to charge the input capacitance (45 pF) to a 16-bit settling level within the
minimum acquisition time (120 ns). When the converter goes into hold mode, the input impedance is greater than
1 G Ω .
Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN
and – IN inputs and the span [+IN – ( – IN)] should be within the limits specified. Outside of these ranges,
converter linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass
filters should be used. Care should be taken to ensure that the output impedance of the sources driving the +IN
and – IN inputs are matched. If this is not observed, the two inputs could have different settling times. This may
result in an offset error, gain error, and linearity error which change with temperature and input voltage.
Figure 51. Input Equivalent Circuit
The analog input to the converter needs to be driven with a low noise, op-amp like the THS4031 or OPA365. An
RC filter is recommended at the input pins to low-pass filter the noise from the source. Two resistors of 20 Ω and
a capacitor of 470 pF are recommended. The input to the converter is a unipolar input voltage in the range 0 V to
V
REF
. The minimum – 3dB bandwidth of the driving operational amplifier can be calculated to:
f
3db
= (ln(2) × (n+1))/(2 π × t
ACQ
)
where n is equal to 16, the resolution of the ADC (in the case of the ADS8329/30). When t
ACQ
= 120 ns
(minimum acquisition time), the minimum bandwidth of the driving amplifier is 15.6 MHz. The bandwidth can be
relaxed if the acquisition time is increased by the application. The OPA365, OPA827, or THS4031 from Texas
Instruments are recommended. The THS4031 used in the source follower configuration to drive the converter is
shown in the typical input drive configuration, Figure 52 . For the ADS8330, a series resistor of 0 Ω should be
used on the COM pin (or no resistor at all).
In systems where the input is bipolar, the THS4031 can be used in the inverting configuration with an additional
DC bias applied to its + input so as to keep the input to the ADS8329/30 within its rated operating voltage range.
This configuration is also recommended when the ADS8329/30 is used in signal processing applications where
good SNR and THD performance is required. The DC bias can be derived from the REF3225 or the REF3240
reference voltage ICs. The input configuration shown in Figure 53 is capable of delivering better than 91 dB SNR
and – 96 dB THD at an input frequency of 10 kHz. In case bandpass filters are used to filter the input, care should
be taken to ensure that the signal swing at the input of the bandpass filter is small so as to keep the distortion
introduced by the filter minimal. In such cases, the gain of the circuit shown in Figure 53 can be increased to
keep the input to the ADS8329/30 large to keep the SNR of the system high. Note that the gain of the system
from the + input to the output of the THS4031 in such a configuration is a function of the gain of the AC signal. A
resistor divider can be used to scale the output of the REF3225 or REF3240 to reduce the voltage at the DC
input to THS4031 to keep the voltage at the input of the converter within its rated operating range.
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Product Folder Link(s): ADS8329 ADS8330